Building the World’s Fastest 8-bit ADC - In CMOSpoulton.net/papers.public/2005_ims_adc.pdf ·...

1

est

13 June 2005Agilent Technologies

[ Workshop WMA ]

Building the World’s Fast8-bit ADC - In CMOS

Ken Poulton

Agilent Laboratories3500 Deer Creek Road

Palo Alto, CA 94306

2
Outline

■ Trends in CMOS ADCs

■ Massively Interleaved ADCs

● 4 GSa/s

● 20 GSa/s

3

C 1998-2005

1G 10G

ourtesy of Boris Murmann


ADC Dynamic Range vs. Input BW - ISSC

1k 10k 100k 1M 10M 100M

ADC BW (Hz)

0

20

40

60

80

100

120

Dyn

am

ic R

an

ge

(d

B)

1 ps rms clock jitter

FlashFlash_Time_InterleavedFoldingPipePipe_Time_InterleavedSD_CTSD_SCSD__SwOpAmpTwo-Step

Data c

4

C 1998-2005

1G 10G

Practical limitations: Input buffering Clock gen + dist’n Jitter I/O power


ADC Figure of Merit vs. Input BW - ISSCFOM = P / ( 2ENOB * 2 * FIN)

1k 10k 100k 1M 10M 100M

ADC BW (Hz)

0.1

0.3

1

3

10

30

100

300P

ower

Fig

ure

of M

erit

(pJ/

conv

/leve

l)FlashFlash_Time_InterleavedFoldingPipePipe_Time_InterleavedSD_CTSD_SCSD__SwOpAmpTwo-Step

5

Cs

limited

ited

n have both limits

Cs

to maintain the same

tions with digital

rcuits harder

s analog imperfections

nd academic ADCs


Some Trends in CMOS AD■ Increasing focus on power reduction

● Battery-powered (e.g., toys, laptops) - supply

● High-end ADCs (e.g., scopes) - dissipation lim

● System-on-a-Chip (e.g., wireless, PDAs) - ca

■ Increasing numbers of embedded ADCs and DA

■ Lower-voltage CMOS tends to take more power SNR

➪ Increased advantage in replacing analog func

■ Lower-voltage CMOS makes precision analog ci

➪ Increasing use of simpler analog circuits

➪ Increasing use of digital techniques to addres

■ Calibration Techniques

● Foreground calibration used in some ADCs

● Background calibration starting to move beyo

6

will."


Process SelectionPoulton’s Polemic:

"Don’t use III-V FETs if HBTs will work.

Don’t use III-V HBTs if silicon will work.

Don’t use bipolar if CMOS will work."

Robertson’s Reason:

"If we don’t do it in CMOS, someone else

■ CMOS is cheaper (at least in volume)

■ CMOS circuits are more widely reusable

■ CMOS designers are less difficult to hire

■ But some jobs do need other technologies

7

PU, Disk,

PC

C memory,Display

cope Software


What’s in a Scope?

■ Resolution - 8 bits

■ Realtime BW up to FS/2.5

■ Money specs: bandwidth and sample rate

AnalogInput

Amplifier Fast

RAM

CMemory P

S

AmpVoltage ADC

The ADC Designer’s View:

The Scope User’s View:

8

Way

ick-film package with

OS memory chipolar ADC chip and


Designing Scope ADCs the Old◆ Approach:

■ Use the fastest technology available

■ Design for the highest sample rate

■ If necessary, time-interleave 2-6x

◆ State of the Art in 1996:■ 25-GHz bipolar process

■ 2-GSa/s unit ADC

■ Interleaved 2x to get 4 GSa/s on one chip

■ 2.2 GHz BW (with 4x interleave)

■ 6.5 effective bits at 100 MHz

■ 5.4 effective bits at 1 GHz

■ 13 watts

■ Expensive

Custom th

custom CMcustom bip

9

ADCs?

96)

rate than bipolars

e virtually free

-hold (T/H)


Could We Use CMOS for Scope

“Don’t be stupid:”◆ CMOS ADCs are 60 times too slow (in 19

◆ CMOS transistors are 10 times less accu

“But...”◆ CMOS chips are cheap and transistors ar

◆ Could integrate with memory

◆ Might be lower power

◆ One high-BW circuit: the NMOS track-and

10

wer ADCs

lice

h, Clocks

uit area


Idea: Massive Interleaving of Low-Po

■ Start with the most power-efficient CMOS ADC s

■ Time-interleave like crazy to get sample rate

■ Fix up analog accuracy through calibration

Challenges:Track/Hold : Bandwidth, Channel mismatc

ADC: Sample Rate, Power/sample, Circ

11

(4 GSa/s)

25 MSa/s

s 4 muxes

8b +clk, 1GSa/s


CMOS ADC Chip Architecture

■ 32 time-interleaved pipeline ADCs at 1

■ Net sample rate is 4 GSa/s

32 T/H+V/I

32 ADCsDLL

InputClock

Vin

Clock

Gen

32 RC

Radix C

onverters+-

12

tion

an apparent voltage

z)


Timing Error and ADC Resolu

■ Fast signal converts a sample timing error (dT) toerror (dV).

■ Rule of thumb: 1 ps / 1 GHz --> 7 effective bits

dV

dT

Vin

Fin(MH

Effe

ctiv

e bi

ts

3

5

7

9

1000 200050025012562.5

4 ps rms

1 ps rms

16 ps rmsOtherwise Ideal ADC

13

180 200


Timing Error Signature

■ Larger voltage errors during high dV/dt.Fs = 20 GSa/s Fin = 5007.5 MHz 5.0 effective bits

-10

-5

0

5

10

Err

or (L

SB

s)

0 20 40 60 80 100 120 140 160Equivalent Time (ps)

0

50

100

150

200

250

AD

C C

ode

14

y: 2 ns

er cal

32SamplingClocks(125 MHz)


Timing Generator

● Max input edge to sampling edge dela

~ 1 ps jitter < 1 ps static error aft

DLL

/4/4

/4/4

/4/4

/4/4

500 MHz Clock

PD...

RingCntrs

DelayAdjusters

15

ld

arity:

rasitics

peak)

dB HD3 dB HD3

old


Simplified Input Track/Ho

■ To achieve highest bandwidth and line● ONLY 1 NMOS FET in signal path

● Restrict Chold to only T/H and load pa

● Low common mode input voltage

● Low-swing differential signal (250 mV

● Fastest possible full-swing clock edge

In 0.35 um: 2 GHz bandwidth, -50In 0.18 um: 7 GHz bandwidth, -50

Clock

Cds

VholdVin

Ch

16

tation

)

ves ADC

Iout +

Iout -


Analog Front End Implemen

■ Parasitic-only hold capacitance (140 fF

■ Only 1 ns (12.5%) pulse width for Clks

■ Reset phase

■ Transconductor (V/I) current output dri

W/2

Clk rst

Clkcc

Vin+

-

Clks

V/I

Vhold +

Vhold -

W W/2Sample Charge Reset

Comp.

17

am

G=1.6

Residue

1-bitquantizer

12

b inary )

dix 1.6


Pipeline ADC Block Diagr

● Only 1 comparator per stage

1-bitquantizer

T/H

De-skew latches

DACFF+_

G

…

+-

Clock

Input

Radix Conversion Circuit

Clock

Input

1-bitquantizer

21

Corrected Output (8 bits,

Raw ADC output: 12 bits, Ra

18

ain

scodes are 8 bit

Iout

*W


Current-Mode T/H and G

■ Good Linearity: Current mirrors with calinear.

■ Poor Accuracy: Gain and offset errors

Gain=M

Iin

W M

19

le

ed to represent

w1 + b0.w0

sign

d.

g design.ation

.


Radix Converter Princip

■ ADC is performing linear operations.

■ Output bits are can be linearly combininput signal:

ADC output = b 11.w11 + b10.w10 + ... + b1.

■ Traditional design: Accurate analog de● wi are powers of 2

● No explicit Multiply/Accumulate neede

■ Digital Calibration: Approximate analo● Actual wi are measured through calibr

● Compliments reduced radix approach

● Requires Multiply/Accumulate block.

20

nverter)

Binary Output

ing cal.

w1 + b0.w0

(8 bits)


Multiply/Accumulate (Radix Co

■ 1 bit “Multiply” is just a memory access

■ Look-up table is an alternative.

weight 11Bit 11

Bit 10

Bit 9

Bit 1

Bit 0

weight 10

weight 9

weight 1

weight 0

…

…

Calculate and download bit weights dur

Output = b 11.w11 + b10.w10 + ... + b1.

Σ…

21

ted?

sources

s muxes

ExternalLookup

Table


What Needs To Be Calibra

● Offline Calibration with DC and Pulse

Radix C

onverters

32 T/H+V/I

32 ADCsDLL

Clock

Clock

Gen

32 RC

RC Bit Weights

Per-sliceGain + OffsetDACs

TimingAdjust

22

proach

alog design.DC slice.

order mismatch

.

easily cal’ed.

asonable bound on calibration DAC is

chip.


Advantages of a Calibration Ap

■ We can get away with approximate an● No 6-sigma 1% matching needed in A

● Do not need precise modelling of 2ndeffects (like layout related delta W).

● Time delay mismatch can be tolerated

● Signal path offset and gain errors are

● If an effect can be calibrated, and a reits effect computed, then design of therelatively simple.

■ Benefits:● Reduced design time.

● High yield possible with many ADCs /

23

out

W 0.35 µm

16 R

Cs


4 GSa/sec ADC Chip Lay

7.1 mm x 4.0 mm 300,000 FETs 4.6

16 P

ipel

ines

16 T/H

16 RC

s

16 Pipelines

16 T/H

24

tion

2 2.5


Acquisition Before Calibra

~ 5 effective bits

0 0.5 1 1.5Time (µs)

-100-80-60-40-20

020406080

100

AD

C C

ode

(LS

Bs)

25

on

ffective bits

5 30 35


Acquisition After Calibrati

Fs=4000 MSa/sec F in=30.27 MHz 7.0 e

0 5 10 15 20 2Equivalent Time (ns)

-150

-100

-50

0

50

100

150A

DC

Cod

e

26

quency

2G 4G

ll scale

6.2 @1 GHz


ADC Effective Bits vs Input Fre

1.2 ps rms clock error

40M 100M 200M 400M 1GFrequency (Hz)

0

1

2

3

4

5

6

7A

ccur

acy

(Effe

ctiv

e B

its)

5.9 GSample/sec

4.0 GSample/sec

Input amplitude ~95% of fu

27

6 GHz

er BW

ip

emory

2 muxes

CMOS ADC Chip

8 Mem

ory Controllers

1 MB

yte SR

AM


0.18 µm CMOS: 20 GSa/s,

■ 2x faster process, 5x higher sample rate, 6x high

■ 80 ADC slices, larger Cin --> SiGe input buffer ch

■ 160 Gb/s data rate --> 1 MB on-board sample m

1 GHzClock

Clock

Gen

80 Pipeline A

DC

s

80 Radix C

onverters

80-Slice D

ecimator SiGe

Vin

80 T/H

s

Buffer Chip

BiBiCMOS

28

roop

Buffer:40 GHz SiGe

1 x 2 mm1000 transistors

1 W

ADC:0.18-um CMOS

14 x 14 mm50M transistors

9 W

Package:438-ball BGA35 x 35 mm


20 GSa/sec ADC Module

➪ System Challenges: Low Voltage + Supply D Digital Complexity

Memory

PipelinesRadix Converters

Memory Controllers

29

quency

jitter

0G


ADC Effective Bits vs Input Fre

6.5 effbits at low frequency. 0.7 ps rms

10M 20M 50M 100M 200M 500M 1G 2G 5G 1

Input Frequency (Hz)

0

1

2

3

4

5

6

7

8E

ffec

tive

Bit

s

Noise-limited Jitter-limited

Input amplitude 95% of full scale.

30

sa/s Units

GSa/sbitsGHz

effective bits(ENOB)ps rms

LSB rms0.3 LSB

Watts5GHz CMOS / SiGe 1x2 mm2

1km BGA

samples


ADC Chips - Key Spec4 GSa/s 20 GS

Nominal Sample Rate 4 20Resolution 8 8

3 dB Bandwidth 1.6 6.6Accuracy @ 30 MHz

Fs/47.06.2

6.55.0

Timing Error (jitter) 1.2 0.7Noise 0.6 0.9

INL / DNL ±0.3 / ±0.2 ±0.4 / ±Power 4.6 10

IC Technology 0.35 µm 0.18µm / 3

Chip Size 7.14 x 4.04 14x14 /Transistors 300k 50M / Package 27 mm 35 mMemory 0 1 M

31

4

40G

8 bit

8 bit

20 GSa/s2003


Monolithic ADCs in 200

1G 2G 4G 10G 20G

Sample Rate

3

4

5

6

7

8E

NO

B a

t Fs/

4CMOS

Bipolar



4 GSa/s 2002

VLSI1997

ISSCC1991

CommercialDatasheet

CommercialDatasheet

ISSCC2004

ISSCC2004

32

rest competitor

20G 40G

20 GSa/s2003


Energy per Sample

■ Twice the sample rate at 1/3 the power of the nea

1G 2G 4G 10G

Sample Rate (Fs) (Hz)

0.1

0.2

0.4

0.60.8

1

2

4

68

10

Ene

rgy

per

Sam

ple

(Wat

ts/G

Sa/

s)

CMOS 8 bitBipolar 8 bit

LeCroy

4 GSa/s 2002

HP1997

HP1991

SPT

Maxim

2002

National2004

33

d low cost

arket

mpete at the highest

curate circuits


Conclusions■ Trends

● Increasing importance of power efficiency an

● CMOS is taking over ever more of the ADC m

■ Interleaved ADCs

● Massive time-interleaving allows CMOS to cosample rates

● Very high BW possible with NMOS T/H

● Calibration is a key to utilizing low-power, inac

● The world’s fastest 8-bit ADC is now CMOS

34

Mehrdad Heshami

Andy Burstein

Charles Tan

Jorge Pernillo

und at

pers.html


Acknowledgements

Robert Neff

Brian Setterberg

Bernd Wuppermann

Tom Kopley

Bob Jewett

Updated versions of these slides may be fo

http://www.labs.agilent.com/Ken_Poulton/pa

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