BUILT-IN SELF-TEST AND REPAIR FORpeople.math.sfu.ca/~rtt/ugrad_thesis.pdf · BUILT-IN SELF-TEST AND...

BUILT-IN SELF-TEST AND REPAIR FOREMBEDDED SRAMS

by

Ross Tulloch

THESIS SUBMITTED IN PARTIAL FULFILLMENT OF

THE REQUIREMENTS FOR THE DEGREE OF

BACHELOR OF APPLIED SCIENCE

in the School

of

Engineering Science

© Ross Tulloch 2002

SIMON FRASER UNIVERSITY

August 2002

All rights reserved. This work may not bereproduced in whole or in part, by photocopy

or other means, without permission of the author.

ii

Approval

Name: Ross Tulloch

Degree: Bachelor of Applied Science

Title of thesis: Built-In Self-Test and Repair for Embedded SRAMs

Dr. John JonesDirectorSchool of Engineering Science, SFU

Examining Committee:

Academic Supervisor: Dr. Rick HobsonProfessorSchool of Engineering Science, SFU

Technical Supervisor: Allan DyckASIC Engineering ManagerCogent ChipWare Inc.

Committee member: Keith CheungASIC Engingeering ManagerCogent ChipWare Inc.

Date approved:

iii

Abstract

The proliferation of large, high capacity embedded memory on system-

on-a-chip (SOC) microelectronic applications has created the need for

built-in self-test (BIST) and repair (BISR) methods. Embedded memories

are relatively inaccessibile through a chip’s pins, making internal testing

effective. Embedded memories, like stand-alone memories, suffer from

random physical defects created during fabrication. Such defects are

expensive because they decrease the manufacturing yield.

First, the theoretical background to the problem is introduced, including

how to estimate yield and how to model physical manufacturing defects

as logical faults, which can be detected using march tests. Next, the

development of behavioral memory models in VHDL is explained. Then

two BISR systems are discussed. The first system can only repair faulty

rows while the second can repair both faulty rows and columns. The

combination row and column repair algorithm requires more circuitry,

but with an overall yield near 65% the combination method showed a 5%

improvement in yield over what could be achieved by either row or

column repair alone.

iv

Acknowledgements

Thank you Rick Hobson for making yourself available and suggesting

this topic. Also thanks for not forgetting about me during such busy

times and for allowing me space to work in the VLSI lab.

I am grateful to Allan Dyck and Keith Cheung for being willing to

participate on my examining committee and review my work.

Finally, thanks to Stephen Liu for your printing help.

v

Contents

Approval ...........................................................................................ii

Abstract............................................................................................iii

Acknowledgements ...........................................................................iv

List of Figures...................................................................................vii

List of Tables ....................................................................................ix

1 Introduction .................................................................................1

2 Background..................................................................................2

2.1 Manufacturing yield and reliability ...................................2

2.2 SRAM memory fault modeling...........................................5

2.3 Fault testing strategies .....................................................10

2.4 Previously proposed designs .............................................12

3 The Memory models......................................................................14

3.1 Basic RAM model .............................................................14

3.2 RAM array model..............................................................16

3.3 "Faultable RAM" and "Faultable array" models..................18

4 Design of BIST1/BISR1 for Row Repair .........................................19

4.1 Top level architecture .......................................................19

4.2 The BIST1 test circuit.......................................................20

4.3 The BISR1 and the CAM....................................................22

5 Design of BIST2 for Row and Column Repair.................................28

5.1 Algorithm development.....................................................28

5.2 Top level architecture .......................................................29

5.3 The BIST2 test circuit.......................................................30

vi

5.4 The Row (Column) Fault Latch circuit...............................33

6 Results and Comparisons .............................................................35

6.1 Yield measurements .........................................................35

6.2 Row repair versus row and column repair.........................38

6.3 Statistics from the BISR literature ....................................39

7 Summary and Future Development ..............................................41

Appendix A Verification Scripts and Testbenches .............................43

References ........................................................................................52

vii

List of Figures

Figure 1: Impact on UltraSparc memory and chip yield with and without

repair (Youngs, 1997) ..............................................................5

Figure 2: Some potential faults on an SRAM cell ...............................6

Figure 3: (a) Diagram of a good cell and (b) of a transition fault cell ...8

Figure 4: Diagram of an idempotent coupling fault (CFid)..................9

Figure 5: 9N march test algorithm ....................................................10

Figure 6: Chen’s BISR for ultra-high capacity memories (1992) .........13

Figure 7: Tanabe’s BISR using CAM (1992) .......................................13

Figure 8: Black box diagram of memory model ..................................14

Figure 9: Timing diagram for memory read........................................15

Figure 10: Timing diagram for memory write.....................................16

Figure 11: Block diagram of RAM array.............................................16

Figure 12: Organization of the array column decoder ........................17

Figure 13: Top level architecture of BIST1/BISR1 .............................19

Figure 14: Block diagram of the BIST1..............................................20

Figure 15: State diagram of the BIST1’s finite state machine.............22

Figure 16: Block diagram of the BISR1 .............................................23

Figure 17: Typical CMOS CAM memory cell ......................................24

Figure 18: Typical CAM array circuit.................................................25

Figure 19: Gate level CAM block diagram..........................................26

Figure 20: Functional block diagram of Faulty Address Core.............27

Figure 21: Example values in encoded and decoded cores .................27

viii

Figure 22: The size of the allocation problem for SR=3 and SC=2........28

Figure 23: Top level architecture of the BIST2 system .......................30

Figure 24: Block diagram of BIST2....................................................31

Figure 25: State diagram of the control FSM .....................................32

Figure 26: Diagram of the Row Fault Latch circuit ............................33

Figure 27: Yield versus number of spares..........................................36

Figure 28: CRESTA algorithm yield versus number of spares (Kawagoe,

2000) ......................................................................................37

Figure 29: Best allocation for number of spares ................................37

ix

List of Tables

Table 1: Description of faults in Figure 2...........................................7

Table 2: Reduced functional faults ....................................................7

Table 3: Functional memory faults and the reduced equivalents .......9

Table 4: Necessary background patterns for 8 bit words....................11

Table 5: Necessary background patterns for 32 bit words..................11

Table 6: Types of faults in the “faultable RAM” model........................18

Table 7: Advantages and disadvantages of row repair........................38

Table 8: Advantages and disadvantages of row and column repair.....39

Table 9: Area overhead using BISR for various memory dimensions

(Benso, 2000) ..........................................................................39

Table 10: Total manufacturing cost for commercial micropressors with

and without BISR (Chakraborty, 2001) ....................................40

Chapter 1: Introduction 1

Chapter 1

Introduction

The demand for larger embedded memories and the exponential scaling

of Complementary Metal Oxide Semiconductor (CMOS) logic processes

has created a Design For Testability (DFT) problem in the last ten years.

Higher capacity embedded memories are prone to process and logic

defects. Such defects are difficult to detect using traditional memory test

systems because embedded memories are relatively inaccessible via the

chip’s pins, making built-in self-test (BIST) preferable. However, “to

improve the yield and reliability of very large scale integration (VLSI)

chips, BIST alone is not sufficient; built-in self-repair (BISR) is of growing

importance” (Chakraborty, 2001). A BISR unit can repair defects by

exchanging them with redundant circuitry, which “can significantly

enhance the yield of the manufacturing process, improve reliability of the

outgoing product, and increase the quality of the overall system” (Zorian,

2000).

This thesis discusses the development and evaluation of two BIST/BISR

systems using VHDL. The first system, called BIST1/BISR1, performs

row repair on defective memory arrays using a content addressable

memory (CAM). The second system, called BIST2, uses an allocation

algorithm to perform row and column repair with a configurable number

of spare rows and columns. Background to the BIST/BISR problem is

also discussed, including fault models, testing strategies, manufacturing

yield and reliability, as well as a review of current literature.

Chapter 2: Background 2

Chapter 2

Background

The ultimate goal of BISR is to save the memory producer and consumer

money by increasing the manufacturing yield and lifetime reliability while

minimizing the effect on the memory’s size and performance. As a result,

opting to use BISR on one’s memories creates various tradeoffs. In this

section, yield is first examined, then memory fault models and fault tests

are introduced. Fault test coverage versus testing time is another

tradeoff because production test time can be very expensive. Finally, two

classic examples of BISR from the literature are discussed to give context

to the BISR problem.

2.1 Manufacturing yield and reliabilityYield is defined as the ratio of usable chips after production to the total

number of chips at the start of production. Yield depends on various

process variations, such as dust or impurities on the silicon wafer, and

causes defects to occur randomly across the wafer, leaving some of the

eventual chips defective. The distribution of defects is often quantified

using the Poisson distribution as follows (Ferris-Prabhu,1992). If the

defect density D (per unit area) is constant throughout each chip on the

wafer, then the probability of finding n defects, and the yield Y, are given

by

p ne

nY p e AD

n

( , )!

( , ) ,λλ

λ λλ

λ= ⇒ = = =−

−0 (1)

where λ is the average number of defects per chip, and A is the area.

However, in reality the defect density D is not constant over the wafer


and has its own probability density function f(D). A more accurate

probability of finding n defects is

p n ADf D AD e

ndD

n AD

( , )( )( )

!=

−

∫ , (2)

which is an indefinite integral over D. A common distribution for f(D) is

f DBD e x e s dsD B s x( )

( ), ( )/= =− − − −

∞

∫1 1 1

0ΓΓ

α αα , (3)

which uses the gamma function (a functional representation of

factorials), and where α and B are

α α= = = =D

DB

D

DD avg D B0

2

00var( )

,var( )

, ( ) (4)

and D0 is the expected value of D. The variable α is known as the

clustering parameter, which is typically around 0.5. In the limit α →∞,

clustering effects disappear because D is evenly distributed.

Substituting equation (3) into (2) and performing the nontrivial

integration results in a relatively simple expression for the probability of

n defects

p n ADn

n

AD

AD

n

n( , )( )

! ( )

( / )

( / )=

++ +

ΓΓα

ααα α

0

01(5)

and the yield

Y p ADAD

= =+

( , )( / )

01

1 0 α α . (6)

The difficulty in forecasting yield is that there is no way of determining

f(D) directly until after yield statistics have been compiled from a

production run. The yield also varies throughout a product’s lifecycle,

making it difficult to determine the true value of BISR in a memory.

Once the yield is known though, Koren’s (1998) figure of merit for

redundancy called “effective yield improvement,” defined as


YIY

Y

A

Aredundancy

without

without

redundancy

= (7)

trades silicon area for yield on a 1-to-1 basis, and is a good indicator of

whether a BISR is going to be effective.

In an overview of design and test of embedded memories, Rajsuman

(2001) identified various studies that have shown 5-20% yield

enhancements on embedded memories by BISR methods. Because

embedded memory accounts for a significant amount of silicon area on a

chip, the overall chip yield increases by about 2-10%. These figures will

increase as future system-on-a-chip (SOC) applications use more on-chip

memories. Bhavsar (1999) claims that already approximately 2/3rd of

the transistors in the Alpha 21264, or 1/3rd of the silicon area, and

approximately 90% of the area on the StrongArm SA110 is occupied by

embedded memories. Figure 1, below, shows an example of yield

improvement of about 10% using BISR on the UltraSparc by Youngs

(1997).


Figure 1: Impact on UltraSparc memory and chip yield with and

without repair (Youngs, 1997)

Chip reliability is concerned with the likelihood that a chip will fail

sometime during its lifetime due to general decay. Reliability statistics

such as mean time to failure (MTTF) are modeled using Poisson

distributions and gamma functions to estimate the average lifetime of a

chip. Sharma (1997) gives a detailed discussion of reliability modeling.

With BISR, “soft repair” can be performed in the field at power-up to fix

defects as they arise, which can lengthen product lifetimes.

2.2 SRAM memory fault modelingAny static random access memory (SRAM) consists of a two dimensional

array storage cells 2r rows tall by 2c columns, row and column address

decoders, drivers for writing the cells, sense amplifiers for reading cells,

and interconnect wires (or lines) linking the cells to the decoders, drivers

and sense amps. The cell array occupies the largest amount of silicon


area in an SRAM; therefore, random defects are most likely to occur in

the cells or on the interconnect wires. Because of its simple, repeated

structure the array is fortunately the most easily repaired, as faults in

the array can be replaced by redundancies. Figure 2 shows an SRAM

cell with some common shorts and open circuits that lead to defects

(Bushnell, 2000).

Figure 2: Some potential faults on an SRAM cel

This cell is a traditional CMOS SRAM cell with active pull-up

When the “wrd” line is asserted, “cell” will attempt to pull dow

“bit” or “-bit” depending on whether “-cell” or “cell” are asserte

respectively. On a read, the both “bit” and “-bit” would be pre

before “wrd” is asserted. On a write, “bit” and “-bit” are driven

and VSS to overwrite the value in “cell”. The dashed arrows in

represent short circuits and the double lines are open circuits

to G are described in Table 1 below.

l

transistors.

n either

d

-charged

to VDD

Figure 2

. Faults A


Table 1: Description of faults in Figure 2

FaultLabel Description of fault Fault Type

A -bit line open circuit, cannot read 1 fromcells above fault

Stuck-at-0

B -cell and -bit short, neighbors pulled to 1 ifcell is 1

Coupling fault

C cell shorted to VSS Stuck-at-0D open circuit at -cell gate Stuck-at-0E -cell shorted to VDD Stuck-at-0F Cell and bit line short, neighbors pulled to 0

if cell is 0Coupling fault

G Word line open circuit, cells on word line toright of this cell cannot be accessed

Access fault

Fault A causes a stuck-at-0 fault for cells located higher up on the “-bit”

line because those cells will be unable to pull the “-bit” line low upon

being read, so they will always appear to be logic 0.

Although many types of faults can occur in a memory, they can be

mapped into five “reduced functional faults” shown in Table 2 (Bushnell,

2000).

Table 2: Reduced functional faults

Abbreviation FaultSAF Stuck at fault (1 or 0)CF Coupling faultAF Address decoder faultTF Transition faultNPSF Neighborhood pattern sensitive fault

A stuck-at fault (SAF) occurs when the logic value of a cell is always 0 or

1. To detect SAF’s, both logic states must be read from each cell. A cell

with a transition fault (TF) cannot either make a transition from 1 to 0,


or 0 to 1. To detect TF’s each cell must be made to transition both from

1 to 0 and 0 to 1, with a read after each transition. Figure 3 shows the

state transitions of a good cell in (a), and of a cell that is unable to

transition from 0 to 1 in (b).

Figure 3: (a) Diagram of a good cell and (b) of a transition fault cell

Address decoder faults (AF) are decoding errors where one of the four

following situations occur: no cell is accessed for some address, no

address can access a certain cell, multiple cells are accessed by one

address, or a single cell is accessed by multiple addresses. Coupling

faults (CF) come in various forms, but all are caused by a dependence of

one cell on a neighboring cell. An inversion coupling fault happens when

a transition in cell X, either 1 to 0 or 0 to 1, causes cell Y to change state.

State coupling faults occur when one of the states of cell X causes the

state of cell Y to be a certain value. An idempotent coupling fault (CFid)

is when a transition in cell X sets cell Y to 0 or 1. Figure 4 shows the

state diagram of a CFid where writing a transition from 0 to 1 in cell X

causes cell Y to become 1. The circle on the left shows which values

correspond to x and y.


Figure 4: Diagram of an idempotent coupling fault (CFid)

Finally, neighborhood pattern sensitive coupling faults (NPSF’s) are

multiple coupling faults where a cell is in some way dependent its

neighbors both vertically and horizontally. A list of functional faults are

shown with their corresponding reduced functional faults in Table 3

(Bushnell, 2000).

Table 3: Functional memory faults and the reduced equivalents

Functional fault Reduced FaultCell stuck SAFDriver stuck SAFRead/write line stuck SAFChip-select line stuck SAFData line stuck SAFOpen circuit in data line SAFShort circuit between data lines CFCrosstalk between data lines CFAddress line stuck AFOpen circuit in address line AFShorts between address lines AFOpen circuit in decoder AFWrong address access AFMultiple simultaneous address access AFCell can be set to 0 but not 1 (vice versa) TFNeighborhood pattern sensitive coupling NPSF


2.3 Fault testing strategiesMarch tests are universally employed, when using BIST, to test the fault

models described in section 2.2. To illustrate a typical march test, the

9N march test, as used by Chen (1992) is shown below in Figure 5. In

the first march 0’s are written from lowest address to highest address.

Then in march 2, reads are performed from lowest to highest address,

with 0’s as the expecting data. The rest of the test is similar except that

starting at march 6, addresses are counted from highest to lowest.

9N March Retention TestMarch 1 2 2 4 5 6 7 8 9 wait 10 11 wait 12

Addr0 Wr0 Rd0 Wr1 Rd1 Wr0 Rd0 Wr1 Rd1 Wr0 Rd0 Wr1 Rd1

Addr1 Wr0 Rd0 Wr1 Rd1 Wr0 ↑ ↑ ↑ ↑ ↑ ↑ ↑

… ↓ ↓ ↓ ↓ ↓ Rd0 Wr1 Rd1 Wr0 Rd0 Wr1 Rd1

AddrN Wr0 Rd0 Wr1 Rd1 Wr0 Rd0 Wr1 Rd1 Wr0 Rd0 Wr1 Rd1

Figure 5: 9N march test algorithm

The right side of Figure 5 shows an additional data retention test. This

test is only of concern when testing dynamic random access memory

(DRAM) because DRAM’s are susceptible to charge leakage while SRAM’s

are not. The primary feature of the march test is that it inverts both the

order that cells are read and written to and the values that are read, all

within order N operations. In fact, a 10N march test, that is one that

includes the 10th march in Fgure 5 will detect all SAF’s, AF’s, TF’s, and

CF’s (Bushnell, 2000).

For multi-bit word memories, those with dimensions 2r rows by 2c

columns by b-bits, the march test must be performed log(b)+1 times in

order to detect coupling faults within a word. Half of the “background


patterns” necessary to test multi-bit words with a march test are shown

for 8-bit and 32-bits words in tables 4 and 5 respectively. The other half

of the necessary patterns are the inverse of those listed.

Table 4: Necessary background patterns for 8 bit words

Word Pattern 1 00000000Word Pattern 2 01010101Word Pattern 3 00110011Word Pattern 4 00001111

Table 5: Necessary background patterns for 32 bit words

Word Pattern 1 00000000000000000000000000000000Word Pattern 2 01010101010101010101010101010101Word Pattern 3 00110011001100110011001100110011Word Pattern 4 00001111000011110000111100001111Word Pattern 5 00000000111111110000000011111111Word Pattern 6 00000000000000001111111111111111

Chakraborty (2001) has proposed using a Johnson counter to cover the

necessary background patterns. A Johnson counter is a shift register, b-

bits wide, with the output of the least significant bit inverted and fed into

the most significant bit. The tradeoff is that the Johnson counter cycles

through 2*b states, which increases the test time. For example, for

b=32-bits a Johnson counter has 64 states, while only 12 are necessary.

But for b=8bits, a Johnson counter has 16 states and 8 are required.

The NPSF neighborhood fault is still unaccounted for. However I chose

to ignore NPSF testing because of the relatively high test complexity and

relatively low gains. As Lala (1997) claims, “pattern-sensitive faults are

more likely to occur in high density memory” implying that such faults


are more of a concern in dynamic random access memories (DRAM’s)

than SRAM’s.

2.4 Previously proposed designsTwo seminal papers in the development of BIST and BISR techniques for

memories are by Chen (1992) and Tanabe et al. (1992). Chen’s paper is

significant because he foresaw the advantage of allowing “memory chips

to perform tests, locate faults, and repair themselves without any

external assistance from either test engineers or test equipment.” These

memories will “improve the functional yield and reduce the production

cost.” Chen provides a blueprint for row repair BISR, shown in Figure 6,

using a “fault signature block” to correct addresses before they are sent

to the memory array so faulty addresses are avoided entirely.


Figure 6: Chen’s BISR for ultra-high capacity memories (1992)

Tanabe et al. implemented a row repair BISR, using CAM, on a stand-

alone commercial memory produced by NEC corporation. They used

BIST to perform functional tests in parallel, which reduced production

test time. Also, as can be seen in Figure 7, the BIST was a simple

processor with read only memory (ROM) that could be programmed with

various functional tests. In my designs, the flexibility of such a BIST

processor was desirable but out of the scope of this thesis; consequently,

I created my BIST as a finite state machine (FSM).

Figure 7: Tanabe’s BISR using CAM (1992)

Virage Logic Corporation is the only current high profile designer of

memory compilers that include BISR (Virage, 2000). They hold various

patents on row and column repair BISR. See Bair et al. (1996),

Kablanian et al. (1998) and Bair et al. (2000) for details.

Chapter 3: The memory models 14

Chapter 3

The Memory models

Memories are in general not built using automated ASIC tools, but use

specific compilers. However, behavioral models for memories are built in

VHDL to simulate the functionality of surrounding circuits created in

VHDL. My first design task was to create memory models and specify

their interfaces and bus timing protocols. This section describes the

basic memory models as well as my method for inserting defects into the

memories in order to test the BIST and BISR circuits.

3.1 Basic RAM modelThe basic memory model and timing diagrams originate from a

conversation with Professor Hobson in January 2002. Figure 8 shows

the block diagram of a basic RAM b-bits wide words.

Figure 8: Black box diagram of memory model

In this model, a “row” is defined as the cells that share the same “word”

line, and a “column” are bits that share the same “bit” lines. The clock


signal “clk” is shown in Figure 8, but left out of subsequent diagrams

since it is implied wherever there is a triangle symbol. The “basic RAM”

is a single row of 2r words, each b-bits wide, which is realized in VHDL

by an array of STD_LOGIC_VECTOR. The block enable signal, “BlkEn”,

is the control at both the tristate output and on the inputs. Figure 9

below shows the timing diagram for a memory read.

Figure 9: Timing diagram for memory read

The BlkEn signal is not shown, but it must meet the same timing

requirements as the “Rd” strobe in order for the data to be driven on the

following rising edge of the clock. The timing parameters ts and th are

indicate setup and hold times, which are hypothetical because my

memory models do not have timing delays. Figure 10 shows the write

cycle, where the BlkEn signal must meet the same “Wr” strobe. Data is

stored in the memory by the end of the clock cycle.


Figure 10: Timing diagram for memory write

3.2 RAM array modelTo accommodate for multiple columns, as required for BIST2, the “RAM

array” model was created by instantiating multiple basic RAM’s and

wiring them to a column decoder as shown in Figure 11.

Figure 11: Block diagram of RAM array


The full address for the RAM array is r+c bits wide to make 2c columns

and 2r rows. The column decoder creates 2c “core enable” signals from

the highest c address bits and BlkEn. The core enable signals act as

block enables for each basic RAM core. The decoder is configurable for

any value of c between 1 and 10 inclusive, and can be increased to any

integer by increasing a constant in the source code.

The core enable signal is actually a matrix of c+1 rows by 2c columns,

and only a fraction of the matrix entries are used to perform column

decoding, as shown in the example in Figure 12.

Figure 12: Organization of the array column decoder

The example above shows an array with 8 columns (c=3). The output of

each box in the array is the value at that entry, which is the logical AND

of the two inputs. Even though this decoder is only being used in a

behavioral model, it should be synthesizable because all the unused

entries in the matrix would be optimized out during synthesis.


3.3 “Faultable RAM” and “Faultable array” modelsI created the “faultable RAM” and “faultable array” models to allow

defects from the fault models described in section 2.2 to be inserted into

the memories during simulation. The block diagram of the faultable ram

is the same Figure 8, but with the addition of another input called “fault

core” which is an array of 2r strings, each b-bits wide. Each bit in the

memory has an associated character that defines whether it is a good cell

or a faulty cell. In my implementation, the faults are injected into the

cells only when writing since it assumed that any memory read will

follow a write. The four faults currently implemented in the faultable

RAM model are shown below in Table 6.

Table 6: Types of faults in the “faultable RAM” model

Fault core value Fault type Action during write0 No fault cell <= data in1 SA-1 cell <= ‘1’2 SA-0 cell <= ‘0’3 Access fault null (do nothing to cell)4 Coupling fault cell(i) <= NOT(cell(i-1))

The faultable array model is identical to the RAM array model except that

it instantiates faultable RAM’s instead of basic RAM’s.

The fault core signal is initialized in the test bench at the start of

simulation by a procedure called “fill faults” which imports fault data

from data files. The “fill faults” procedure is described in section A.3 of

the Appendix.

Chapter 4: Design of BIST1/BISR1 for Row Repair 19

Chapter 4

Design of BIST1/BISR1 for Row Repair

The purpose of creating the BIST1/BISR1 system was to implement a

march test in a basic BIST and to perform row repair on the memory

models of section 3. The BIST1 and BISR1 are in some sense building

blocks towards the more complicated BIST2 of section 5, but are by no

means less effective at repairing memories. Section 4 describes the

design of the BIST1 and BISR1, with some detail given to the BISR1’s

CAM. Effectiveness evaluation of the BIST1/BISR1 is left until section 6.

4.1 Top level architectureAt the top level, the BIST1 and BISR1 circuits together behave as a

wrapper to the memory. Figure 13 below illustrates the direction of

information flow in the system.

Figure 13: Top level architecture of BIST1/BISR1


System data, address, read strobe, write strobe, and block enable are

input from a memory bus, as described in section 3.1, to a multiplexer

(MUX). The BIST1 also inputs its own version of these signals to the

MUX, with BIST’s block enable as the MUX control signal. Not shown in

Figure 13 are a “test start” signal input to BIST1 from the system, a “test

done” signal, and “test fail” signal, both output from BIST1 to the system.

During a test, BIST1 is control; during writes it sends addresses and

data to the memory and during reads it sends addresses to the memory

and expected data to BISR1. A memory failure is determined by BISR1

when its CAM overflows because too many repairs have been attempted.

4.2 The BIST1 test circuitDescending the hierarchy one level, Figure 14, shows the circuitry of the

BIST1 circuit.

Figure 14: Block diagram of the BIST1


The BIST1 consists of a substantial FSM to perform the march, an

up/down counter to create addresses, a data counter, and minimal

control circuitry to control the block enable signal. The ubiquitous

“Pause” input signal comes from the BISR1. “Pause” is automatically

enabled during reads and held active if errors are found at an address.

In the BIST1/BISR1 design, test data goes directly from the memory

array to BISR1 (as in Figure 13) without first passing through the output

MUX. As a result, in the current version of VHDL for the BIST1/BISR1

to perform proper repair, the spare rows used by the BISR1 must be

defect free. This is not the case for the BIST2 system of section 5. Also

note as a general rule of thumb for my diagrams that output signals

which do not have arrows, like “state” in Figure 14, are internal to the

circuit. Signals with arrows from the extreme left are inputs and ones

going to the extreme right are outputs.

The FSM for the 9N march algorithm is given in Figure 15. In this figure

“BGD” stands for the index of the background pattern. For example, for

a memory with 8-bit words, the 9N march will be executed four times.


Figure 15: State diagram of the BIST1’s finite state machine

As mentioned in section 2.3 the retention test is optional. If the “Pause”

signal (from Figure 14) is active then the FSM does not update its state,

and if “Test Fail” becomes active then the state will go to “Done”.

4.3 The BISR1 and the CAMFigure 16 shows a detailed circuit diagram for BISR1.


Figure 16: Block diagram of the BISR1

The write enable signal is enabled for 2 cycles because the CAM requires

2 cycles for writes. The “errff_hit” signal is enabled when a previously

found error is encountered again. The “Pause” signal is set on a read

and reset if the data is correct or after an error has been written to the

CAM or determined to have already been stored. The “sr” match signals

coming out of the CAM enable each of the spare rows.


CAM’s are typically designed using full custom VLSI techniques. A

typical CAM cell is shown in Figure 17 (Weste, 1993).

Figure 17: Typical CMOS CAM memory cell

Transistors Q1 and Q2 form an XOR gate between data on the bit lines

and the cell values. Transistor Q3 makes a wired NOR from the output

of the Q1/Q2 XOR gate. Then cells are strung together in rows to create

the array in Figure 18.


Figure 18: Typical CAM array circuit

Each match line has a then fed to a vertical wired NOR which is finally

negated to produce the “Hit” signal which indicates if the addressed cell

matches the data at the input.

Because the purpose of this project was to investigate BISR techniques

and not memory design, I built my CAM using logic gates. Field

programmable gate arrays (FPGA’s) are often used as CAM, so I obtained

some help from a Xilinx application note (Brelet, 2000) to build a fairly

inefficient CAM using gates. The CAM circuit is shown in Figure 19. In


this diagram the “WE” signal is the same as “Write_En” from Figure 16,

and “WE_del” is “WE” delayed by 1 cycle.

Figure 19: Gate level CAM block diagram

The “initial fault” signal resets to 1, and is 0 after the first WE pulse. The

“Erase/write” signal is logic 1 for the first WE cycle and logic 0 for the

second WE cycle. Figure 20 illustrates how the “Erase/write” signal

controls address input to the “decoded core”. For each redundancy

faulty addresses are stored in an “encoded” register and a decoded core.


Figure 20: Functional block diagram of Faulty Address Core

As an example, Figure 21 shows CAM with 4 spare rows performing

repair on a memory with 16 rows, and so far 3 faulty addresses have

been found.

Figure 21: Example values in encoded and decoded cores

In normal address matching mode, the CAM indicates a match simply by

reading the contents of the decoded core. When a new faulty address is

being written to the CAM, the previous value must first be erased which

is why a write requires 2 cycles. This CAM is synthesizable if the storage

elements in the decoded core are synthesizable. For my simulations, I

used registers for the encoded core and a behavioral array for the

decoded core.

Chapter 5: Design of BIST2 for Row and Column Repair 28

Chapter 5

Design of BIST2 for Row and Column Repair

The BIST2 design extends the 9N march algorithm from the

BIST1/BISR1 system to perform row and column repair. The repair

algorithm is slower but potentially more powerful. Section 5.1 describes

the method for proper allocation of spare rows and column, and the rest

of section 5 describes the circuit.

5.1 Algorithm developmentBhavsar (1999) determined “the size” of the worst case problem that the

row and column allocation algorithm must handle. With SR spare rows

and SC spare columns, the size of the problem is 2*SR*SC because there

can be that many errors without invoking a “forced repair”. A forced row

repair occurs if there are SC+1 or more errors in a single row, and a

forced column repair occurs if there are SR+1 or more errors in a column.

From an allocation standpoint forced repairs are good because they

simplify the problem. Figure 22 illustrates how there can be 2*SR*SC

without any forced repairs.

Figure 22: The size of the allocation problem for SR=3 and SC=2


At most 2*SR*SC address entries must be kept in a failure bitmap.

However, allocation logic must still determine the proper placement of

spare rows and columns, which can be complicated if SR and SC are

greater than 1.

Perhaps a better way to arrive at correct allocation is to run the march

test multiple times so that all repairs are forced. This idea was used by

Bair (2000). By decreasing a threshold value for forced repair after each

march test, good allocation can be made without excessive circuitry.

However, test time does increase because as many as (SR-1)+(SC-1)

march tests may be required. If no errors are found then only one march

test is necessary. Even still, perfect allocation is not guaranteed because

“it has been shown that the problem of optimally utilizing the columns

and rows to cover defective cells is [non-deterministic polynomial] NP-

hard” (Kim, 1998). This implies that perfect allocation is not certain, but

must be efficiently approximated.

5.2 Top level architectureThe top level of the BIST2 system is shown in Figure 23. In this system

test data out of the memory is corrected before being compared with the

expected data at the BIST2 block. The “row fault latch” block stores

faulty row address values and enables spare rows.


Figure 23: Top level architecture of the BIST2 system

If a spare row is found to contain defects then the “row fault latch” block

can also disable that row. The “col fault latch” block is identical to “row

fault latch” but can have different dimensions. Both “row hit” and “col

hit” control the output MUX, but priority is given to row hit. If an

address is accessed that happens to have been replaced by both a spare

row and column then its value is read from the spare row.

5.3 The BIST2 test circuitFigure 24 shows complete BIST2 circuit. Any signals with “R/C” or

“row/col” mean that the circuitry is duplicated, and the order of the “R”

and “C” is deliberate. The “X” shaped block that outputs “BIST addr”

inverts the address counter bits depending on whether a “row test” or a

“col test” is being run. A row test follows a raster scan pattern to detect

forced row repairs, while the column test traverses each column to detect

forced column repairs.


Figure 24: Block diagram of BIST2


The BIST2 sends “Activate Sp Row” to the “row fault latch” block when a

forced row repair is found, and receives back “rows full” when all the

spare rows have been allocated. Three important blocks are the “control

FSM” and the counters “threshold R/C” and “R/C error” because they

control the allocation algorithm. The “march 9N FSM” is the same as for

BIST1 except that “Done” is replaced with “Wait state” and is directed by

the control FSM shown in Figure 25.

Figure 25: State diagram of the control FSM

In Figure 25, “mstate=Wait” occurs after a march test is completed. If

“test fail” is encountered then the control FSM is halted.

The key to the allocation algorithm is deciding when to perform row

testing versus column testing and when to decrement the threshold

counters. I decided to decrement the row threshold, from a maximum of

SC+1 to a minimum of 1, whenever a forced column repair occurs or

when a row test has completed and there were no column repairs in the

last column test. As seen in Figure 25, the row test is performed until

the row threshold is less than or equal to the column threshold. The


final test is a column test, when its threshold is 1. This way if any errors

are found they are immediately repaired, and a “test fail” is declared if an

error occurs while both “rows full” and “columns full” signals are active.

The “test done” signal, which indicates a “pass”, is activated whenever a

march test has completed without finding any errors.

5.4 The Row (Column) Fault Latch circuitThe row fault latch circuit is shown in Figure 26. Up to “sr” faulty row

addresses can be stored.

Figure 26: Diagram of the Row Fault Latch circuit


One address register is enabled at a time by the shift register on the left.

The “active” register keeps track of which addresses have been enabled

when stored and can also disable an address if an error reoccurs on a

previously stored address.

Chapter 6: Results and Comparisons 35

Chapter 6

Results and Comparisons

Once designed, the two BISR systems were simulated with NCSIM to

verify functionality and evaluate the performance of the allocation

algorithm. This section analyzes the simulation data as well as data

from the BISR literature to determine whether BISR is effective and what

type of BISR is best.

6.1 Yield measurementsOnce the BIST2 circuit was built and behaving as a sane circuit, I

wanted to quantify its ability to fix repair defects in memories. I created

the automated C-Shell script, described in detail in appendix A, that

generates yield approximations for a set number of spare rows and

columns. I then executed the script on a memory with 16 rows by 8

columns (and 8-bit words) for the 9 permutations of spares from

(sr,sc)=(1,1) to (3,3). The data used was a random set for 68 memories of

which only 3 were free of errors. Most of the random errors were SA-1 or

SA-0 single cell faults. I set the probability of a SA-word fault at 1/4th

the chance of a single cell, and the chance of a whole row or column

being defective were proportionally lower (actually there was only one

entire column fault in the set of 68). Note that the faults in the

simulation were distributed uniformly, so the clustering parameter of

section 2.1, α, was nearly infinity. Finally I manually counted the

number of memories that could have been repaired by row only and


column only repair for (1,0) to (4,0) and (0,1) to (0,4) respectively, and

plotted Figure 27 using MatLab.

Figure 27: Yield versus number of spares

The trend in Figure 27 is similar to results obtained by Kawagoe (2000),

which are plotted in Figure 28. In the figure, “2 or more spare improve

yield drastically” implies to 2 or more spare rows or columns improve the

yield drastically.


Figure 28: CRESTA algorithm yield versus number of spares

(Kawagoe, 2000)

A finer scale plot of Figure 27 is given in Figure 29, highlighting the best

(sr,sc) configuration compared to the total number of spares used.

Figure 29: Best allocation for number of spares


At higher yields (4,0) the discrepancy between row only repair and

combined row and column repair is minimal. This is a bit surprising

considering that a spare column is twice as large as a spare row in this

memory. At moderate yields (1,1) obtained about 5% higher yield than

both (1,0) and (0,1) proving the effectiveness of row and column repair.

6.2 Row repair versus row and column repairEvaluating which method of BISR is best is difficult because defect

distributions and yield statistics are highly dependent not only on the

product but also the phase of the product life cycle. The only way to

know for sure which BISR will work best is from experimenting during

production runs, which is expensive. There are also other tradeoffs

between the two systems such as silicon area requirements, yield, test

time, circuit speed, and design time. Unfortunately, there also has been

little research into whether row and column repair is more effective than

row repair by itself. With my knowledge, the best evaluation I can make

between the two types of repair is to list the advantages and

disadvantages of both types, see Tables 7 and 8.

Table 7: Advantages and disadvantages of row repair

Advantages DisadvantagesFaster, simpler algorithm Access time penaltyLess overhead, simpler circuit Requires an extra memory (CAM)Easily configurable “sr” spare rows Limited to just row related defectsAnalysis and repair is concurrent(repair as you go)Some good research is available(Chakraborty, 2001)


Table 8: Advantages and disadvantages of row and column repair

Advantages DisadvantagesCapable of repairing more types offaults (eg. defective columns)

Difficult to make algorithmconfigurable to “sr” spare rows and“sc” spare columnsCorrect allocation not assured (not100% coverage)Access time penaltyGood published research is scarce

6.3 Statistics from the BISR literatureTable 9 shows area overhead estimates of row repair BISR using CAM

that were calculated by Benso (2000) for various memory sizes based on

synthesis results. BIST overhead is not included, and spare rows are

considered as part of the BISR logic. They claim that the overhead of a

march based BIST (like BIST1) is negligible.

Table 9: Area overhead using BISR for various memory dimensions

(Benso, 2000)

Number of spare rowsBits per

wordNumber of

rows16 32 64

1k 31% 62.5% 127%2k 22.5% 42% 80%8-bits4k 12% 22.5% 46%1k 20% 39.5% 75%2k 12% 25% 48%16-bits4k 7% 14% 27.5%1k 11% 20% 42%2k 6% 12% 26%32-bits4k 3% 7% 13%

Another study by Chakraborty et al. (2001) gives the cost savings using

their row repair BISR with CAM. Using die photographs of commercial


microprocessors they calculated the fraction of the die that was occupied

by embedded RAM’s. Then using the following equation

Embedded RAM yield = (die yield)RAM area/die area (8)

they found the embedded RAM yield and determined how much their

BISR could improve on that yield. Finally they approximated the cost

savings of using their BISR assuming the processors did not already

contain self repair circuits, see Table 10.

Table 10: Total manufacturing cost for commercial micropressors

with and without BISR (Chakraborty, 2001)

Processor # Pins Die costw/o BISR

Die costwith BISR

Total costw/o BISR

Total costwith BISR

Intel486DX2 168 $10.00 $9.60 $17.00 $16.60Pentium (.5µ) 273 $68.00 $44.98 $118.00 $94.98PowerPC601+

304 $24.00 $18.49 $69.00 $63.49

MIPSR4400SC

447 $38.00 $33.12 $116.00 $111.12

HP PA7100 504 $74.00 $44.78 $125.00 $95.78

Chapter 7: Conclusions and Future Development 41

Chapter 7

Summary and Future Development

The BISR problem was introduced as being an issue mainly for

embedded memories, which are rapidly colonizing large portions of

silicon area on deep sub-micron VLSI chips. Section 2 discussed the

theoretical background to the problem. Manufacturing processes

generate random physical defects that are modeled as logical faults. The

purpose of BISR is primarily to increase the manufacturing yield, but

also to improve product reliability. The previous sections describe

memory models and two BISR systems that were created using VHDL.

Finally, simulation results were reported and an attempt was made to

show the value of including BISR in one’s memories. At yields near 65%

the row and column repair algorithm showed a 5% improvement in yield

over what could be achieved by either row or column repair alone.

Certainly further development can be made on this project. Quality

manufacturing process statistics on defects would make the simulations

realistic. Exhaustive simulation would also improve the yield

measurements. Perhaps most important would be the inclusion of

proper memory cores for the CAM and SRAM’s not only for simulation,

but also for synthesis to estimate the area overhead of each system. An

HSPICE simulation of the critical path would also hint at the access time

penalty for the address comparisons. Finally, since BIST and BISR are

considered a form of DFT, the inclusion of a scan chain in the BIST and

BISR blocks would be appropriate.

Chapter 7: Conclusions and Future Development 42

The design of the two BISR systems could also have been improved. The

algorithm of the second system was perhaps too complicated for small

memory cores. Probably a two-stage row and column repair algorithm

would be almost as effective and require less overhead. Such a two stage

system would allocate all spare columns as necessary, then perform a

row test to allocate spare rows. The test circuitry required would be

similar to the BIST1/BISR1 system, and the yield improvement would be

similar to the BIST2 system. Finally, some defects, such as shorts to VDD

of VSS, are also not repairable using the type of BISR systems mentioned

in this thesis. Such defects would increase the power consumption of

the chip dramatically and require the chip to be discarded. Fortunately,

such defects can be detected with IDDQ tests.

Appendix A: Verification Scripts and Testbenches 43

Appendix A

Verification Scripts and Testbenches

A.1 The “measure_yield” Script“measure_yield” is a C-Shell script which collects yield data for a memory

with a BIST2 repair circuit of one or more spare rows and one or more

spare columns. Its input parameters are: $sr, the number of spare rows,

$sc, the spare columns, $num_errs, the number of erroneous memories

to attempt to repair, and -same_data/new_data which is a flag to create

new random error data or use the current set. The values of $sr and $sc,

which must each be in the range [1:15], are instantiated into the VHDL

source code (bisr_local_.vhd) before compilation. If -new_data is selected,

$sr and $sc are also substituted into a MatLab script (gen_input.m),

described in section A.2, which generates random error data for the test

memory of a predetermined number of rows and columns (16 rows by 8

columns). The MatLab script also returns the number of attempts it

made to generate at least 1 fault (usually 1 or 2), these are accumulated

by a variable called $trials_cnt in the C-Shell script. Then the erroneous

data is inserted into the memory and simulated. A pass/fail result of

each trial is captured and accumulated by $pass_cnt for yield

calculations at the end of the $num_errs iterations.

The yield of a memory without redundancy is

Yin = ($trials_cnt - $num_errs) / $trials_cnt

while the yield with redundancy is


Yout = ($pass_cnt + ($trials_cnt-$num_errs>))/ $trials_cnt

which are both calculated in another MatLab script called gen_output.m.

The measure_yield script is listed below:#!/bin/csh -f

set startTime=`date`set count = 0set num_errs = 0set sr = 0set sc = 0set flag = 0set new_dat = 0

#STEP 0: Get num trials, sp_rows, and sp_cols from parameters.switch($1) case -same_data breaksw case -new_data set new_dat = 1 breakswendsw

if ($#argv == 4) then # NEW shift argv # NEW set flag = 1 while($#argv) set option = $1 if ($count == 0) then set num_errs = $option set count = 1 else if ($count == 1) then set sr = $option set count = 2 else set sc = $option endif shift argv end

#STEP 1: Use sc and sr in matlab to get ".dat files" cd test cat gen_input.m | sed "s/sr=.*/sr=$sr;/" > FILEOUT rm gen_input.m cat FILEOUT | sed "s/sc=.*/sc=$sc;/" > gen_input.m rm FILEOUT

#STEP 2: Update VHDL: NUM_SP_COLS, NUM_SP_ROWS in bisr_local_.vhd cd ../src cat bisr_local_.vhd | sed "s/NUM_SP_COLS : INTEGER :=.*/NUM_SP_COLS : INTEGER := $sc;/" >FILEOUT


cat FILEOUT | sed "s/NUM_SP_ROWS : INTEGER := .*/NUM_SP_ROWS :INTEGER := $sr;/" >FILEOUT2 rm FILEOUT rm bisr_local_.vhd mv FILEOUT2 bisr_local_.vhd cd ..

#STEP 3: Loop through $num_errs simulations. @ counter = 1 @ trials_cnt = 0 @ pass_cnt = 0 while ($counter <= $num_errs) if ($counter == 1) then compile -s compile -t ncelab config_bist2_basic cd test if ($new_dat == 1) then # NEW cat gen_input.m | /ensc/local2/matlab12.1/bin/matlab cp mem_faults.dat test_data/mem_faults_$counter.dat cp row_faults.dat test_data/row_faults_$counter.dat cp col_faults.dat test_data/col_faults_$counter.dat endif # NEW rm mem_faults.dat rm row_faults.dat rm col_faults.dat cp test_data/mem_faults_$counter.dat mem_faults.dat cp test_data/row_faults_$counter.dat row_faults.dat cp test_data/col_faults_$counter.dat col_faults.dat

@ trials_cnt = $trials_cnt + `fgrep -h 'n='mem_faults.dat | sed 's/n=//'` cat mem_faults.dat | sed '/n=/d' > FILEOUT cat FILEOUT > mem_faults_all.dat cat FILEOUT | sed '/^$/d' > FILEOUT2 rm mem_faults.dat rm FILEOUT mv FILEOUT2 mem_faults.dat cat row_faults.dat | sed '/n=/d' > FILEOUT cat FILEOUT > row_faults_all.dat cat FILEOUT | sed '/^$/d' > FILEOUT2 rm row_faults.dat rm FILEOUT mv FILEOUT2 row_faults.dat cat col_faults.dat | sed '/n=/d' > FILEOUT cat FILEOUT > col_faults_all.dat cat FILEOUT | sed '/^$/d' > FILEOUT2 rm col_faults.dat rm FILEOUT mv FILEOUT2 col_faults.dat else cd test if ($new_dat == 1) then # NEW cat gen_input.m | /ensc/local2/matlab12.1/bin/matlab cp mem_faults.dat test_data/mem_faults_$counter.dat cp row_faults.dat test_data/row_faults_$counter.dat cp col_faults.dat test_data/col_faults_$counter.dat


endif # NEW rm mem_faults.dat rm row_faults.dat rm col_faults.dat cp test_data/mem_faults_$counter.dat mem_faults.dat cp test_data/row_faults_$counter.dat row_faults.dat cp test_data/col_faults_$counter.dat col_faults.dat

@ trials_cnt = $trials_cnt + `fgrep -h 'n='mem_faults.dat | sed 's/n=//'` cat mem_faults.dat | sed '/n=/d' > FILEOUT cat FILEOUT >> mem_faults_all.dat cat FILEOUT | sed '/^$/d' > FILEOUT2 rm mem_faults.dat rm FILEOUT mv FILEOUT2 mem_faults.dat cat row_faults.dat | sed '/n=/d' > FILEOUT cat FILEOUT >> row_faults_all.dat cat FILEOUT | sed '/^$/d' > FILEOUT2 rm row_faults.dat rm FILEOUT mv FILEOUT2 row_faults.dat cat col_faults.dat | sed '/n=/d' > FILEOUT cat FILEOUT >> col_faults_all.dat cat FILEOUT | sed '/^$/d' > FILEOUT2 rm col_faults.dat rm FILEOUT mv FILEOUT2 col_faults.dat endif

cd ..

ncsim config_bist2_basic cd test @ pass_cnt = $pass_cnt + `fgrep -h 'Result=' results.dat |sed 's/Result=//'`

#append output to running output file if ($counter == 1) then cat results.dat > results_all.dat else cat results.dat >> results_all.dat endif

cd .. @ counter++ end

#STEP 4: Compare yield with no spare case.#get input yield:#@ in_yield = ($trials_cnt - $num_errs) / $trials_cnt#get output yield:#@ out_yield = ($pass_cnt + ($trials_cnt-$num_errs))/ $trials_cnt# But how to divide? -> use matlab. cd test cat gen_output.m | sed "s/n=.*/n=$trials_cnt;/" > FILEOUT rm gen_output.m


cat FILEOUT | sed "s/e=.*/e=$num_errs;/" > FILEOUT2 rm FILEOUT cat FILEOUT2 | sed "s/p=.*/p=$pass_cnt;/" > gen_output.m rm FILEOUT2 cat gen_output.m | sed "s/sr=.*/sr=$sr;/" > FILEOUT rm gen_output.m cat FILEOUT | sed "s/sc=.*/sc=$sc;/" > gen_output.m rm FILEOUT cat gen_output.m | /ensc/local2/matlab12.1/bin/matlab cd ..endif

if ($flag != 1) then echo "" echo " Usage: measure_yield -same_data/new_data <num_trials><#sp_r> <#sp_c>" echo " -same_data if you want 1 random set generated" echo " -new_data if you want new random data generated" echo " <num_trials> is the number memories to test insuccession." echo " Each one will have at least one fault." echo " <#sp_r> is the number of spare rows added to memory." echo " <#sp_c> is the number of spare columns added tomemory."elseecho "Test Start Time : $startTime" echo "Test End Time : `date`" cat test/yield_result.dat echo ""endif

exit(0)

A.2 MatLab ScriptsThe gen_input.m script calls a fairly simple random number generating

function (gen_input_mem.m) and gen_output.m just performs division

because C-Shell is archaic. The listing of gen_input.m is given below.% gen_input.m%

%initialize constants% N = r*c*b;% lambda = N*p;% P(n,lambda)=lambda^n*exp(-lambda)/n!;% Yield (approx)= P(0,lambda)=exp(-lambda)% want Yield around 25% -> lambda ~= 1.386% Assume p_SA0=p_SA1 <=~ p/4 so that half errors are single cellerrors.

rand('state',101*sum(109*clock)+sum(100*clock));sr=1;sc=1;r=16;c=8;b=8;


N= r*c*b;Y =0.25; %--> results in yield of ~0.4 using rand func.Y =0.15; % still too high. ~ 0.29Y =0.10; % Produces yield in 0.2-0.25 range.Y=0.04; %lambda=-log(Y);p=lambda/N;p_cell=p; p_SA0=p_cell/2; p_SA1=p_cell/2; % Y~=0.04.p_word=p/4; p_row=p/8; p_col=p/8;

fid=fopen('mem_faults.dat','w');fid_sr =fopen('row_faults.dat','w');fid_sc =fopen('col_faults.dat','w');

% call gen_input_mem functionmem_array = gen_input_mem(r,c,b,p_SA0,p_SA1,p_word,p_row,p_col);

% get random dataerr=0;n=0; %num_trials=30;%while err<num_trialswhile err<1 %gen input for each sim now. mem_array =gen_input_mem(r,c,b,p_SA0,p_SA1,p_word,p_row,p_col); n=n+1; if sum(sum(sum(mem_array)))>0 err=err+1; %sp_col_array =gen_input_col(r,sc,b,p_SA0,p_SA1,p_word,p_col); sp_col_array = gen_input_col(r,sc,b,0,0,0,0); %sp_row_array =gen_input_row(c,sr,b,p_SA0,p_SA1,p_word,p_row); sp_row_array = gen_input_row(c,sr,b,0,0,0,0);

% put data into 3 files. First mem_faults_all.dat for i = 1:r for j = 1:c x=(squeeze(mem_array(i,j,:)))'; if (x==zeros(1,b)) else y=[j-1; i-1]; z=num2str(x,'%1x'); fprintf(fid,'%X %X %s\n',y,z); end end end % Now for spare rows file. flag=0; for i = 1:c for j = 1:sr x=(squeeze(sp_row_array(i,j,:)))'; if (x==zeros(1,b)) else y=[j-1; i-1]; z=num2str(x,'%1x'); fprintf(fid_sr,'%X %X %s\n',y,z); flag=1; end end end


if (flag==0) y=[0; 0]; z=num2str(zeros(1,b),'%1x'); fprintf(fid_sr,'%X %X %s\n',y,z); end % Now for spare cols file. flag=0; for i = 1:r for j = 1:sc x=(squeeze(sp_col_array(i,j,:)))'; if (x==zeros(1,b)) else y=[j-1; i-1]; z=num2str(x,'%1x'); fprintf(fid_sc,'%X %X %s\n',y,z); flag=1; end end end if (flag==0) y=[0; 0]; z=num2str(zeros(1,b),'%1x'); fprintf(fid_sc,'%X %X %s\n',y,z); end% if (err<num_trials)% fprintf(fid,'\n');% fprintf(fid_sr,'\n');% fprintf(fid_sc,'\n');% end endend%Y =(n-err)/nfprintf(fid,'\nn=%d\n',n);fprintf(fid_sr,'\nn=%d\n',n);fprintf(fid_sc,'\nn=%d\n',n);fclose(fid);fclose(fid_sr);fclose(fid_sc);quit

Although I used error free spare rows and columns in simulation, the

redundant memory can just as easily have faults by using the linesp_row_array = gen_input_row(c,sr,b,p_SA0,p_SA1,p_word,p_row);

instead ofsp_col_array = gen_input_col(r,sc,b,0,0,0,0);

The listing for the random generator function gen_input_mem.m is

below:%% gen_input_mem.mfunction[array] =gen_input_mem(r,c,b,p_SA0,p_SA1,p_word,p_row,p_col)

% create array of SA0 faults from prob. of a SA0 at a each cell.arr_SA0 = 2*(rand(r,c,b) < p_SA0);arr_SA1 = (rand(r,c,b) < p_SA1);


if b>1 arr_word2 = (rand(r,c) < p_word); arr_word3 = arr_word2; for i = 2:b arr_word3 = cat(3,arr_word3,arr_word2); endelse arr_word3 = zeros(r,c,b);endif r>1 arr_row = (rand(r,1) < p_row); arr_row2 = arr_row; if c>1 for i = 2:c arr_row2 = cat(2,arr_row2,arr_row); end end arr_row3 = arr_row2; if b>1 for i = 2:b arr_row3 = cat(3,arr_row3,arr_row2); end endelse arr_row3 = zeros(r,c,b);endif c>1 arr_col = (rand(1,c) < p_col); arr_col2 = arr_col; if r>1 for i = 2:r arr_col2 = cat(1,arr_col2,arr_col); end end arr_col3 = arr_col2; if b>1 for i = 2:b arr_col3 = cat(3,arr_col3,arr_col2); end endelse arr_col3 = zeros(r,c,b);end% combine all stuck at 1 type faults (logical OR)arr_SA1 = arr_SA1 | arr_word3 | arr_row3 | arr_col3;% now combine two arrays, make SA0 dominate over SA1array = arr_SA0 + arr_SA1;for i = 1:r for j = 1:c for k = 1:b if array(i,j,k)==3 array(i,j,k)=2; end end endend


A.3 Testbench structureThe testbench used for the “measure_yield” script is called

bist2_basic_testbench.vhd and is located on CSSNet in the

~rtt/bisr/vhdl/BISR/test directory. Error data is imported into the

faultable memory at startup by the FILL_FAULT_MEM process below:FILL_FAULT_MEM : process(IniClk) begin if (IniClk'event and IniClk='1') then fill_faults_mem(fault_core_mem); fill_faults_rows(fault_core_rows); fill_faults_cols(fault_core_cols); end if; end process;

The “fill_faults_xxx” procedures are data parsers that take a text file of a

variable number of lines and format as shown below:0 0 000000017 F 111111110 3 020000011 5 00030000

as input and assign those values to the “fault_core” of the memory which

has one of the following VHDL types: type FAULT_TYPE is array (0 to (CORE_DEPTH-1)) ofSTRING(DATA_WIDTH downto 1); type FAULT_TYPE_MEM is array (0 to (NUM_CORES-1)) ofFAULT_TYPE; type FAULT_TYPE_COLS is array (0 to (NUM_SP_COLS-1)) ofFAULT_TYPE; type FAULT_TYPE2 is array (0 to (NUM_CORES-1)) ofSTRING(DATA_WIDTH downto 1); type FAULT_TYPE_ROWS is array (0 to (NUM_SP_ROWS-1)) ofFAULT_TYPE2;

where CORE_DEPTH is the number of rows in the memory and

NUM_CORES is the number of columns. The 3rd line of the input file,

0 3 02000001, means that the 8-bit word at column 0, row 3 has a stuck-

at-0 fault at bit 6, and a stuck-at-1 fault at bit 0.

The simulation output is written as a simple pass or fail to a text file

which can easily be parsed by the C-Shell script.

References 52

References

O. Bair et al., 1996, Method and Apparatus for Configurable Build-in Self-Repairing of ASIC memories Design, United States patent 5577050,Washington: Patent and Trademark Office

O. Bair et al., 2000, Method for repairing an ASIC Memory withRedundancy Row and Input/Output Lines, United States patent6065134, Washington: Patent and Trademark Office

A. Benso et al., 2000, “A family of Self-Repair SRAM Cores,” Proceedingsof the 6th IEEE International On-Line Testing Workshop, pp. 214-218

D. Bhavsar, 1999, “An Algorithm for Row-Column Self-Repair of RAMsand Its Implementation in the Alpha 21264,” Proceedings of theInternational Test Conference, pp. 311-318

J. Brelet, 2000, “Using Block RAM for High Performance Read/WriteCAMs,” Application Note: Virtex Series (XAPP 204), Xilinx Inc.

M. Bushnell and V. Agrawal, 2000, Essentials of Electronic Testing forDigital, Memory and Mixed-Signal VLSI Circuits, Boston: KluwerAcademic Publishers, pp. 266-278

K. Chakraborty et al., April 2001, “A Physical Design Tool for Built-InSelf-Repairable RAMs,” IEEE Transactions on VLSI Systems, Vol.9, No. 2, pp. 352-364

T. Chen and G. Sunada, 1992, “A Self-Testing and Self-RepairingStructure for Ultra-Large Capacity Memories,” Proc. of theInternational Test Conference, pp. 623-631

A. Ferris-Prabhu, 1992, Introduction to Semiconductor Device YieldModeling, Boston: Artech House, Inc., pp. 36-40

A. Kablanian et al., 1998, Built-In Self Repair System for EmbeddedMemories, United States patent 5764878, Washington: Patent andTrademark Office

T. Kawagoe et al., 2000, “A Built-In Self-Repair Analyzer (CRESTA) forembedded DRAMs,” Proc. of the International Test Conference, pp.567-573

References 53

I. Kim, Y. Zorian et al., 1998, “Built In Self Repair for Embedded HighDensity SRAM,” Proc. of the International Test Conference, pp.1112-1119

I. Koren and Z. Koren, 1998, “Defect Tolerant VLSI Circuits: Techniquesand Yield Analysis,” Proceedings of the IEEE, Vol. 86, No. 9, pp.1817-1836

P. Lala, 1997, Digital Circuit Testing and Testability, San Diego: AcademicPress Ltd., p. 174

R. Rajsuman, May-June 2001, “Design and Test of Large EmbeddedMemories: An Overview,” IEEE Design and Test of Computers, Vol.18, No. 3, pp. 16-27

A Sharma, 1997, Semiconductor Memories: Technology, Testing, andReliability, New York: IEEE Press, pp. 287-296

A. Tanabe et al, November 1992, “A 30-ns 64-Mb DRAM with Built-inSelf-Test and Self-Repair Function,” IEEE Journal of Solid StateCircuits, Vol. 27, No. 11, pp. 1525-1531

N. Weste and K. Eshraghian, 1993, Principles of CMOS VLSI Design: ASystems Perspective, Second Edition, New York: Addison-WesleyPublishing Company, pp. 589-590

Virage Logic Corporation, 2000, “The STAR Memory System” (productbrochure), available at:http://www.viragelogic.com/products/compilers/star/index.jsp

L. Youngs and S. Paramanandam, 1997, “Mapping and RepairingEmbedded Memory Defects,” IEEE Journal of Solid State Circuits,Vol. 33, No. 1, pp. 18-24

Y. Zorian, 2000, “Yield Improvement and Repair Trade-Off For LargeEmbedded Memories”, Design, Automation and Test Conference inEurope, pp. 69-71

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