Built-In Self-Test for Built-In Self-Test for Field Programmable Gate ArraysField Programmable Gate Arrays

funded by National Security Agencyfunded by National Security Agency

Chuck StroudChuck StroudElectrical & Computer Electrical & Computer

EngineeringEngineeringAuburn UniversityAuburn University

Outline of PresentationOutline of Presentation• OverviewOverview

Built-In Self-Test (BIST)Built-In Self-Test (BIST) Field Programmable Gate Arrays (FPGAs)Field Programmable Gate Arrays (FPGAs)

• BIST for FPGAsBIST for FPGAs Logic resourcesLogic resources Routing resourcesRouting resources

• Demonstration of FPGA logic BIST & Demonstration of FPGA logic BIST & DiagnosisDiagnosis

The Need for TestThe Need for Test

2000 International Technology Roadmap for 2000 International Technology Roadmap for SemiconductorsSemiconductors (by the Semiconductor Industry (by the Semiconductor Industry Association - Association - SEMATECHSEMATECH) predicts by 2014:) predicts by 2014:

• Test machines will cost > $20MTest machines will cost > $20M• It will cost more to test a transistor than to It will cost more to test a transistor than to

manufacture itmanufacture it• Built-In Self-Test (BIST) is a likely solutionBuilt-In Self-Test (BIST) is a likely solution

Analog BIST is needed for mixed-signal systemsAnalog BIST is needed for mixed-signal systems Fault diagnosis is needed with BISTFault diagnosis is needed with BIST Tools are needed for automating BISTTools are needed for automating BIST

What is BIST?What is BIST?• Basic idea:Basic idea: Add circuitry to IC or PCB to facilitate Add circuitry to IC or PCB to facilitate

testing itselftesting itself Only power and clock needed during BIST sequenceOnly power and clock needed during BIST sequence Pass/Fail result reported at end of BIST sequencePass/Fail result reported at end of BIST sequence

No need for external test equipmentNo need for external test equipment

• Necessary components:Necessary components: Test Pattern Generator (TPG)Test Pattern Generator (TPG) Output Response Analyzer (ORA)Output Response Analyzer (ORA) For system level use:For system level use:

Test controllerTest controller Input isolationInput isolation

• Penalties:Penalties: area overhead, performance area overhead, performance• Benefits:Benefits: low testing time & cost low testing time & cost

TPGTPG

ORAORA

CircuitCircuitUnderUnderTestTest

TestTestControlControl

MUXMUX

SystemSystemInputsInputs

SystemSystemOutputsOutputsPass/FailPass/Fail

BIST BIST StartStart

Overview of FPGAsOverview of FPGAs

• Configuration Configuration MemoryMemory

• Programmable Programmable Logic Blocks Logic Blocks (PLBs)(PLBs)

• Programmable Programmable Input/Output CellsInput/Output Cells

• Programmable Programmable InterconnectInterconnect

Typical Complexity = 5M - 100M transistorsTypical Complexity = 5M - 100M transistors

11100110100010001001010100010111110011010001000100101010001011100010100101010101001001000100010001010010101010100100100010001010100100100110010010000111100101010010010011001001000011110001100101000100001100100010100010110010100010000110010001010001001001001000101001010101001001000100100100010100101010100100100101000101001010001010010100100010100010100101000101001010010001001010101110101010101010101010100101010111010101010101010101010101111011111000000000000001101010111101111100000000000000110100111110000100111000001110010010011111000010011100000111001001010000000011111001001000101000101000000001111100100100010100111001001010000111100011100010011100100101000011110001110001001010101010101010101001010010101101010101010101010100101001010101001001010101010101010010010010100100101010101010101001001001

Basic FPGA OperationBasic FPGA OperationLoad Configuration MemoryLoad Configuration Memory• Defines system functionDefines system function

Input/Output CellsInput/Output Cells Logic in PLBsLogic in PLBs Connections between Connections between

PLBs & I/O cellsPLBs & I/O cellsChanging configuration Changing configuration

memory => changes memory => changes system functionsystem function

• Can change at anytimeCan change at anytime Even while system Even while system

function is in operationfunction is in operation Run-time Run-time

reconfiguration (RTR)reconfiguration (RTR)

Programmable Logic BlocksProgrammable Logic Blocks• PLBs can perform any logic PLBs can perform any logic

functionfunction Look-Up Tables (LUTs)Look-Up Tables (LUTs)

Combinational logicCombinational logic Memory (RAM)Memory (RAM)

Flip-flopsFlip-flops Sequential logicSequential logic

Special logicSpecial logic Add, subtract, multiplyAdd, subtract, multiply Count up and/or downCount up and/or down Dual port RAMDual port RAM

• Must be tested in all modes of Must be tested in all modes of operationoperation

• #PLBs/FPGA: 100 to 50,000#PLBs/FPGA: 100 to 50,000

LUT/RAM

FF

LUT/RAM

FF

LUT/RAM

FF

LUT/RAM

FF

PLB architecturePLB architecture

Programmable InterconnectProgrammable InterconnectWire segments & Programmable Interconnect Points (PIPs)Wire segments & Programmable Interconnect Points (PIPs)

cross-point PIPs – connect/disconnect wire segmentscross-point PIPs – connect/disconnect wire segments To turn cornersTo turn corners

break-point PIPs – connect/disconnect wire segmentsbreak-point PIPs – connect/disconnect wire segments To make long and short signal routesTo make long and short signal routes

multiplexer (MUX) PIPs select 1 of many wires for outputmultiplexer (MUX) PIPs select 1 of many wires for output Used at PLB inputsUsed at PLB inputs Primary interconnect media for new FPGAsPrimary interconnect media for new FPGAs

configurationconfigurationmemorymemoryelementelement

wire Awire A wire Bwire B

cross-point PIPcross-point PIP

wire Awire A

wire Bwire B

wire Awire A wire Bwire B

break-point PIPbreak-point PIP

wire Awire A wire Bwire B

outputoutput

multiplexer PIPmultiplexer PIP

wire Cwire C

BIST for FPGAsBIST for FPGAs• Basic idea:Basic idea: reprogram FPGA to test itself reprogram FPGA to test itself• BIST logic disappears after testBIST logic disappears after test

No area overhead or performance penaltiesNo area overhead or performance penalties• Applicable to all levels of testingApplicable to all levels of testing

A generic test for a generic componentA generic test for a generic component Independent of system functionIndependent of system function

• Good diagnostic resolutionGood diagnostic resolution Logic:Logic: Look-Up Table (LUT) or flip-flop Look-Up Table (LUT) or flip-flop Routing:Routing: wire segment or switch wire segment or switch Reconfigure system function for fault-toleranceReconfigure system function for fault-tolerance

• CostCost: memory to store BIST configurations: memory to store BIST configurations

BIST Architecture for PLBsBIST Architecture for PLBs

TPGsTPGsBUTsBUTsORAsORAsBUTsBUTsORAsORAsBUTsBUTsORAsORAsBUTsBUTs

TPGsTPGs

BUTsBUTsORAsORAsBUTsBUTsORAsORAsBUTsBUTsORAsORAsBUTsBUTs

TPGTPG TPGTPG

BUTBUT

BUTBUT

ORAORA

BUTBUT

BUTBUT

ORAORA

BUTBUT

BUTBUT

ORAORA

BUTBUT

BUTBUT

ORAORA

Configure row (or columns) of PLBs as:Configure row (or columns) of PLBs as:Test Pattern Generators (TPGs)Test Pattern Generators (TPGs)Output Response Analyzers (ORAs)Output Response Analyzers (ORAs)Blocks Under Test (BUTs)Blocks Under Test (BUTs)

Reverse rolls after testing 1Reverse rolls after testing 1stst set of BUTs set of BUTs

Diagnostic ProcedureDiagnostic Procedure

Step 1:Step 1: Record ORA results Record ORA results

B1

O2

B3

O4

B5

O6

B7

O8

B9

O10

B11

O12

B13

O14

B15

O16

B17

O18

B19

1 2 3 4 5 6 7 8Test #

Step 2:Step 2: Mark known good BUTs Mark known good BUTs

0 0 0 0 0 0 0 0

0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0

0 1 0 1 0 0 0 0

1 1 1 0 1 0 1 0

0 0 1 0 0 0 0 0

1 0 0 0 1 0 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0

0 0 0 0

0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0

0 0 0

0 0

0 0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0

0 0 0 0

0 0 0 0 0 0 0

Step 3:Step 3: Mark implied good BUTs Mark implied good BUTs

MULTIple faulty CELL LOcatorMULTIple faulty CELL LOcator

MULTICELLOMULTICELLO

0 0 0 0 0 0 0

0 0 0 0 0 1 1

0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

1 0 0 0 1 0 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

1 0 1 0 1 0 1 0

0 1 0 0 0 0 0 0

0 0 0 ? 0 0 0 0

0 0 0 0 0 ? 1 1

0 0 0 ? 0 0 0 0

0 0 0 1 0 0 0 0

1 0 0 0 1 0 1 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

1 0 1 0 1 0 1 0

0 1 0 0 0 0 0 0

Step 4:Step 4: Mark known faulty BUTs Mark known faulty BUTs

Step 5:Step 5: Look for inconsistences Look for inconsistences=>=> implies possible interconnect faultsimplies possible interconnect faults

Step 6:Step 6: If every PLB has been identified as If every PLB has been identified as fault-free or faulty, the group of faulty fault-free or faulty, the group of faulty PLBs has been uniquely diagnosedPLBs has been uniquely diagnosed

=>=> otherwise mark as unknownotherwise mark as unknown

Routing BIST ArchitectureRouting BIST Architecture• Wires Under Test (WUTs)Wires Under Test (WUTs)

Wire segments connected via PIPs & PLBs to form WUTsWire segments connected via PIPs & PLBs to form WUTs Opposite values on busses not under test (PIPs stuck-on)Opposite values on busses not under test (PIPs stuck-on) All WUTs are 2-tested to detect equivalent faultsAll WUTs are 2-tested to detect equivalent faults

• TPGs & ORAs formed as in logic BISTTPGs & ORAs formed as in logic BIST Exhaustive test patterns detect shorts, opens, & stuck-at faultsExhaustive test patterns detect shorts, opens, & stuck-at faults ORA compares two sets of WUTs (A WUTs & B WUTs)ORA compares two sets of WUTs (A WUTs & B WUTs)

PLBPLB

TPGTPG ORAORA

A WUTsA WUTs

B WUTsB WUTs

ORA TPGSTAR

Routing BIST ArchitectureRouting BIST ArchitectureRouting BIST ArchitectureRouting BIST Architecture

Uses small Self-Test AReas (STARs) to test Uses small Self-Test AReas (STARs) to test routing resources routing resources

• Good diagnostic resolutionGood diagnostic resolution To STARTo STAR

• Higher speed testingHigher speed testing Fewer series PIPs delaysFewer series PIPs delays

Run STARs in parallelRun STARs in parallel• V-STARs test vertical routingV-STARs test vertical routing• H-STARs test horizontal routingH-STARs test horizontal routing

Uses small Self-Test AReas (STARs) to test Uses small Self-Test AReas (STARs) to test routing resources routing resources

• Good diagnostic resolutionGood diagnostic resolution To STARTo STAR

• Higher speed testingHigher speed testing Fewer series PIPs delaysFewer series PIPs delays

Run STARs in parallelRun STARs in parallel• V-STARs test vertical routingV-STARs test vertical routing• H-STARs test horizontal routingH-STARs test horizontal routing

ORA TPGSTAR

ORA TPGSTAR

ORA TPGSTAR

ORA TPGSTAR

ORA TPGSTAR

Diagnostic ConfigurationsDiagnostic Configurations• Partition into smaller STARsPartition into smaller STARs

Identify faulty region of WUT Identify faulty region of WUT

TPGTPG

ORAORA

TPGTPG

ORAORA

TPGTPG

ORAORA

SingleSingle

wirewire

TPGTPG

ORAORA

TPGTPG

ORAORA

ORAORA

ORAORA

ORAORA

• Re-route portions of netRe-route portions of net Identify faulty wire segment or PIPIdentify faulty wire segment or PIP

• Add ORAs & change directionsAdd ORAs & change directions Identify fault region of WUTIdentify fault region of WUT

TPGTPG ORAORA ORAORA ORAORA

TPGTPGORAORAORAORAORAORA ORAORAORAORA

ORAORAORAORA

Test Results for Faulty FPGAsTest Results for Faulty FPGAsFailures from Chip 1Failures from Chip 1 At least 1 faultAt least 1 fault

maybe at intersection of STARsmaybe at intersection of STARs

  11 33 55 77 99 1111 1313 1515 1717 1919

11

33                          

55

77                          

99                          

1111                          

1313                          

1515                          

1717                          

1919                          

V-STAR column positionV-STAR column position

H-S

TA

R r

ow

po

siti

on

H-S

TA

R r

ow

po

siti

on

11 33 55 77 99 1111 1313 1515 1717 1919

11                          

33                          

55                          

77                          

99

1111                          

1313                          

1515                          

1717                          

1919                          

H-S

TA

R r

ow

po

siti

on

H-S

TA

R r

ow

po

siti

on

V-STAR column positionV-STAR column position

Failures from Chip 2Failures from Chip 2 At least 2 faultsAt least 2 faults

maybe at intersection of STARsmaybe at intersection of STARsDiagnostic resultsDiagnostic results A short at row 10 column 8A short at row 10 column 8

Diagnostic resultsDiagnostic results A short at row 1 column 12A short at row 1 column 12 Short in 3 wires of 4-wire busShort in 3 wires of 4-wire bus

row 5 columns 6-8row 5 columns 6-8

110111010000100010110101System or BIST configSystem or BIST config

FPGAFPGA

Fault Injection EmulatorFault Injection Emulator• Faulty FPGA are difficult to findFaulty FPGA are difficult to find

1 FPGA with faulty PLB & 2 FPGAs with faulty routing1 FPGA with faulty PLB & 2 FPGAs with faulty routing

• We created a Fault Injection EmulatorWe created a Fault Injection Emulator Intercepts & modifies configuration bits prior to downloadIntercepts & modifies configuration bits prior to download Fault Emulator can create multiple faults in:Fault Emulator can create multiple faults in:

PLBs: PLBs: LUTs, flip-flops, etc.LUTs, flip-flops, etc. Interconnect: Interconnect: PIPs stuck-on & stuck-offPIPs stuck-on & stuck-off

011001101110011001000000Stuck-at valuesStuck-at values

000010000100000010000100Fault maskFault mask

110111011100100010000101

Download fileDownload file 1101 1101

11001001

00000101faultsfaults

BIST DemonstrationBIST Demonstration• Graphic User InterfaceGraphic User Interface

Shows what is happening inside FPGA during testShows what is happening inside FPGA during test Provides interface to fault injection emulationProvides interface to fault injection emulation

• Fault Injection EmulatorFault Injection Emulator Inserts faults into configuration data fileInserts faults into configuration data file Emulated faults are downloaded with BIST phasesEmulated faults are downloaded with BIST phases

• Logic BISTLogic BIST MULTICELLO diagnostic algorithm incorporatedMULTICELLO diagnostic algorithm incorporated

• Current demo for Xilinx 4010XL FPGACurrent demo for Xilinx 4010XL FPGA 20x20 PLB array with 100K PIPs & 25K wire segments20x20 PLB array with 100K PIPs & 25K wire segments BIST phases automatically generated for any 4000 BIST phases automatically generated for any 4000

series FPGA by programs we have developedseries FPGA by programs we have developed