Built-In Self-Test for Radio

Frequency System-On-Chip

Bruce Kim

The University of Alabama

2

Outline

• Proposed BIST Architecture

• Developed Equations

• Measurement Results

• Conclusions

3

Motivatio

nToday

System-On-Board (SOB)

Future

System-On-Chip (SOC)

4

RF

Testing

• Expensive

• Labor intensive

5

What is BIST (Built-In Self-Test)?

A test technique which allows the SOC to

evaluate its own quality without expensive

external equipment.

6

Test Flow

Functional Test

Proposed BIST

(Go-No Go)

SingulatedWafer Level Testing

Package

Proposed BIST

Functional Testing

7

Wireless Radio

Duplexer

VGA

LO

VGA

ADC

ADC

DSP

DAC

DAC

LOPhase Shifter

LOPhase Shifter

LNA

PA

8

Proposed RF BIST for LNA

LNA

TA

PD1

PD2

S1 S2

VT1

VT2

vin Rs=50

ZL=50

DC Meter

S3

On-Chip

VL

VT

VL1

S1 closed: Measure VT1

S2 & S3 closed: Measure VT2

9

Proposed RF BIST Hardware

PD1

PD2

VT1

VT2 vT

Band-gap Reference

vL1

DN

TA

10

Equivalent Circuit Model

LNA

TA PD2 VT2

vin Rs=50

ZL=50

DVM

ZLNA

ZTA

ZTA

Vt

Rs=50

ZLNA Vin

11

Development of Equations

insLNA

LNA

inTALNAs

TALNAt

VRZ

Z

VZZR

ZZV

2

)]//([

//

20

202

2 STAinsLNA

LNA

STAtT

VGVRZ

Z

VGVV

(1)

(2)

(3)

12

Fault-Free Input Impedance

2G : Voltage gain of Test Amplifier

211 / GGK

),( 21 inT vVfG : Voltage gain of BIST

][

11 1

1

K

ZR

KRZ

TA

s

sLNA

13

Faulty-Case Input Impedance(VT2)

211 / GGK

: Voltage gain of BIST under faulty case ),( 21 inT vVfG

][

11 1

1

K

ZR

KRZ

TA

s

sLNA

14

Fault-Free Voltage Gain

),( 13 inT vVfG : Voltage gain of BIST

31 GZ

RG

LNA

sLNA

15

Faulty-Case Voltage Gain (VT1,

VT2)

: Voltage gain of BIST under faulty case ),( 13 inT vVfG

31 GZ

RG

LNA

sLNA

16

Input Return Loss

500Z

inRL : Input Return Loss of BIST

0

0log20ZZ

ZZRL

LNA

LNAin

0

0log20ZZ

ZZRL

LNA

LNAin

Fault-Free Case

Faulty Case

17

NFkTBZRR

VZSNR

LNAss

inLNAout

12

Output Signal-to-Noise Ratio

Faulty Case

Fault-Free Case

kT: -204 dB

B: signal bandwidth

NFkTBZRR

VZSNR

LNAss

inLNAout

12

18

Summary of Equations

19

5GHz Low Noise Amplifier

Amplifier

C1 LbVL

GND

Le1

Lc1 C2

Le2

Lc2 C4

C3

C5

R1

R2

R3

R4

Rb1 Rb2

Q1

Q3

Q4

Band-gap reference

VCC = 1

Q2

Output

0.18m SiGe HBT Technology

20

Small-Signal Model for 5GHz LNA

Stage 1

C1 Lb VL C2

Lc1

1cLR

bLR

Le1

Rb1

rb1

r1 C1

C1

1eLR

+ _ gm1v1 v1

Hybrid-π model for HBT with series resistance and two capacitances

Inductor model with series resistance

Stage 2: same topology as stage 1

Stage 2

21

RF BIST Circuit

Test Amplifier

VT

GND

Lc C03

C02

C06

R01

R02

R03

R04

Rb01

Q01

Q02

Q03

Band-gap reference

VCC

C04 R5

C5

VT2 Q4

R6 R7

Peak Detector2

CB

Validation Procedure & System Calibration

3/2 TT VVGain

Test VT2 for Gain=3

22

Programmable Capacitor Banks for CB VDD

D1 D2 D3

CB1

vT

RD1 RD2 RD3

RS2 RS1 RS3

M1 M2 M3

GND

CB2

vB

2Cb1

2Cb1 2Cb2

2Cb2 2Cb3

2Cb3

(D3D2D1) = (001) for 5.25GHz, (011) for 2.4GHz and (111) for 1.8GHz

23

Chip Micrograph

BIST block

TA PD2

PD1

24

Defect Models

(a) Defect-free

C

Rs=1

Rp=10M

E

B

(b) Open Defect

Rs=10M

C

E

B

(c) C-E Short Defect

Rp=1

C

E

B

Defect Models for Actives

25

Defect Models

(a) Defect-free (c) Short Defect

Rp= Z /10

(b) Open Defect

Rs=10Z

Z

Z

Z

Defect Models for Passives

26

Measurement Set-Up for LNA and TA

LNA

TA

PD1

PD2

S1 S2

VT1

VT2

vin Rs=50

ZL=50

Labview Board

S3

VL

VT

27

Fault-Free

Wafer Level Testing for Catastrophic Faults

28

Wafer Level Testing for Parametric Variations

Tolerance: 20%

Good Device

Fault Free Device

29

Results

• Measured Values mean that external equipment was used.

• Simulation results are from ADS commercial software.

• Modeling results are from the Hybrid- and other passives modeling in the LNA circuit.

30

Input Impedance of TA

31

Gain of TA

32

Input Impedances

33

Gains

34

Input Return Losses

35

Input VSWRs

36

Data Summary

Impedance Gain Return Loss SNR

Fault-Free 41.76 16.89 -20.9 96.99

Q1 – open base

terminal

70.88 -44.44 -12.9 39.80

Lb +30% tolerance

49.01 14.95 -26.7 96.07

37

ADC

DAC

Digital

Signal

Processor

IF Filter

IF Filter

RF FilterPower amp. Attenuator

RF Filter

IF Filter

RF Filter RF Filter

Phase filter

Amp.

Amp. Amp.

Amp.

Amp.

PLLPLL VCOVCOSwitch

RF Filter

Antenna

SoC Transceiver System

Auto Compensation

Parametric Variations

Amplifier

Cb1 Lb vLNAin vLNAout

GND

Le1

Lc1 C2

Le2

Lc2 C4

C3

C5

R1

R2

R3

R4

Rb1 Rb2

Q1

Q3

Q4

Band-gap reference

VCC

Q2

39

Capacitor Mirror Banks (CMB) VDD

D4 D5 DN

bCN

2 bC

N

2 bC

N

2

CB3

vout

RD4 RD4 RDN

RS4 RS4 RSN

M4 M5 MN

bCN

2 bCN

2 bCN

2

GND

CB4

vin

N = 8-bit: When (D11D10…D5D4) = (00…01), CB = Cb/8

40

Lc1 Parametric Variations

Lc1 : Most sensitive component in LNA

41

Changes of Cb1 to Compensate Gain

42

Gain Compensations

Lc1 : Most gain-sensitive component in LNA

43

Noise Figure Compensations

44

Programmable RF BIST Technique

Used for GSM, Bluetooth, IEEE802.11g

LNA

S1

S2

VT1

VT2

vin

Rs=50

ZL=50

S3

LNA Under Test

vL

vT

External Board

BIST

vL1

A/D Labview

DN

PC

CMB

45

Test Technique Comparison

NF, SNR, Sensitivity, Impedance, Gain, RL, VSWR

External Equipment RF BIST

Test Cost High Low

Test Time Large Small

Resolution High High

46

Limitation

Parameters LNA specifications Using proposed BIST

Input Impedance [] 50

Voltage Gain [dB] > 10

Noise Figure [dB] < 3 Approximate

Return Loss [dB] < -10

VSWR < 2

SNRout [dB] Not Available Approximate

Sensitivity [dBm] Not Available

IIP3 [dBm] > 0

47

On-going Work

• Construct automatic test structure with on-chip BIST structure and relays on a load board

• Develop a LabView software for test automation

48

Conclusions

• Introduced a new low-cost RF test hardware.

• Successful with programmable RF test for different standards.

• Self-compensation network for process and thermal variations.