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The 3D FDTD Buried Object Detection Forward Model used in this project was developed by Panos Kosmas and Dr. Carey Rappaport of Northeastern University. It is designed for buried object detection using 3D FDTD in different kinds of soil and buried object conditions. • The forward model simulates the whole electromagnetic space and wave propagation in the model space. (As figures in the middle of this poster) • We simplified model from 3D to 2D, which can be easily expand to 3D later. • Quantize the double floating-point precision data to fix-point data. Buried Object Detection Forward Model 64-bit floating-point 28-bit fix-point Quantization FPGA Implementation of the 3-D FDTD Algorithm Wang Chen , Dr. Miriam Leeser , Dr. Carey Rappaport [email protected] [email protected] [email protected] Abstract 3D Finite-Difference Time-Domain is a powerful method for modeling the electromagnetic field. The 3D FDTD buried object detection forward model is emerging as a useful application in mine detection and other subsurface sensing areas. However, the computation of this model is complex and time consuming. Implementing this algorithm in hardware will greatly increase its computational speed and widen its usage in many other areas. We present a FPGA implementation to speedup the FDTD algorithm. We transfer the 3D FDTD model and complete boundary conditions to the FPGA. Our FDTD core is suitable for other FDTD applications too. The computational speed on the reconfigurable hardware is greatly increased over the software implementation. Goal Speedup Finite-Difference Time- Domain (FDTD) Algorithm through the use of Field Programmable Gate Arrays (FPGAs). Future Work • Adding Different Soil and buried object conditions to the 2D Model. • Testing and comparing the speed of 2D FDTD hardware and software design. • Expanding the 2D FDTD model to 3D FDTD model. Hardware Implementation • Figures above are the hardware structure of the 2D FDTD Free space model. The basic structure has three parallel pipelines. Two pipelines are used to update Electric Field, the other one is used to update Magnetic Field. • We have 5 on-board memories and we use all of them. Four memories are used for memory updating and the last one is used to store the source field value. • The detailed structure of electric field pipeline module Exs is shown in the figure on the right side. The Quantized Fix-point Simulation FIREBIRD™/PCI Reconfigurable FPGA Computing Engine • Firebird is a product of Annapolis Micro Systems, Inc. • Firebird is the target for our hardware implementation. The features of the FIREBIRD™/PCI boards are : · Uses Xilinx® VIRTEX™-E FPGAs XCV2000E · Processing clocks up to 150MHz · Five independent memory banks (4 x 64-bit, 1 x 32-bit) · 5.4Gbytes/sec of memory bandwidth · 3Gbytes/sec of I/O bandwidth Reconfigurable Hardware Implementing the FDTD Algorithm in hardware will greatly increase its computational speed and widen its usage in many other areas. • Simplified and Quantized the 2D FDTD model as first step. • Designed, simulated and synthesized modules for: Electrical field update, Magnetic field update, Memory interface Boundary condition and Full datapath. 2D FDTD Model Hardware Structure FIREBIRD BO ARD FPG A DESIG N MEMORY HOST PCIBUS MEMORY S tate m achine Electrica l Field M odule P ipe lined M ag netic Field M odule P ipe lined Work in Progress Reference • Complete the 2D FDTD TE Wave model in hardware. • Working on TM Wave model, with different structure shown below. Electric Field M em 0 Electric Field M em 2 M agnetic Field M em 1 M agnetic Field M em 3 Source Data M em 4 Pipeline Exs Pipeline Ezs P ipeline H ys BlockR am 0 BlockR am 1 BlockR am 2 BlockR am 3 Source Adder 2D TE Wave Hardware Structure This work was supported in part by CenSSIS, the Center for Subsurface Sensing and Imaging Systems, under the Engineering Research Centers Program of the National Science Foundation (Award Number EEC-9986821). Hin_2 Hin_3 Hin_4 DTin_2 DTin_1 - - x x - + E_in1 Eout dt11 hp11 hm 21 hp31 hm 41 dt21 e12 dt22 hr22 r21 r11 hr12 dt12 r12 r22 hr23 hr13 r13 hr14 r14 0 O ut_ok1 O ut_ok2 D one reg_ok Ready Hin_1 1 2 3 4 5 6 e13 e14 e15 e16 e17 e11 O ut_ok3 O ut_ok4 O ut_ok5 O ut_ok6 O ut_ok7 e18 O ut_ok8 e19 O ut_ok9 7 8 9 W rite to Exs_m em R ead H ysM em Read HysM em R ead ExsM em Hys(k-1) H ys Exs - + CEin_1 hr15 10 x 11 12 13 14 15 16 17 O ut_ok10 O ut_ok11 O ut_ok12 O ut_ok13 O ut_ok14 O ut_ok15 O ut_ok16 O ut_ok17 C DTin C Ein_2 e21 e22 e25 e26 e24 e23 e27 e28 e29 e210 e31 e32 e33 e34 e35 e36 e37 e38 e39 e310 e311 e312 e313 e314 e315 e316 e317 dt31 dt32 dt33 dt34 dt35 dt36 dt37 dt38 dt39 dt310 dt311 r15 hr16 r16 hr17 r17 BlockR am BlockR am BlockRam Electric Field Pipeline Module [1] Ryan N. Schneider, Laurence E. Turner, Michal M.Okoniewski, “Application of FPGA Technology to Accelerate the Finite- Difference Time-Domain (FDTD) Method”, FPGA 2002. [2] Karl S. Kunz, Raymond J. Luebbers, “The Finite Difference Time Domain Method for Electromagnetics”, CRC Press, 1993." Hardware design 2D TM Wave Hardware Structure Electric Field M em 0 Electric Field M em 2 M agnetic Field M em 1 M agnetic Field M em 3 Source D ata M em 4 Pipeline E ys P ipeline H xs BlockR am 0 BlockR am 1 BlockR am 3 Source Adder P ipeline H zs BlockR am 1
