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Business trends in Advanced Packaging

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  • Le Quartz, 75 Cours Emile Zola

    69100 Villeurbanne, France

    Tel : +33 472 83 01 80 - Fax : +33 472 83 01 83

    Web: http://www.yole.fr

    Semi Networking Day

    Packaging Key for System Integration

  • 2013 22013 Copyrights Yole Dveloppement SA. All right reserved.

    Christophe Fitamant

    Sales & Marketing Director, Yole Dveloppement

    Christophe Fitamant joined Yole Dveloppement in 2013 to lead Mdia and Sales activities. He holds

    an engineering degree of INP Grenoble - Phelma - with a major in Chemical Process Engineering. He

    has worked at IBM Corbeil-Essonnes, and Applied Materials. Hes lived in California when he managed

    the Applied etch product support group for Taiwan and Japan. Back to France for Lam Research he

    first took the responsibility of the ST Crolles site, before taking the Sales Account Management for

    Europe. With the acquisition of SEZ in Austria by Lam in 2008, he led Sales and Marketing for Lam

    penetration in MEMS and Advanced Packaging for Clean.

    Semi Networking Day

  • 2013 3

    Fields of Expertise

    Yole Developpement is a market, technology and strategy consultingcompany, founded in 1998. We operate in the following areas:

    Our expertise is based on research done by our in-house analysts,conducting open-ended interviews with most industry players.

    30+ full time analysts with technical and marketing degrees

    Primary research including over 3,500 interviews per year

    MEMS & image sensors

    Photovoltaic

    Advanced Packaging

    Microfluidic

    & Med Tech

    Power Electronics

    HB LED, LED & LD Equipment and materials

  • 2013 42013 Copyrights Yole Dveloppement SA. All right reserved.

    Yole Activities in a Nutshell

    MEDIANews feed / Magazines / Webcasts

    REPORTSMarket & technology

    Patent Analysis

    Reverse costing report

    CONSULTINGMarket research

    Technology & Strategy

    Patent Analysis

    www.yole.fr

    YOLE FINANCE M&A / Due Diligence /

    Fund raising services

  • 2013 52013 Copyrights Yole Dveloppement SA. All right reserved.

    Rozalia Beica

    Chief Technical Officer, Yole Dveloppement

    Rozalia Beica is the CTO and Business Unit Manager leading Advanced / 3D Packaging and

    Semiconductor Manufacturing activities within Yole Dveloppement. For more than 15 years she has

    been involved in research, strategic marketing and application of WLP and 3D/TSV at materials (Rohm

    and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim

    IC) organizations.

    Rozalia has authored over 50 papers and publications and she is actively participating in several 3D &

    Advanced Packaging Committees worldwide.

    Rozalia holds a M.Sc. in Chemical Engineering (Romania), a M. Sc. In Management of Technology

    (USA) and a GXMBA from IE University (Spain).

    Semi Networking Day

  • 2013

    Copyrights Yole Dveloppement SA. All rights reserved.

    Business Trends in Advanced

    Packaging

    Courtesy of Fraunhofer-IZM

    Rozalia Beica

    SEMI Networking Day: Packaging - Key for System Integration

    Porto June 27, 2013

    Nokia

  • 2013 7Copyrights Yole Dveloppement SA. All rights reserved.

    Presentation Outline

    FCI NXP

    Advanced Packaging

    Platforms

    Emerging Packaging

    Technologies

    FOWLP

    Market Forecasts

    Cost Considerations

    IP Activities

    Conclusions

  • 2013 8Copyrights Yole Dveloppement SA. All rights reserved.

    Introduction

    Wafer-level-packaging market is gaining more and more significance in the semiconductor industry; it

    shows the greatest potential for significant future growth in the semiconductor industry.

    Historically supported by the market growth in flip-chip wafer bumping with electroplated gold, solder

    bumps and today copper pillars; wafer-level-packages are actually coming in many different, namely

    Fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D Glass / Silicon interposers and of course

    3DIC integration with TSV interconnects.

    The evolution of semiconductor packaging technologies over the past 40 years has

    been driven by the need to bridge the increasing I/O interconnect gap, between the

    fast decreasing silicon geometries (Moores law) and the slower shrink of the Printed

    Circuit Board technologies

  • 2013 9Copyrights Yole Dveloppement SA. All rights reserved.

    2011 2012 2013 2014 2015 2016 2017

    TOT Semiconductor IC wafers 84 92 101 111 122 135 148

    TOT Wafer-Scale-Packaged IC wafers 13 14 17 21 25 31 35

    % ratio 15% 16% 17% 19% 20% 23% 23%

    0%

    5%

    10%

    15%

    20%

    25%

    30%

    35%

    40%

    45%

    50%

    0

    20

    40

    60

    80

    100

    120

    140

    160

    % p

    enet

    rati

    on

    Rat

    io

    Waf

    er

    ship

    me

    nts

    (i

    n M

    un

    its

    of

    30

    0m

    m w

    afer

    s eq

    .)

    % Ratio of WW Semiconductor IC Wafers Packaged at the Wafer-Scale(Volume in millions of 300mm wafers eq.)

    Yole Dveloppement October 2012

    Wafer-Level-PackagingIn the semiconductor IC wafer processing industry

    In 2012, ~ 16% of overall semiconductor IC wafers were manufactured with packaging features

    (bumping, RDL, TSV, etc) processed at the wafer-scale

    CAGR

    21%

    10%

  • 2013 10Copyrights Yole Dveloppement SA. All rights reserved.

    Advanced Packaging Platforms

    PANEL / WLP Platforms

    Wafer-Level Electrical Redistribution

    Flip-chip & Wafer-LevelStacking / Integration

    WL CSPFan-in

    FOWLPFan-out

    Glass / Silicon Flip-chip wafer bumping

    on BGA

    3D IC

    & TSVEmbedded die in PCB / laminate

    Wafer-Level Interface / Encapsulation

    3D WLPFor MEMS & sensors

    (also called 3D SiP sometimes)

    LED & Sensors

    WLOptics 2.5D interposers

    Historically supported by flip-chip wafer bumping with electroplated gold & solder bumps, today

    there are an array of solutions, such as: copper pillars, Fan-in WLCSP packages, 3D WLP, FO-WLP

    packages, 2.5D Glass / Silicon interposers and 3DIC with TSV interconnects

    Wafer-level-packages have emerged in many different varieties that can be categorized

    into different advanced packaging technology platforms

  • 2013 11Copyrights Yole Dveloppement SA. All rights reserved.

    WLP Middle-End Technologies

    FEwafer manufacturing

    Middle-end

    BEassembly & testetch

    implant

    CVD

    PVD

    CMP

    Wafer test

    TSV bumpingRDL / wiring C2W

    C2C / C2S

    underfill molding Final testhandling

    thinning BGAdicing

    inspection

    cleaning

    Middle-end vs Front-End vs Back-End

    inspection W2W

    Courtesy of Stats ChipPAC

    Wafer level packages are true Middle-end technologies, leverage similar type of process

    manufacturing know-how

    Middle-end is a strategic area where Foundries, OSATs, WLP Houses and IDMs stepped in,

    an infrastructure that has emerged by itself in the last 5 years.

    Middle-end infrastructure is growing and is the leading driver and the fastest growingsemiconductor packaging technology with more than 18% CAGR in units over the next 6 years

    Middle end technologies are found in the overlap area between the IDMs or CMOS foundries back-

    end of line (BEOL) wafer fabs and the the back-end wafer bumping assembly facilities of the OSATs

    and wafer bumping houses

  • 2013 12Copyrights Yole Dveloppement SA. All rights reserved.

    Technological Differences

    Bump

    characteristics

    Plating

    pitch: < 60m

    WAFER BUMPING

    FLIP CHIP WAFER LEVEL PACKAGING

    FC BGA FC CSP FAN IN FAN OUT

    Bump

    characteristics

    Plating, screen

    printing

    pitch:

  • 2013 13Copyrights Yole Dveloppement SA. All rights reserved.

    Middle-end Infrastructure is Growing

    Significant growth of 3D Packages: 3D IC, Embedded (3D SIP and FOWLP) and Interposers

    0,0

    5,0

    10,0

    15,0

    20,0

    25,0

    30,0

    35,0

    40,0

    2011 2012 2013 2014 2015 2016 2017

    Vo

    lum

    e (i

    n M

    un

    its

    of

    30

    0m

    m w

    afer

    eq

    .)

    Global Wafer-Level-Packaging Demand(in Munits of 300mm wafer eq. )

    Yole Dveloppement October 2012

    3DIC

    Flip-chip

    2.5D interposers

    3D WLP

    WL CSP

    FO WLP

    3D SiP

    Mid-End infrastructure the leading driver and the fastest growing semiconductorpackaging technology with more than 18% CAGR in units over the next 6 years

  • 2013 14Copyrights Yole Dveloppement SA. All rights reserved.

    In 2012, the equipment market is lower compared to the market in 2011 due to the high

    investment made in 2011 for 3D IC & WLP applications.

    TOT $867 M $642 M $863 M $1,204M $1,721M $2,578M $3,782M

    Equipment Market Needs for WLP

    28%

    $0 M

    $500 M

    $1 000 M

    $1 500 M

    $2 000 M

    $2 500 M

    $3 000 M

    $3 500 M

    $4 000 M

    2011 2012 2013 2014 2015 2016 2017

    Sale

    s fo

    reca

    sts

    (M$

    )

    Global Equipment Market Forecastfor 3DIC & Wafer-Level-Packaging (in M$)

    3DIC TSV stacks

    FO WLP / SiP

    3D WLP

    Fan-in WL CSP

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