by Carlos Pardo Presentation for - KDPOF! 3.5 bits/symbol 16-PAM! 312.5 MBaud P O F the knowledge...

PO

Fthe knowledge development

Robust High Speed Communications Technology over POF

A standardised solution

by Carlos Pardo

AtlantaSeptember 2012

Presentation for:

domingo 9 de septiembre de 12

Sept 2012

PO

F

the knowledge development

Agenda•The DKE/VDE standard

•The ETSI standard

•Quasar-POF association

•The next standardisation steps

•Performance

•Products

2


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F


The DKE/VDE Standard


Sept 2012

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The DKE/VDE Standard - Architecture

4

PCS:

PMA:

Physical Coding Sublayer

Physical Medium Attachment

Input 0processing

Input 1processing

Input N-1processing In

terfa

ces

Mul

tiple

xer

THPrecoding

Power Scaling

Payload data-pathGMII Rate

Adapt

Symbol Scramb

I2C Modulation

MLCC Enc

Data Encap

Bin Scramb

DVP

MOST


Sept 2012

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4

PCS:

PMA:



Control & SystemInformation

Physical Header data-path

CRC-16 Binary Scrambler

2-PAM Modulation

BCH Encoder

Phy Header Builder

Power Scaling

Input 0processing

Input 1processing


terfa

ces

Mul

tiple

xer

THPrecoding

Power Scaling


Adapt

Symbol Scramb

I2C Modulation

MLCC Enc

Data Encap

Bin Scramb

DVP

MOST


Sept 2012

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4

PCS:

PMA:



Pilot S1Generator

Pilot S2Generator

Power Scaling

Power Scaling

Pilo

ts d

ata-

path




2-PAM Modulation

BCH Encoder

Phy Header Builder

Power Scaling

Input 0processing

Input 1processing


terfa

ces

Mul

tiple

xer

THPrecoding

Power Scaling


Adapt

Symbol Scramb

I2C Modulation

MLCC Enc

Data Encap

Bin Scramb

DVP

MOST


Sept 2012

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4

PCS:

PMA:



PMD: Physical Medium Dependent

PMD

Fram

e Bu

ildin

g

POF

Pilot S1Generator

Pilot S2Generator

Power Scaling

Power Scaling

Pilo

ts d

ata-

path




2-PAM Modulation

BCH Encoder

Phy Header Builder

Power Scaling

Input 0processing

Input 1processing


terfa

ces

Mul

tiple

xer

THPrecoding

Power Scaling


Adapt

Symbol Scramb

I2C Modulation

MLCC Enc

Data Encap

Bin Scramb

DVP

MOST


Sept 2012

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The DKE/VDE Standard - FEC

5

Standard for Gigabit Ethernet over POFTechnical Overview

www.kdpof.com

“approaching the Shannon limit”

260 270 280 290 300 310 320 330 340 350

−15

−13

−11

−9

−7

−5

−3

−1

1

3

5

7

9

11

13

15

260 270 280 290 300 310 320 330 340 350−1

−0.9375−0.875−0.8125−0.75

−0.6875−0.625−0.5625

−0.5−0.4375−0.375−0.3125−0.25

−0.1875−0.125−0.0625

00.06250.1250.18750.25

0.31250.3750.4375

0.50.56250.6250.68750.75

0.81250.8750.9375

1

BCH encoder

BCH encoder

QPSK mapper

B/QPSK mapper

Z2/RZ2 mapper

Transf.

Level 3

Level 2

Level 1

(nc(2), !(2))

(nc(1), !(1))

Transf.

Transf.

Transf.

!(1)

!(2)

!(3)

!1t (1)

!1t (2)

!1t (3)

!2t

1008 2D symbols/ codeword

nc(1)

nc(2)

nc(3)

nb(1)=1

nb(2) = 0.5 or 1

nb(3)

MLC

C d

emux

Z2/RZ2 to M-PAM mux

2016 1D symbols/codeword

Symbol Scrambler mod-!p

Adaptive MLCC (encoding)

−2 0 2 4 6 8 10 12 14 1610−16

10−14

10−12

10−10

10−8

10−6

10−4

10−2

3.5 bits/dim, 16−PAM, 3.31448 b/s/Hz/dim, MLCC 2016, Error−rate vs. SNR norm

SNRnorm (dB)

Err

or R

ate

BER − UncodedShannon−BoundSphere−BoundBER − Output level 1BER − Output level 2BER − Output level 3MLCC BER

Multi Stage Decoding of MLCC

10−16 10−14 10−12 10−10 10−8 10−6 10−410−20

100

1020

1040

1060

1080

101003.5 bits/dim, 16−PAM, 3.31448 b/s/Hz/dim, MLCC 2016, 312.5 MSymb/s, MTTFPA vs. BER

MLCC BER

MTT

FPA

(yea

rs)

Lifetime of universeMLCC w/o BCH detectMLCC w/ BCH detectAfter CRC−8(6) w/o BCH detectAfter CRC−8(6) w/ BCH detect

16-PAM

Tomlinson-Harashima Precoding

SystemInformation

Payload data-path


Pilo

ts d

ata-

path

PCS:

PMA:



GMII Rate Adapt


Fram

e B

uild

ing

MDI

CRC8(6)

Transmission Block DiagramFlexible, Capacity Achieving, Low Cost and Green Implementability

RX MLCC Level 10.8254 bits/s/Hz/1D



Bit Error Rate performance Mean Time To False Packet AcceptanceMLCC 2D constellation3.5 bits/1D - 128-QAM

MLCC coset partitioning3.5 bits/1D

Video

SPI

CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 CW10 CW11

S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16

timeFrame j

Frame Structure (normal mode)

Pilot S1:!Frame synchronization!Timing recovery

Payload: Adaptive THP - MLCC!Multi-protocol encapsulation:

!Ethernet, Video, SPI, I2C, ...

Phy Header:!Link startup!THP and MLCC negotiation!Decapsulation synchronization

Pilot S2:!Non linear channel estimation!Equalizer adaptation!Timing recovery

CW0 CW1 CW2 CW3 CW8 CW9 CW10 CW11

S1 PHS0 PHS1S20

timeFrame j

Frame Structure (low power mode)

CW98 CW99

PHS12 PHS13S212

CW108 CW109

sleep

sleep sleep

sleep wake

8064 symbols

wake

wake

On every S1, S2 and PHS system wakes up to be able to track clock and equalizers

Link Power BudgetOptimization based on Information Theory

200 400 600 800 1000 120011

12

13

14

15

16

17

18

19

20

21

Symbol Rate (MHz)

dB

o

1Gbps Link Budget

LED−RED 50.00 MHz UMD NA 0.3



2-PAM1 bit/1D

4-PAM1.5 bits/1D

4-PAM2 bits/1D

8-PAM2.5 bits/1D

8-PAM3 bits/1D

16-PAM3.5 bits/1D

Modulation scheme, error correcting codes and symbol rate were designed to provide the maximum link power budget at 1Gbps:! 3.3145 bits/s/Hz/dim! 3.5 bits/symbol 16-PAM! 312.5 MBaud

POF

the knowledge development THIS WORK HAS BEEN CARRIED OUT UNDER THE COORDINATION OF VDE/DKE WG 412.7.1

POF


Modulation Pre-equalization

Bit

stre

am

Knowledge Development for POF ©


Sept 2012

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The DKE/VDE Standard - Optimality

6

Standard for Gigabit Ethernet over POFTechnical Overview

www.kdpof.com


260 270 280 290 300 310 320 330 340 350

−15

−13

−11

−9

−7

−5

−3

−1

1

3

5

7

9

11

13

15

260 270 280 290 300 310 320 330 340 350−1

−0.9375−0.875−0.8125−0.75

−0.6875−0.625−0.5625

−0.5−0.4375−0.375−0.3125−0.25

−0.1875−0.125−0.0625

00.06250.1250.18750.25

0.31250.3750.4375

0.50.56250.6250.68750.75

0.81250.8750.9375

1

Level 3

Level 2

Level 1

(nc(2), !(2))

(nc(1), !(1))

!(1)

!(2)

!(3)

!1t (1)

!1t (2)

!1t (3)

!2t

1008 2D symbols/ codeword

nc(1)

nc(2)

nc(3)

nb(1)=1

nb(2) = 0.5 or 1

nb(3)

MLC

C d

emux

2016 1D symbols/codeword

Adaptive MLCC (encoding)

−2 0 2 4 6 8 10 12 14 1610−16

10−14

10−12

10−10

10−8

10−6

10−4

10−2


SNRnorm (dB)

Err

or R

ate



10−16 10−14 10−12 10−10 10−8 10−6 10−410−20

100

1020

1040

1060

1080


MLCC BER

MTT

FPA

(yea

rs)


16-PAM

Tomlinson-Harashima Precoding

SystemInformation

Payload data-path


Pilo

ts d

ata-

path

PCS:

PMA:



GMII Rate Adapt


Fram

e B

uild

ing

MDI

CRC8(6)

Transmission Block DiagramFlexible, Capacity Achieving, Low Cost and Green Implementability




Bit Error Rate performance Mean Time To False Packet AcceptanceMLCC 2D constellation3.5 bits/1D - 128-QAM

MLCC coset partitioning3.5 bits/1D

Video

SPI


S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16

timeFrame j

Frame Structure (normal mode)

Pilot S1:!Frame synchronization!Timing recovery

Payload: Adaptive THP - MLCC!Multi-protocol encapsulation:

!Ethernet, Video, SPI, I2C, ...

Phy Header:!Link startup!THP and MLCC negotiation!Decapsulation synchronization

Pilot S2:!Non linear channel estimation!Equalizer adaptation!Timing recovery


S1 PHS0 PHS1S20

timeFrame j

Frame Structure (low power mode)

CW98 CW99

PHS12 PHS13S212

CW108 CW109

sleep

sleep sleep

sleep wake

8064 symbols

wake

wake

On every S1, S2 and PHS system wakes up to be able to track clock and equalizers

Link Power BudgetOptimization based on Information Theory

200 400 600 800 1000 120011

12

13

14

15

16

17

18

19

20

21

Symbol Rate (MHz)

dB

o

1Gbps Link Budget




2-PAM1 bit/1D

4-PAM1.5 bits/1D

4-PAM2 bits/1D

8-PAM2.5 bits/1D

8-PAM3 bits/1D

16-PAM3.5 bits/1D

Modulation scheme, error correcting codes and symbol rate were designed to provide the maximum link power budget at 1Gbps:! 3.3145 bits/s/Hz/dim! 3.5 bits/symbol 16-PAM! 312.5 MBaud

POF

the knowledge development THIS WORK HAS BEEN CARRIED OUT UNDER THE COORDINATION OF VDE/DKE WG 412.7.1

POF


Modulation Pre-equalization

Bit

stre

am


−2 0 2 4 6 8 10 12 14 1610−16

10−14

10−12

10−10

10−8

10−6

10−4

10−2


SNRnorm (dB)

Err

or R

ate



10−16 10−14 10−12 10−10 10−8 10−6 10−410−20

100

1020

1040

1060

1080


MLCC BER

MTT

FPA

(yea

rs)





Bit Error Rate performance Mean Time To False Packet Acceptance

KDPOF technology approaches the SISO Shannon’ limit with affordable silicon

implementation


Sept 2012

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The DKE/VDE Standard- Frame structure

7

• Continuous timing and channel estimation and equalisation tracking

• Robust negotiation among link partners

• Very fast link startup

• Optimum for large core fibres

• Very simple implementation

• Clock frequency tolerance +-1000 ppm based on data-aided recovery algorithms


Sept 2012

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7


S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16

Frame j 8064 symbols

160 symbols








Sept 2012

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7

Pilot S1:✦ Frame synchronisation✦ Timing recovery


S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16


160 symbols








Sept 2012

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7


Pilot S2:✦ Non linear channel estimation✦ Equaliser adaptation✦ Timing recovery


S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16


160 symbols








Sept 2012

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7


Phy Header:✦ Link startup✦ THP and MLCC negotiation✦ Decapsulation synchronisation



S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16


160 symbols








Sept 2012

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7


Payload: Adaptive THP - MLCC✦ Multi-protocol encapsulation:

✦ Ethernet, Video, SPI, I2C, ...

Phy Header:✦ Link startup✦ THP and MLCC negotiation✦ Decapsulation synchronisation



S1 PHS0 PHS1S20

CW12 CW13 CW14 CW15

S21

CW16


160 symbols








Sept 2012

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The DKE/VDE Standard - Low power modes

8


S1 PHS0 PHS1S20

timeFrame j

CW98 CW99

PHS12 PHS13S212

CW108 CW109sleep

sleep sleep

sleep wake

8064 symbols

wake

wake

•Same principle of EEE: Low Power Idle (LPI)

•On every S1, S2 and PHS, the PHY wakes up transmission to be able to make clock and equalisers tracking


Sept 2012

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The DKE/VDE Standard - Energy Saving•KDPOF EE vs. 1Gbps EEE:

• Poisson arrivals• Use 600 byte frames (average frame size)

9

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

20

30

40

50

60

70

80

90

100

Link load

Powe

r con

sum

ptio

n re

lativ

e to

act

ive

mod

e

EE-POFEEE-1G


Sept 2012

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The DKE/VDE Standard - Energy Saving•LPI is evaluated for different packet sizes:

• Poisson arrivals• 64, 600 and 1500 bytes per Ethernet frame

10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

20

30

40

50

60

70

80

90

100

Link load

Powe

r con

sum

ptio

n re

lativ

e to

act

ive

mod

e

64 byte600 byte1500 byte


Sept 2012

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Standardisation•2010 VDE starts a group in Germany for Gigabit over SI-POF

• Franhoufer institute• Simenes, University of Leipzig• Torino and Nuremberg Universities• KDPOF

• Avago• Firecomms• Phoenix Contact• Others ...

•Finally 16 PAM - THP - MLCC & Advanced Frame Structure solution was selected: 1Gbps Ethernet level full duplex.

•Low power, 100 Mbps, ABR and simplex modes optionally available.

•VDE 0885-763-1 Q3 - 2012. To be published next month.

11

4 proposals


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The ETSI Standard


Sept 2012

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Standardisation

•ETSI TS 105 175-1-1 Q3-2012: POF application requirements for HN.• ETSI has approved an application requirements document:

• How to use POF in home networking environment.

• Linked to VDE 0885-763-1 and CENELEC 50173-1 and 50173-4: European norm.• Linked to ETSI TS 105 175-1.

• Standardisation done in collaboration with Orange.

•CENELEC was planing to remove POF from the 50173 norm. Thanks to the ETSI effort, POF is still in the normative document, and now linked to ETSI TS 105 175-1 and ETSI TS 105 175-1-1.

13


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Quasar POF Association


Sept 2012

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QUASAR-POF Associations•Objective:

• Promotion of the technology• Marketing• Standardisation

• Laboratory results sharing• Interoperability tests

•Participants• Fibre, Silicon & Optics manufacturers

• Product Manufacturer / Solution Provider

• Telecom Operators

15


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Next Standardisation Steps


Sept 2012

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Standardisation: Next steps•Starting the process of standardisation in IEEE.

• Current supporters: Telefonica, Toyota, Avago & Hamamatsu, and Quasar-Pof Alliance.• CFI is in preparation.• The full standardisation process will take 2 years at least.• Companies like Broadcom, Marvell, Lantiq and Intel has been contacted to obtain their

support.

•Open Alliance.• An Automotive Association for the promotion of Ethernet in the car.• POF and VDE standard is proposed as an alternative to Reduced Twisted Pair.• Now under discussion.

•Jaspar.• Japanese Automotive Association for the Communications in the car.• Presented the standard to JASPAR this summer.• Very positive feedback from Toyota.

17


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Performance


Sept 2012

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Performance• In general: “Same link margin than current 100Fx based solutions”.• Full Duplex real 1Gbps at Ethernet level.• Performance in standard A4a.2 (ESKA GH4002) SI-POF as a function of injected power:

19

0"

200"

400"

600"

800"

1000"

1200"

1400"

1600"

1800"

2000"

0" (1,5" (3" (6" (8"

PHY$rate$(M

bps)$

Transmi3ed$AOP$(dBm)$

Link$speed$vs.$Injected$power$

10m"(3dBo)"

25m"(6dBo)"

50m"(10dBo)"

80m"(14.7dBo)"

100m"(18dBo)"


Sept 2012

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1Gbps Full-Duplex Ethernet for SOHO

20

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

50m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDI

1Gbps1Gbps

min. Input Power @ TP3, Sensitivity

= -20 dBm

max. Output Power @ TP2

= -1.5 dBm

min. Output Power @ TP2

= -7.0 dBm

Worst Case Link Budget 13 dBo @ BER < 10-12

Latency < 25 usMTTFPA > 1040 years

FS = 312.5 MS/sη = 3.3145 bits/SymbPAM-16

Considered manufacturing process deviations in optics and electronics as well as -40ºC to +70ºC temperature range

Automotive industryqualified LED and

optics


Sept 2012

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Performance•Adaptive Bit Rate performance at worst case conditions (-5 dBm AOP).

21

50#

250#

450#

650#

850#

1050#

1250#

1450#

1650#

1850#

0# 20# 40# 60# 80# 100# 120# 140# 160# 180#

Data$ra

te$(M

b/s)$

Link$Length$(m)$

Adap7ve$Bit$Rate$

xGBASE/P#xFBASE/P#Serie3#

Gigabit##performance# Long#reach#

applicaCons#

agregated#traffic#

State#of#the#art#


Sept 2012

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1Gbps FD simplex POF - Std 650nm LED

22

Driver+

LED

PatchCord

SimplexOptical Fibre

Cabling30m POF

MDI

Splitter

Receptacle

Y

MDI

Y

DAC

PGA+

ADC

TXPMA

RXPCS

IL = 4.5 dBo

PTP2 = -6.5 dBmPLED = -2 dBm

BWE-to-E ≥ 70 MHz

IL = 4.5 dBo

PSENS = -21 dBm

TXPCS

xMII

Inte

rface

Driver+

LED

Photodiode+

TIA

Xtalk Att =25 to 50 dBo

Xtalk Cancel > 30dB

RXPMA

EchoCanceller

1 mm polymer optical fiber (POF) splitter

Description:

Assembled from two branches of partially polished standard POF (1mm POF, NA = 0.5) this optical

power splitter component splits up the light of the input POF to two equal portions (50:50 symmetry) in

the output branches. The polished POF parts are coated with a plastic metal combination in order to

increase the cross talk attenuation between the two output branches. The low splitter cross talk is

useful in sensor applications and data transmission systems that use one fiber only for bidirectional,

full duplex operation.

The standard splitter has a 2.2mm diameter input ferrule and two bare fiber output branches (see

figure below).

input POF

output POF 1

output POF 2

With 2.2mm short jacket tubes on the bare fiber output POF the access to standard 2.2 POF cables is

feasible (left photo below). Metal alignment ferrules to connect the output splitter ports to standard

2.2mm POF cable by crimping (middle photo below) and the lock nut adapter to connect and open up

2.2mm POF cables (right photo below) come with each splitter.

Technical Data 50:50 symmetry splitter:

type

splitting ratio (%)

typical

excess loss (dB)

min. typ. max.

cross talk (dB)

typical

standard splitter

50 : 50 (± 10%)

0.9

1.4

2.5

50

Customer specific modifications are feasible:

•

unsymmetric couplers comprising an unsymmetry up to 75:25 splitting ratio,

•

length extension of the output fiber up to 120mm.

2011-04-27

Photodiode+

TIA

Diemount Technology

It is considered ambient temperature and no process degradationEstimations based on measurements provided by Diemount

Typical link budget = 10 dBo ➤ 50m are possible with 1dBo reserve


Sept 2012

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1Gbps FD simplex POF - HighPw 650nm LED

23

Driver+

LED

PatchCord


Cabling50m POF

MDI

Splitter

Receptacle

Y

MDI

Y

DAC

PGA+

ADC

TXPMA

RXPCS

IL = 4.5 dBo

PTP2 = +0.5 dBmPLED = +5 dBm

BWE-to-E ≥ 70 MHz

IL = 4.5 dBo

PSENS = -20 dBm

TXPCS

xMII

Inte

rface

Driver+

LED

Photodiode+

TIA


Xtalk Cancel > 30dB

RXPMA

EchoCanceller


Description:








figure below).

input POF

output POF 1

output POF 2






type

splitting ratio (%)

typical

excess loss (dB)

min. typ. max.

cross talk (dB)

typical

standard splitter

50 : 50 (± 10%)

0.9

1.4

2.5

50


•


•


2011-04-27

Diemount Technology


Typical link budget = 16 dBo ➤ 80m are possible with 3dBo reserve

Photodiode+

TIA


Sept 2012

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1Gbps FD simplex POF - HighPw 470nm LED

24

Driver+

LED

PatchCord


Cabling80m POF

MDI

Splitter

Receptacle

Y

MDI

Y

DAC

PGA+

ADC

TXPMA

RXPCS

IL = 4.5 dBo

PTP2 = +3.5 dBmPLED = +8 dBm

BWE-to-E ≥ 70 MHz

IL = 4.5 dBo

PSENS = -17.5 dBm

TXPCS

xMII

Inte

rface

Driver+

LED

Photodiode+

TIA


Xtalk Cancel > 30dB

RXPMA

EchoCanceller


Description:








figure below).

input POF

output POF 1

output POF 2






type

splitting ratio (%)

typical

excess loss (dB)

min. typ. max.

cross talk (dB)

typical

standard splitter

50 : 50 (± 10%)

0.9

1.4

2.5

50


•


•


2011-04-27

Diemount Technology


Typical link budget = 16.5 dBo ➤ 120m are possible with 3dBo reserve

Photodiode+

TIA


Sept 2012

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F


Automotive - 1Gbps Full-Duplex Ethernet

25

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

15m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDI

1Gbps1Gbps

Ethernet Ethernet

FS = 312.5 MS/sη = 3.3145 bits/SymbPAM-16 Considered

manufacturing process deviations

in optics and electronics as well as

-40ºC to +95ºC temperature range


Sept 2012

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F



25

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

15m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDI

1Gbps1Gbps

Ethernet Ethernet


= -21.5 dBm


= -1.5 dBm


= -7.8 dBm

Link Budget 13.7 dBo @ BER < 10-12







Sept 2012

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25

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

15m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDIC C C C

Very worst-case: Support 4 inline connectors(5.6 dBo POF loss)

1Gbps1Gbps

Ethernet Ethernet


= -21.5 dBm


= -1.5 dBm


= -7.8 dBm








Sept 2012

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F


Automotive - 100 Mbps Full-Duplex Ethernet

26

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

15m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDI

100 Mbps100 Mbps

Ethernet Ethernet






Sept 2012

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F



26

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

15m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDI

100 Mbps100 Mbps

Ethernet Ethernet


= -34.6 dBm


= -1.5 dBm


= -7.8 dBm








Sept 2012

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F



26

Optical PMD

TX/RX

PHYTX/RX

MDI

TP2 TP3

15m duplex SI-POF

PHYTX/RX

Optical PMD

TX/RXMDI

100 Mbps100 Mbps

C C C C

Very worst-case: Support 10 inline connectors(5.6 dBo POF loss)

C C C C C C

Ethernet Ethernet


= -34.6 dBm


= -1.5 dBm


= -7.8 dBm








PO

F


Products


Sept 2012

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KD-PHY1000 - Block diagram

28


POFKnowledge Development for POF S.L.

Ronda de Poniente 12, Bajo-G28760 Tres Cantos, MadridSpain

Phone: +34 918 043 387Fax: +34 918 063 725e-mail: [email protected]://www.kdpof.com


August 2011

The KD-PHY1000 is a fully integrated Gigabit transceiver, optimized for low power and small footprint size. The KD-PHY1000 incorporates the leading edge digital communication technology developed by KDPOF. The KDPOF technology incorporates the most advanced techniques in spectrally efficient coded modulations, adaptive non-linear equalization and adaptive bit-rate, never used before in optical fiber communications. The KDPOF technology is able to reach a performance very close to the Shannon limit, increasing both the bit-rate and the coverage over any large core optical fiber as SI-POF, MC-POF or PCS.The optimal 65 nm CMOS process offers the best performance, lowest cost, and lowest power for Gigabit POF solutions. Further, devices based on the 65 nm process offer an excellent long-term cost curve, enabling better cost reduction over time compared to older technologies.The KD-PHY1000 is designed to fulfill the requirements of the main POF markets: Home Networking, Automotive and Industrial. The KD-PHY1000 is available in small footprint 64-QFN package as well as in bare-die. The last option enables integration of KD-PHY1000 with optoelectronics in a single optical package, reducing the size of the POF port. Further, by using the SerDes interface, the POF port offers the same connectivity that any IEEE 802.3TM 1000base-X device (i.e. 1.25 Gbps with 8b/10b NRZ line code) or 100base-X (i.e. 125 Mbps with 4b/5b NRZI line code).Home and Small Office are two of the key applications for the future POF networking development. The KD-PHY1000 ASIC is the perfect device to integrate Gigabit capabilities in POF ports. Further, the wide range of supported MAC and PHY Ethernet interfaces simplifies the system and board level designs. Examples of products able to incorporate POF ports based on KD-PHY1000 are Set Top Boxes, Routers, Digital TVs, Network

attached Drives, as well as network components like switches, wall plugs and media converters (e.g. POF-to-Copper).Both point-to-point and daisy-chain topologies are possible with KD-PHY1000. The implementation of network nodes, like wall plugs incorporating several POF ports for daisy-chain topology, is highly simplified thanks to the flexible interfaces: MII, GMII, RGMII, SGMII and SerDes MAC. On the other hand, KD-PHY1000 allows backwards compatibility with POF ports based on IEEE 802.3 100base-FX, enabling connectivity in legacy installations.The KD-PHY1000 is also well suited to fulfill the industrial market requirements. The performance provided by KDPOF technology under industrial power budget requirements extends the reach of PROFINET and other field buses from the actual limits up to more than 150 meters, running at 100 Mbps. KD-PHY1000 is suitable for integration in 9x1 and SFP packages, and ensures a smooth backwards compatibility with current equipments and systems.It has been already several years since the automotive industry incorporated POF in cars. With the growing demand for automotive safety, all the leading OEMs and suppliers are heavily investing in ADAS (Automotive Driving Assistance Systems) technologies. Most of the ADAS implementations are based on a sensor (typically a CMOS or CCD image device), an ECU and a display or any other HMI. The link between all these subsystems is very well suited for POF, running at Gigabit speeds and low latency. The KD-PHY1000 is optimized for ADAS applications by integrating parallel video and SPI/I2C control interfaces as well as an advanced multi-protocol multiplexer. KD-PHY1000 can be integrated in an image based sensor without requiring additional micro-controller, encapsulating transparently the video data and the control signals between the sensor and ECU over a single POF link.

Overview

KD-PHY1000 Block Diagram

Inte

rface

Mul

tiple

xer

Encapsulator Binary Scrambler

MLCC Encoder

Symbol Scrambler

TH Precoding

2-PAMMapper

BCHEncoder

Binary Scrambler

Header Builder

Pilot Generator

Fram

e B

uild

er

DAC

100base-FX Encoder

SerDes

PGAConfFilter

ADC

Timing Recovery

Clock Synth

Clock Synth

Non linear Equalizer

TTADSP

Symbol Descrambler

MLCC MSD

Binary Descrambler

Header Decoding

100base-FX Decoder

Adaptive EQ and Bitrate

Decapsulator

R/G/MII

SGMII /SerDes MAC

Video Interface

SPI

I2C

TX OFE

RX OFE

RTBI

AGC

8b/10b Encoding / Decoding


Sept 2012

PO

F


KDPOF Technology - Silicon area comparison

29

VSC9902-01

www.vitesse.com

PRODUCT BRIEF

Single Port 10/100/1000BASE-T Copper PHY 65 nm IP Core

Vitesse2s proven Gigabit PHY technology is available for integration in Ethernet ASIC and ASSP platforms.

Vitesse Semiconductor Corporation, a leading provider of physical layer technology, has deployed over 150 million Gigabit Ethernet PHY ports into various production platforms across the globe.

Now, Vitesse PHY core integration enables systems to achieve lower system Bill of Material (BOM) costs compared to standalone PHY products, making systems less expensive to produce and more cost effective to deploy.

The mixed-signal IP core provides 10/100/1000BASE-T PHY functions and is fully compliant to IEEE 802.3az Energy Efficient Ethernet (EEE) with power dissipation between 160 mW and 400 mW per port, depending on traffic utilization.

Ideal for emerging green applications, the IP core supports Vitesse2s EcoEthernet] 2.0 power saving features including the PerfectReach] intelligent cable length algorithm that saves power based on the reach of a connection, and ActiPHY], which provides power savings of over 75% for ports with no link.

Highlights` GE PHY hard macro for TSMC 65GP

` IEEE 802.3-2008 compliant with IEEE 802.3az energy efficiency

` Lowest BOM solution using only two voltage planes

` Robust EMI and ESD performance

Applications` Commercial temperature support for

electronics, networking, personal computers, printers, and storage

` Extended temperature ranges for automotive, PON ONT/OLT, and industrial applications

AUTO-NEGOTIATION

PCS DECODER

PCS ENCODER

TIMING RECOVERY

+

DAC HYBRID

VGAADCFFE

PMA (DSP Data Pump)PCS MDI (Analog Front End)

4

TX FIR

X4

NC1 NC2 NC3 EC

REF_REXTREF_FILT

XTAL1 / REFCLKXTAL2

OSC_EN / CLKOUT

MAC Output

MAC Input

MACI/F

MDCMDIO

NMDINT NRESET

SERIALMANAGEMENT

INTERFACE

TRELLISDECODER

PAM-5 SYMBOL MAPPER,

SCRAMBLER

PAM-5 SYMBOL DE-MAPPER,

DESCRAMBLER

TXVP_ATXVN_A

TXVP_BTXVN_B

TXVP_CTXVN_C

TXVP_DTXVN_D

PLL,OSCILLATOR

LEDsPLLMODE

BIASINGMII

REGISTERS

LEDINTERFACE

1000BASE-T PHY (UTP)






August 2011



Overview


Inte

rface

Mul

tiple

xer


MLCC Encoder

Symbol Scrambler

TH Precoding

2-PAMMapper

BCHEncoder

Binary Scrambler

Header Builder

Pilot Generator

Fram

e B

uild

er

DAC

100base-FX Encoder

SerDes

PGAConfFilter

ADC

Timing Recovery

Clock Synth

Clock Synth


TTADSP

Symbol Descrambler

MLCC MSD

Binary Descrambler

Header Decoding

100base-FX Decoder


Decapsulator

R/G/MII

SGMII /SerDes MAC

Video Interface

SPI

I2C

TX OFE

RX OFE

RTBI

AGC


KD-PHY1000 (POF)KD-PHY1000

1000BASE-T PHY

PO

F



Sept 2012

PO

F


KDPOF Technology - Silicon area comparison

29

VSC9902-01

www.vitesse.com

PRODUCT BRIEF

Single Port 10/100/1000BASE-T Copper PHY 65 nm IP Core

Vitesse2s proven Gigabit PHY technology is available for integration in Ethernet ASIC and ASSP platforms.

Vitesse Semiconductor Corporation, a leading provider of physical layer technology, has deployed over 150 million Gigabit Ethernet PHY ports into various production platforms across the globe.

Now, Vitesse PHY core integration enables systems to achieve lower system Bill of Material (BOM) costs compared to standalone PHY products, making systems less expensive to produce and more cost effective to deploy.

The mixed-signal IP core provides 10/100/1000BASE-T PHY functions and is fully compliant to IEEE 802.3az Energy Efficient Ethernet (EEE) with power dissipation between 160 mW and 400 mW per port, depending on traffic utilization.

Ideal for emerging green applications, the IP core supports Vitesse2s EcoEthernet] 2.0 power saving features including the PerfectReach] intelligent cable length algorithm that saves power based on the reach of a connection, and ActiPHY], which provides power savings of over 75% for ports with no link.

Highlights` GE PHY hard macro for TSMC 65GP

` IEEE 802.3-2008 compliant with IEEE 802.3az energy efficiency

` Lowest BOM solution using only two voltage planes

` Robust EMI and ESD performance

Applications` Commercial temperature support for

electronics, networking, personal computers, printers, and storage

` Extended temperature ranges for automotive, PON ONT/OLT, and industrial applications

AUTO-NEGOTIATION

PCS DECODER

PCS ENCODER

TIMING RECOVERY

+

DAC HYBRID

VGAADCFFE

PMA (DSP Data Pump)PCS MDI (Analog Front End)

4

TX FIR

X4

NC1 NC2 NC3 EC

REF_REXTREF_FILT

XTAL1 / REFCLKXTAL2

OSC_EN / CLKOUT

MAC Output

MAC Input

MACI/F

MDCMDIO

NMDINT NRESET

SERIALMANAGEMENT

INTERFACE

TRELLISDECODER

PAM-5 SYMBOL MAPPER,

SCRAMBLER

PAM-5 SYMBOL DE-MAPPER,

DESCRAMBLER

TXVP_ATXVN_A

TXVP_BTXVN_B

TXVP_CTXVN_C

TXVP_DTXVN_D

PLL,OSCILLATOR

LEDsPLLMODE

BIASINGMII

REGISTERS

LEDINTERFACE

1000BASE-T PHY (UTP)






August 2011



Overview


Inte

rface

Mul

tiple

xer


MLCC Encoder

Symbol Scrambler

TH Precoding

2-PAMMapper

BCHEncoder

Binary Scrambler

Header Builder

Pilot Generator

Fram

e B

uild

er

DAC

100base-FX Encoder

SerDes

PGAConfFilter

ADC

Timing Recovery

Clock Synth

Clock Synth


TTADSP

Symbol Descrambler

MLCC MSD

Binary Descrambler

Header Decoding

100base-FX Decoder


Decapsulator

R/G/MII

SGMII /SerDes MAC

Video Interface

SPI

I2C

TX OFE

RX OFE

RTBI

AGC


KD-PHY1000 (POF)KD-PHY1000

1000BASE-T PHY

PO

F


70 % area saving


Sept 2012

PO

F


30

KD-‐PHY1001• RGMII interface• Phy and MAC opera6on• 100 FX backward compa6bility• 1000 Base-‐P + 100 Fx Only solu6on.• Commercial temperature grade.• Silicon availability in Q4-‐2012

Silicon Availability: KD-‐PHY1000 family

KD-‐PHY1002• SGMII interface. SFP ready• 100 FX backward compa6bility• 1000 Base-‐P + 100 Base-‐P + 100 Fx• Commercial temperature grade• Silicon availability Q2-‐2013

KD-‐PHY1100• Mul6 port : 2xRGMII interfaces.• 100 FX backward compa6bility• 1000 Base-‐P + 100 Fx Only solu6on.• Commercial temperature grade• Silicon availability Q1-‐2014

KD-‐PHY1001

KD-‐PHY1002

KD-‐PHY1100

POF

POF

POF

RGMII

SGMII

RGMII

RGMII

POF

Comm

ercia

l


Sept 2012

PO

F


31

KD-‐PHY1011• RGMII interface• Phy and MAC opera6on• 100 FX backward compa6bility• 1000 Base-‐P + 100 Base-‐P + 100 Fx• Industrial temperature grade.• Silicon availability in Q4-‐2012

Silicon Availability: KD-‐PHY1000 family

KD-‐PHY1012• SGMII interface. SFP ready• 100 FX backward compa6bility• 1000 Base-‐P + 100 Base-‐P + 100 Fx• Industrial temperature grade.• Silicon availability Q2-‐2013

KD-‐PHY1011

KD-‐PHY1012

POF

POF

RGMII

SGMII

Indus

trial


Sept 2012

PO

F


KD-PHY1001 - Applications

32

Driver

KD-PHY1001

POF

TIA

Optical Front End (OFE)

Gigabit RJ45-POF Media Converter

1000 base-T PHY

RGMII

Tran

sfor

mer

RJ 45

Network node with POF daisy-chain topology support, that offers external HS-BASE-T and WiFi connectivities

KD-PHY1001

POF

KD-PHY1001

POF

RGMII

POF port 1

POF port 2

AntennaMII

RGMII

1000base-T

KD-PHY1001

POF

RGMII

POF port 1

KD-PHY1001

POF

POF port 2

RGMII

KD-PHY1001

POF

POF port 3

RGMII

KD-PHY1001

POF

POF port 4

RGMII

1000base-Tport 1

1000base-Tport 2

1000base-Tport 3

1000base-Tport 4

Switch with POF and HS-BASE-T connectivity

BCM5388

BCM5388

BCM5461

For do-it-yourself kitsand terminal points


Sept 2012

PO

F



33

BCM5388

Gigabit router with POF, 1000base-T and Wifi connectivity

KD-PHY1001

POF

RGMII

POF port 1

AntennasGMII

KD-PHY1001

POF

POF port 2

RGMII

GMII

Access MMFGPON

1000base-Tport 2

1000base-Tport 3

1000base-Tport 4

1000base-Tport 1

GMII

BCM5345M: RGMIIKD-PHY1001

POF

OFERGMII

POF port 1

Gigabit Ethernet Switch

RJ 451000base-Tport

KD-PHY1001

POF

OFERGMII

POF port 2

KD-PHY1001

POF

OFERGMII

POF port 24

High density Gigabit POF Switch

In-home star topology


Sept 2012

PO

F



34

KD-PHY1001

POF


Gigabit RJ45-POF Media Converter

RGMII

Network node with POF daisy-chain topology support, that offers external HS-BASE-T and WiFi connectivities

KD-PHY1001

POF

OFE

KD-PHY1001

POF

OFE


RGMIIRJ 45

WiFi

POF port 1

POF port 2

AntennaMII

RGMIIRJ 45

1000base-T

KD-PHY1001

POF

RGMII

POF port 1

KD-PHY1001

POF

POF port 2

RGMII

KD-PHY1001

POF

POF port 3

RGMII

KD-PHY1001

POF

POF port 4

RGMII

1000base-Tport 1

1000base-Tport 2

1000base-Tport 3

1000base-Tport 4

Switch with POF and 1000-BASE-T connectivity

BCM5388

BCM5388

BCM5461

Full daisy chain solution


Sept 2012

PO

F



35

SGMII

Driver

KD-PHY1002

POF

TIA


SFP

Con

nect

or

Gigabit POF SFP/GBIC Module

Professional solutions for SMEs


Sept 2012

PO

F



36

KD-PHY1002

POF

OFESGMII

POF port 1

SerDesGigabit Ethernet

Switch

RJ 451000base-Tport 1

KD-PHY1002

POF

OFESGMII

POF port 2

KD-PHY1002

POF

OFESGMII

POF port 47

Very High density Gigabit POF Switch for SOHO, simpler PCB

KD-PHY1002

POF

POF port

Satellite/DVBT/DAB

DVBC

AccessSGMII/RTBI

RGMII

Aggregated Trafficis differentiatedby KD-PHY1002

To POF based Daisy-Chain Network,

e.g 1.5 Gbps

e.g. BCM56510: SGMII

Professional solutions for SMEs


Sept 2012

PO

F



37

Low cost daisy chain solution

Network node (e.g. wall plug) with POF daisy-chain topology support, that offers external 1000base-T and WiFi connectivities

KD-PHY1100

POF

OFE

OFE


RGMIIRJ 45

WiFi

POF port 1

POF port 2

AntennaMII

RJ 45

1000base-T

BCM5388


Sept 2012

PO

F



38

Home gateway low cost solutions

Network node (e.g. wall plug) with integrated KD-PHY1000 support of POF daisy-chain topology, that offers external

1000base-T and WiFi connectivities

KD-PHY1005

POF

KD-PHY1005

POF

RGMII

SERDES

POF port 1

POF port 2Antenna

RGMII

KD-PHY1100

POF

OFE

OFE

RGMIIPOF

port 1

POF port 2

SGMIIKD-PHY1002

POF


Gigabit POF SFP/GBIC Module

RGMII

KD-PHY1100

POF

OFE

POF port 3

OFE

POF port 4

GPON ONT/WiFi/

Gigabit Ethernet Router





Antennas

Access MMFGPON

Low cost Gigabit router with POF, 1000base-T and Wifi connectivity

≥ 1 Gbps

BCM5461


PO

F


Thank you for your attention!


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