1
IMPACT OF STRAIN ON MEMORY AND LATERAL POWER MOSFETS
By
UMAMAHESWARI AGHORAM
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2010
2
© Umamaheswari Aghoram
3
To my family
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ACKNOWLEDGMENTS
I would like to express my sincere gratitude to my advisor Dr. Scott E. Thompson
for his guidance and support over the years. I thank my co-chair Dr. Toshikazu Nishida
for his encouragement and helpful discussions. I would also like to thank Dr. Ant Ural
and Dr. Franky So for serving on my committee.
Special thanks go to the industry liaisons from Texas Instruments, Dr Sridhar
Seetharaman, Dr Marie Denison Dr Rick Wise, and Dr Sameer Pendharkar for their
help and guidance on the SRC project. I am grateful to SRC and TI for the opportunity
to work on their project.
My heart-felt thanks to all the current and past members of our research group:
Andy, Amit, Guangyu, Hyunwoo, Jingjing, Ji-Song, Kehuey, Lu, Mehmet, Min, Nidhi,
Sagar, Sri, Tony, Ukjin, Xiaodong, Yongke, Younsung for their assistance, support and
friendship. I would like to thank Saurabh, Daniel and David for helping me with TCAD
simulations. My sincere gratitude goes to Dr. Toshinori Numata for his invaluable help
and mentorship.
Last but not the least; I would like to thank my colleagues at TI, friends, faculty and
staff and everyone who helped me during my graduate studies here at UF. A special
thanks to my good friends Min, Krishna, Manasa, and Saranya for their encouragement
and support.
I dedicate my dissertation to my family for their unwavering love, encouragement,
and support.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS .................................................................................................. 4
LIST OF TABLES ............................................................................................................ 7
LIST OF FIGURES .......................................................................................................... 8
CHAPTER
1. INTRODUCTION .................................................................................................... 13
Strained Silicon Technology ................................................................................... 13
Memory Overview ................................................................................................... 17
Lateral Power MOSFET .......................................................................................... 19
Organization ........................................................................................................... 21
2. EFFECT OF MECHANICAL STRESS ON MEMORY DEVICES ............................ 22
Introduction ............................................................................................................. 22
DRAM Retention ..................................................................................................... 22
Experiment ....................................................................................................... 25
Results and Discussion .................................................................................... 26
Conclusion ........................................................................................................ 30
Flash Memory Retention ......................................................................................... 31
Experiment ....................................................................................................... 31
Results and Discussions .................................................................................. 32
Summary ................................................................................................................ 34
3. EFFECT OF STRAIN ON LATERAL POWER MOSFETS ...................................... 35
Introduction ............................................................................................................. 35
LOCOS vs. STI technology ..................................................................................... 36
Introduction ....................................................................................................... 36
Experimental Approach .................................................................................... 37
Results and Discussion .................................................................................... 38
On-resistance ............................................................................................. 38
Breakdown voltage .................................................................................... 42
Orientation Dependence ......................................................................................... 43
Experiment ....................................................................................................... 45
Results and Discussions .................................................................................. 46
High Stress ............................................................................................................. 54
Device Voltage Rating ............................................................................................ 54
Summary ................................................................................................................ 56
4. STRESS SIMULATION OF STRAINED MEMORY AND LDMOSFET .................... 57
6
Introduction ............................................................................................................. 57
Overview of Simulation tool .................................................................................... 58
Simulation Setup ..................................................................................................... 59
Strain in DRAM Transistor ................................................................................ 60
Strained Flash Memory Device ........................................................................ 61
Strained LDMOSFET ....................................................................................... 62
Nitride capping ........................................................................................... 63
STI induced stress ..................................................................................... 66
Results and Discussion ........................................................................................... 68
Strain in DRAM Transistor ................................................................................ 68
Strained Flash Memory .................................................................................... 69
Strained LDMOS .............................................................................................. 70
Nitride capping with dummy gates ............................................................. 70
STI induced stress ..................................................................................... 72
Summary ................................................................................................................ 76
5. SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK ........................... 78
Summary ................................................................................................................ 78
Recommendations for Future Work ........................................................................ 78
LIST OF REFERENCES ............................................................................................... 80
BIOGRAPHICAL SKETCH ............................................................................................ 86
7
LIST OF TABLES
Table page 1-1. Comparison between DRAM and Flash memory ................................................... 19
3-1. Expected and measured longitudinal coefficients of <110> NLDMOS and DEPMOS ............................................................................................................ 40
3-2. Comparison of carrier mobility and coefficient in logic MOSFET and bulk along different orientations. [8, 9, 46] ................................................................. 45
3-3. Expected and measured coefficients for <100> and <110> N-LDMOS and DEPMOS with the measurement uncertainty in brackets. .................................. 49
4-1. Material Constants used in simulation .................................................................... 60
4-2. Beneficial stress for N-LDMOSFET ........................................................................ 63
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LIST OF FIGURES
Figure page 1-1. Strained silicon technology nodes of Intel nano transistors [5] ............................... 14
1-2. Process induced uniaxial and biaxial stress [6] ...................................................... 14
1-3. Layout of mixed signal integrated chip ................................................................... 15
1-4. Four point wafer bending jig ................................................................................... 16
1-5. Schematic for applying uniaxial and biaxial stress [8] ............................................ 16
1-6. Classification of semiconductor memory ................................................................ 17
1-7. World wide memory market in year 2000 [10] ........................................................ 18
1-8. Evolution of LDMOS from NMOS ........................................................................... 20
1-9. System rating of power devices [15] ...................................................................... 21
2-1. DRAM leakage components .................................................................................. 24
2-2. Band diagram ......................................................................................................... 25
2-3. Typical currents-gate voltage (Vg) characteristics of NMOSFET. .......................... 26
2-4. Setup to measure leakage in MOSFET .................................................................. 26
2-5. Shift in substrate current of n-MOSFET with SiO2 dielectric under the tensile stress. ................................................................................................................. 29
2-6. GIDL shift under mechanical stress for n-MOSFET with SiO2 and high-κ gate dielectric at high (filled marks) and low (open marks) electric fields. .................. 30
2-7. Band diagram of NVM under retention ................................................................... 31
2-8. Experiment setup for data retention bake under stress of NVM cell ....................... 32
2-9 NVM cell retention after baking at 190C for 24h ..................................................... 34
3-1. Cross section of lateral power MOSFET with LOCOS and STI .............................. 37
3-2. Drain current enhancement under low and high gate bias ..................................... 39
3-3. Polar pi plot of n-Bulk under longitudinal tensile stress along <110> direction ....... 41
3-4. Shift in breakdown voltage of N-LDMOS under tensile stress ................................ 43
9
3-5. Mobility enhancement factors for (001)-surface n-MOSFETs under 100-
longitudinal, 110-longitudinal, and biaxial tensile stress [5] ............................ 44
3-6. Channel orientation on (100) wafer ........................................................................ 45
3-7. Linear Drain current enhancement versus stress for NLDMOS ............................. 47
3-8. Linear Drain current enhancement versus stress for DEPMOSFET ...................... 49
3-9. N-bulk piezoresistance vs. angle of spread in drift region under stress ................. 51
3-10. P-Bulk piezoresistance vs. angle of spread in drift region .................................... 52
3-11. On-Resistance distribution of N-LDMOS at rated gate bias ................................. 53
3-12. Linear drain current enhancement under high stress ........................................... 54
3-13. Linear drain current enhancement versus stress with increasing drift region length .................................................................................................................. 55
4-1. Applied Materials scheme for strained NAND Flash. (Courtesy AMAT) ................. 61
4-2. Multi-gate simulation structure with HARP STI and PMD ....................................... 62
4-3. N-LDMOSFET with dummy gates and nitride capping ........................................... 64
4-4. Longitudinal channel stress vs. gate length in logic MOSFET with tensile capping layer [59] ............................................................................................... 65
4-5. 2D capping layer on N-LDMOSFET simulation structure ....................................... 65
4-6. DIELER structure ................................................................................................... 66
4-7. Principle of Dielectric RESURF [60] ....................................................................... 67
4-8. STI induced stress simulation structure for 2-D and 3-D ........................................ 67
4-9. A process simulation of built-in stress in the middle and the gate edge of the channel in a strained Si MOSFET with stressed silicon nitride CESL ................. 68
4-10. Stress in NAND flash memory due to STI and PMD ............................................ 69
4-11. Stress in nested gate structure. A) Expected simulation result of LDMOS with tensile capping layer B) Actual simulation cross section from [60] ..................... 71
4-12. Stress in device center as a function of gate to gate separation. ......................... 72
4-13. STI induced stress in active region [59] ............................................................... 73
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4-14. 2D stress contours of STI induced stress in active drain extension fingers .......... 74
4-15. Transverse compression along the fin ................................................................. 75
4-16. Out of plane tension along the fin ........................................................................ 75
4-17. Longitudinal tension along fin ............................................................................... 76
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
IMPACT OF STRAIN ON MEMORY AND LATERAL POWER MOSFETS
By
Umamaheswari Aghoram
May 2010
Chair: Scott Thompson Cochair: Toshikazu Nishida Major: Electrical and Computer Engineering
To circumvent the limitations of conventional scaling, the semiconductor industry
incorporated strained silicon technology to boost the performance of digital logic
devices. Since strain alters several semiconductor properties, its effect on all device
parameters needs to be investigated. This work focuses on the effect of mechanical
stress on memory and power devices.
Growth of digital electronics is largely attributed to the success of CMOS memory
such as DRAM and Flash. The most significant device characteristic for memory is the
duration of time for which the memory cell is capable of storing the data with integrity or
‘retention time’. Using four-point wafer bending apparatus to apply mechanical stress
the dependence of memory retention time on strain is studied. From measurements it
was observed that while DRAM retention degenerates with mechanical stress, NVM
improved with tensile stress.
Power MOSFETs are used as high current and voltage drivers in automotive,
telecommunication and power industries. The two main figures of merit of power
devices are their on-resistance and breakdown voltage. The design of these devices is
complicated by the tradeoff between the requirements for minimum on-resistance and
12
maximum breakdown voltage. This work focuses on the application of mechanical
stress to improve the performance of Lateral Diffusion MOSFET. The device behavior
was analyzed by measuring and extracting piezoresistance coefficients of these devices
and by monitoring avalanche breakdown with mechanical stress. It was found that the
on-resistance reduced with stress, while breakdown voltage remained a constant thus
making strain a viable performance booster in these devices.
With the understanding of device behavior with strain, the application of stress via
process was simulated with FLOOPS and Sentaurus process. The amount/ type of
stress present in device gives insight into strained device structure and performance.
13
CHAPTER 1 INTRODUCTION
Strained Silicon Technology
The revolutionary growth of the semiconductor industry can be attributed to scaling
of devices. Every two years the chip density has doubled in accordance to Moore’s law
[1]. However improving the performance of transistors by scaling is progressively
becoming difficult and this has spurred the industry to look for other mechanisms to
boost the performance of devices. In early 90’s strained silicon on Si-Ge was
investigated as a means to improve logic performance [2]. In 2003, Intel introduced
strained silicon technology in its 90nm node [3]. Since then fourth generation strained
silicon has been incorporated into the 32nm technology [4]. International Technology
Roadmap for Semiconductors (ITRS’09) named strained silicon as one of the potential
solutions to improve the performance of devices in 22nm node (Figure 1-1). Not only is
strain intentionally introduced to improve performance (Figure 1-2), but strain is
inherently present due to device fabrication process such as isolation, oxidation,
silicidation, implant and packaging. Since strain is known to alter several semiconductor
properties such as: Band structure, carrier mass, scattering and trap properties, it is
important to study its effect on device properties, so that we can engineer strain to
improve the device.
14
Figure 1-1. Strained silicon technology nodes of Intel nano transistors [5]
Figure 1-2. Process induced uniaxial and biaxial stress [6]
The layout of a standard mixed signal integrated chip is shown in Figure 1-3. It
consists of a digital core with semiconductor memory and the interface to the real world
is provided by the surrounding analog shell [7]. The analog shell protects the core from
external electric stresses, provides power management and acts as the communication
link between the control logic circuitry and the load. This technology is gaining more
importance with the increasing interest in System-On-Chip for consumer electronics,
telecommunications, automobile and power management for portable equipments. With
90nm Node2003
65nm Node2005
45nm Node2007
32nm Node2009
22nm Node2011
1st Generation strained Silicon
Strained Silicon?
Fig 4. Technology node for Intel nano-transistors
2nd Generation strained Silicon
3rd Generation strained Silicon 4th Generation
strained Silicon
Uniaxial StressBiaxial Stress
15
the scaling of the digital core to increase functionality there is an increased pressure on
the analog shell to scale as well. Traditionally, scaling in semiconductor industry has
been predominantly digital centric, i.e. focused on logic Metal Oxide Semiconductor
Field Effect Transistors (MOSFET). Scaling of the analog shell lags several years
behind digital logic due to cost considerations and stress from increased power density.
Since the main performance metric for memory and power devices are not similar
to that of logic MOSFETs, the effect of strain on these devices needs to be studied.
Also, it is of interest to see if strain can improve the performance in these devices.
Figure 1-3. Layout of mixed signal integrated chip
Experiment Setup: The four point wafer bending apparatus is used to apply
mechanical stress to device wafer. This apparatus, shown in Figure 1-4, has been
calibrated using wafer curvature and strain gage measurements. Both uniaixal and
biaxial stresses can be applied by using the setup shown in Figure 1-5. The distance of
separation between the rods determines the amount of stress per graduation and can
be calculated using the simple formula (Equation 1-1). The jig is easy and reliable to
Digital Core
Memory
Power Circuitry
Analogue shell
VDD VDD
Inputs
loads
16
use and is especially valuable in taking repeated device measurements under low
stress levels.
𝜎 =
𝐸𝑦𝑡
2𝑎 𝐿2−2𝑎3 (1-1)
Where E-Young’s Modulus, y- vertical displacement, t- wafer thickness, L- distance
between outer two rods, a- Distance between outer rod and inner rod.
Figure 1-4. Four point wafer bending jig
Figure 1-5. Schematic for applying uniaxial and biaxial stress [8]
The device electrical characteristics are monitored using Keithley 4200
semiconductor characterization system. Historically the strain induced change in device
La
y
t
schematic for applying biaxial stressschematic for applying uniaxial stress
longitudinal
transverse
17
drive current is quantized by extracting the piezoresistance coefficient (-coefficient). -
coefficient is defined as the normalized change in resistance per unit applied stress.
000 D
D
I
I
(1-2)
Where -semiconductor piezoresistance -applied mechanical stress, -semiconductor
resistivity, m-carrier mobility, and ID-Drain current
First reported by Smith [9] in 1954, the piezoresistance of silicon has been the basis by
which industry predicts strained device behavior.
Memory Overview
The growth of digital electronics can be largely attributed to the success of
semiconductor memory. It is found in most consumer electronics such as cell phones,
computers, digital cameras, global positioning systems, etc. CMOS memory can be
divided into two main categories: Volatile memory (Random access memory or RAM)
and non volatile memory (NVM) or read only memory (ROM) [10]. Volatile memory
loses the stored information once the power supply is turned off. NVM on the other hand
retains the data. Figure 1-6 shows the various types of semiconductor memory devices.
Figure 1-6. Classification of semiconductor memory
Semiconductor Memory
Volatile
SRAM DRAM
Non Volatile
EEPROM FLASH EPROM ROM
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Figure 1-7. World wide memory market in year 2000 [10]
Dynamic Random Access Memory (DRAM) and Flash memory are billion dollar
industry and are the most popular CMOS memory types (Figure 1-7). Commercially
introduced by Intel in 1971, DRAM consists of one transistor and one capacitor (1T-1C)
[11]. It is a volatile memory that requires the stored information to be refreshed after
every read cycle. It has fast read/write times. With the advent of trench capacitors the
density of DRAM has increased dramatically.
Floating gate flash memory [12] was produced by Toshiba in 1984. It consists of
only one transistor with a polysilicon floating gate acting as the storage element.
Channel hot electron (CHE) injection is used to store electrons in the floating gate, thus
altering the threshold voltage of the device (programmed state). Data is erased by
removing the electrons from the floating gate by Fowler Nordheim tunneling (F-N
tunneling). In 2001, AMD introduced the first commercial Mirror bit flash [13] which was
capable of storing two independent bits of information. The electrons are locally trapped
in two separate locations on the silicon nitride trapping layer. A comparison between
DRAM and Flash memory is shown in Table 1-1.
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Table 1-1. Comparison between DRAM and Flash memory
Lateral Power MOSFET
Power MOSFETs are solid state switches with high power handling capability that
evolved from CMOS technology. The process of increasing the blocking voltage
capability of lateral MOSFET structure led to the development of Diffusion MOSFET
(DMOS) [14]. In NLDMOS structure the source and drain n+ regions are self aligned
with the poly gate.” The p-base region is then driven in deeper than the source [15].
This is called ‘Double-diffusion process’. The difference in lateral diffusion determines
the channel length of the device”. Thus, these devices have very small channel lengths
and hence low on-resistance. These devices have an n-type drift region which
increases the breakdown voltage. Also the presence of field plate and RESURF [16]
reduces the electric field at the surface. Figure 1-8 shows the evolution of LDMOS from
NMOSFET.
DRAM Floating Gate FLASH Mirroe Bit FLASH
Structure
Bits of information 1 Bit 1 Bit 2 Bits
Cell Area (6-8)F2 (2-4)F2 (2-4)F2
Read Destructive Non-Destructive Non-Destructive
Read/Erase/Program speed ns s-ms/ms/ns s-ms/ms/ns
Program Cap charging CHE CHE
Erase Cap Discharging F-N tunneling BTB hot hole tunneling
Relative Cost/Bit Low Medium Medium
Scaling Challenge Capacitor Tunnel oxide, High Voltage
Tunnel oxide, High Voltage
DRAM Floating Gate FLASH Mirror Bit FLASH
Structure
Bits of information 1 bit 1 bit 2 independent bits
Cell Area (6-8) F2 (2-4)F2 (2-4)F2
VolatileYes
Refresh neededNo
(10 yrs retention)No
(10 yrs retention)
program Cap charging CHE CHE
Erase Cap Discharging F-N tunneling BTB hot hole tunneling
Scaling Challenge Capacitor Voltage, retention LCH, Voltage, retention
Bit
Lin
e
Word Line
Capacitorp-Si
Floating Gate
Control Gate
Blocking Oxide
Tunneling Oxiden+n+
p-Si
Trap layer
Control Gate
Blocking Oxide
Tunneling oxide
0 1
n+n+
p-Si
Floating Gate
Control Gate
Blocking Oxide
Tunneling Oxiden+n+
p-Si
Trap layer
Control Gate
Blocking Oxide
Tunneling oxide
0 1
n+n+
DRAM Floating Gate FLASH Mirror Bit FLASH
Structure
Bits of information 1 bit 1 bit 2 independent bits
Cell Area (6-8) F2 (2-4)F2 (2-4)F2
VolatileYes
Refresh neededNo
(10 yrs retention)No
(10 yrs retention)
program Cap charging CHE CHE
Erase Cap Discharging F-N tunneling BTB hot hole tunneling
Scaling Challenge Capacitor Voltage, retention LCH, Voltage, retention
Bit
Lin
e
Word Line
Capacitorp-Si
Floating Gate
Control Gate
Blocking Oxide
Tunneling Oxiden+n+
p-Si
Trap layer
Control Gate
Blocking Oxide
Tunneling oxide
0 1
n+n+
p-Si
Floating Gate
Control Gate
Blocking Oxide
Tunneling Oxiden+n+
p-Si
Trap layer
Control Gate
Blocking Oxide
Tunneling oxide
0 1
n+n+
DRAM Floating Gate FLASH Mirror Bit FLASH
Structure
Bits of information 1 bit 1 bit 2 independent bits
Cell Area (6-8) F2 (2-4)F2 (2-4)F2
VolatileYes
Refresh neededNo
(10 yrs retention)No
(10 yrs retention)
program Cap charging CHE CHE
Erase Cap Discharging F-N tunneling BTB hot hole tunneling
Scaling Challenge Capacitor Voltage, retention LCH, Voltage, retention
Bit
Lin
e
Word Line
Capacitorp-Si
Floating Gate
Control Gate
Blocking Oxide
Tunneling Oxiden+n+
p-Si
Trap layer
Control Gate
Blocking Oxide
Tunneling oxide
0 1
n+n+
p-Si
Floating Gate
Control Gate
Blocking Oxide
Tunneling Oxiden+n+
p-Si
Trap layer
Control Gate
Blocking Oxide
Tunneling oxide
0 1
n+n+
20
Figure 1-8. Evolution of LDMOS from NMOS
Figure 1-9 shows the system rating of power devices. The lateral power MOSFET
has high input impedance, operation frequency, current and voltage handling capability
and ease of integration. They find wide application in automotive, telecommunication
and power industries.
p-Si
Gate
n+n+
Low Voltage logic NMOS logic LDD NMOS
p-Si
Gate
n+ n+n-
DENMOS
p-Si
Gate
n+ n+n
p-Si
Gate
n+
n-regionn+
p-Si
Gate
n+
n-region
n+LOCOS
p-body p-body
p-Si
Gate
n+
n-region
n+
p-body
STI
N-LDMOSN-LDMOS (LOCOS)N-LDMOS (STI)
21
Figure 1-9. System rating of power devices [15]
Organization
The effect of mechanical stress on memory retention and power MOSFET device
characteristics is presented in this work. Chapter 2 discusses the change in GIDL
leakage current with mechanical stress and its effect on DRAM retention. Chapter 3
reports the piezoresistance coefficient of n-LDMOS and DEPMOS devices. The
experimental result of strain induced change in breakdown voltage is also shown.
Chapter 4 deals with simulation of strained memory and power MOSFET structures.
Summary and recommendations for future work are provided in chapter 5.
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CHAPTER 2 EFFECT OF MECHANICAL STRESS ON MEMORY DEVICES
Introduction
Mechanical stress alters several properties of semiconductors such as band
structure, carrier mass, scattering and trap properties. Thus several characteristics of
memory devices may be altered by strain. The most important properties in memory
devices are [17]:
Endurance: Read/Write cycles the device can endure before failure
Data Retention: The value of time for which a memory cell retains data
Memory Disturb: Loss or gain of charge in a memory cell
Program/Erase time: Time required for programming/erasing memory cell
Among all these properties, retention time is the most important parameter. The
industry generally requires Non Volatile Memory (NVM) to have 10 years retention time.
In order to predict the memory retention time, accelerated testing methods such as Data
Retention Bake (DRB) is used. In DRB programmed memory devices are baked at high
temperatures such as 250C for 24-48 hours. The difference in device characteristics
before and after bake, determines the retention.
DRAM Retention
Scaling of memory devices is ultimately determined by the data retention capability
of the designed memory cell. In DRAM, leakage occurs from the capacitor through the
MOSFET during retention period. The main leakage mechanisms in DRAM (Figure 2-1)
are
Subthreshold leakage (ISUBVt): This leakage refers to the flow of charge
carriers from source to drain even when the device is in the off condition.
23
This leakage current is especially large in short channel MOSFETs due to
the Drain induced barrier lowering (DIBL).
Gate induced drain leakage, GIDL (IGIDL): This leakage refers to band to
band leakage between the reversed biased gated diode of drain-substrate
region. For instance in an NMOSFET, high positive bias on the drain results
in the drain- substrate junction being reverse biased. However when there
is a negative bias on gate resulting in an accumulation region in the
channel, the depletion region width of the reverse bias diode reduces at the
surface below the gate. This causes an increased electric field and a
subsequent increase in band to band tunneling current (Figure 2-2A).
Junction leakage (IJXN): This merely refers to the reverse biased junction
leakage of the drain-substrate diode.
With the scaling of the transistor in DRAM, the increase in subthreshold leakage is
countered by applying a negative gate bias during retention. This has resulted in the
increase of GIDL leakage. Thus GIDL current has become the most dominant leakage
mechanism in DRAM.
24
Figure 2-1. DRAM leakage components
GIDL current is dominated by band-to-band tunneling (BTBT) leakage current at
high normal electric fields and by interface-trap-assisted tunneling (TAT) leakage
current at low electric fields [18-20]. Mechanical stress in DRAM may be present due to
the technology node or as a result of processing and packaging. Several studies have
been conducted on the effect of Shallow Trench Isolation (STI) and process induced
strain on GIDL [21-23] in MOSFETs with oxide and high- dielectrics. They report an
increase in GIDL current under compressive stress due to band-gap narrowing and
increase in intrinsic carrier density. The reduction in silicon band-gap due to strain
induced band splitting is reported in reference [24]. Since band-to-band tunneling is
exponentially dependent on bandgap (EG), mechanical stress can be very detrimental to
DRAM retention.
23
2/1exp
1g
g
bb AEE
J (2-1)
Where Jb-b-Band-to-band tunneling leakage current, Eg-Band gap and A-Constant
ISUBVt
IGIDL IJXN
n+ n+
BLWL
insulator
Po
ly S
i
p-Si
GND
ISUBVt
IGIDL IJXN
n+ n+
BLWL
insulator
Po
ly S
i
p-Si
GND
25
A B
Figure 2-2. Band diagram A) GIDL B) Strain induced Si band-gap narrowing
Experiment
The devices used in this study were Silicon (Si) n-channel MOSFETs with oxide
(SiO2) and high- gate dielectrics on (001) wafer. The SiO2 gate dielectric MOSFETs
had n+ poly Si gate and 1.4-nm SiO2 gate dielectrics. The high- gate devices were
formed with 10-nm Titanium Nitride (TiN) gate and 2-nm Hafnium silicate (HfSiO) gate
dielectric. The oxide interfacial layers were created by the gate stack formation. The
MOSFETs with compressive built-in stress were also formed by the process modulated
silicon nitride contact etch stop layers (CESL).
The typical currents and gate voltage (Vg) characteristic of a long channel n-
MOSFET is shown in Figure 2-3. In thin gate dielectric devices, the minimum drain
current is dominated by the gate leakage. Thus to monitor GIDL, the substrate current
(Isub) was measured. Figure 2-4 shows the measurement setup used to distinguish
between the various Isub components. Isub is composed of the GIDL current at negative
Vg and the impact ionization current at positive Vg, both of which were higher than the
corresponding p-n junction leakage between drain and substrate.
unstrained
Tensile stress (compressive)
6
4 (2)
2 (4)
VBHH (LH)
LH (HH)
Eg(0) Eg()
26
Tensile and compressive mechanical stresses were applied longitudinally along
the <110>-channel by using the four-point bending jig.
Figure 2-3. Typical currents-gate voltage (Vg) characteristics of NMOSFET.
Figure 2-4. Setup to measure leakage in MOSFET
Results and Discussion
Figure 2-5 shows the Isub - Vg and the shift in Isub for tensile stress of 150MPa on
long channel MOSFET with the SiO2 gate dielectric with zero built-in stress. On the
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
-0.2 0 0.2 0.4 0.6 0.8
Cu
rren
t, I [
A]
Gate voltage, Vg [V]
ISUB_PN
ID
ISUB_GIDL
ISUB
IG
ISUB_I/I
VD = 1.2 V
10-6
10-9
10-12
Junction leakage
Impact Ionization
GIDL
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
-0.2 0 0.2 0.4 0.6 0.8
Cu
rren
t, I [
A]
Gate voltage, Vg [V]
ISUB_PN
ID
ISUB_GIDL
ISUB
IG
ISUB_I/I
VD = 1.2 V
10-6
10-9
10-12
Junction leakage
Impact Ionization
GIDLGIDL
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
-0.2 0 0.2 0.4 0.6 0.8
Cu
rren
t, I [
A]
Gate voltage, Vg [V]
ISUB_PN
ID
ISUB_GIDL
ISUB
IG
ISUB_I/I
VD = 1.2 V
10-6
10-9
10-12
Junction leakage
Impact Ionization
GIDL
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
-0.2 0 0.2 0.4 0.6 0.8
Cu
rren
t, I [
A]
Gate voltage, Vg [V]
ISUB_PN
ID
ISUB_GIDL
ISUB
IG
ISUB_I/I
VD = 1.2 V
10-6
10-9
10-12
Junction leakage
Impact Ionization
GIDLGIDL
pn Junction
leakage
VD
A
IG
ISUB_PN
GIDL
Impact ionization
pn Junction leakage
VG
VD
A
IG
ID
ISUB_P-N
ISUB_GIDLISUB_I/I
GIDL
pn Junction
leakage
VG
VD
A
IG
ISUB_GIDL
ISUB_P-N
27
application of tensile stress, the Isub shift shows a constant enhancement at high
negative gate voltages. On the other hand at low Vg, Isub decreases. It is thus found that
the GIDL current increases in the high electric field and decreases in the low electric
field for the tensile stress. In the impact ionization region (high positive Vg), Isub shows a
constant enhancement. Figure 2-6 shows the GIDL current shift with stress at high and
low electric fields. It is seen that at high electric field, GIDL current increase for both
tensile and compressive stresses. In this electric field region, GIDL current is generally
dominated by BTBT, which is sensitive to the variation in band gap. The Si band gap
decreases for both tensile and compressive stress, although the sub-bands shifts for 2
and 4 valleys and heavy and light holes are opposite for the tensile and compressive
stresses [6]. On the other hand, the GIDL current in low electric field is due to trap-
assisted generation of electron hole pairs, which can be described by using Shockley-
Read-Hall model [20]. It is reported that the intrinsic carrier density is the main stress-
dependant parameter in the bulk generation-recombination current in p-n junction [25].
A theoretical calculation shows that, for the wafer orientation and stress range
considered in this paper, the intrinsic carrier density decreases with tensile and
increases with compressive stress [26, 27]. This is similar to the strain-altered GIDL
shifts observed at low electric field. However, for a more accurate analysis several other
stress-altered parameters such as the surface current, trap energy and new generation-
recombination centers need to be considered.
Figure 2-6 shows the relative change in GIDL current of high- gate devices under
applied stress. This trend was observed in the entire range of electric field up to the
break down gate voltage. In zero-built-in stress device, the GIDL current increases with
28
an increase in the compressive stress and gently decreases with tensile stress. These
trends are similar but larger than those obtained at low electric fields in the SiO2 gate
dielectric devices.
In high- gate dielectric devices, an additional GIDL component is introduced by
trap-assisted tunneling from the remote traps located at the interface of the high-
dielectric and oxide in the gate stack [28]. The larger change in GIDL current measured
in these devices seems to suggest that the change in trap energy with strain further
enhances the shift in generation-recombination current.
Figure 2-6 also shows the tensile strain altered GIDL current shift of devices with
compressive built-in stress. The slope of curve changes beyond a certain stress value
(flex point). The rate of the GIDL current shift beyond the flex point is identical to that of
the device with zero built in stress. The flex points of the process-stressed devices
changes with gate length. This type of trend strongly suggests that the channel region,
where GIDL current is generated, has a non zero-built-in stress modulated by externally
applied mechanical stress. Therefore the stress value corresponding to the flex points
give an estimate of the original built-in stress in the channel near the gate edge where
the GIDL current is generated. These flex points also shows that the built-in stress still
remains in the long channel devices with stressed CESL.
29
Figure 2-5. Shift in substrate current of n-MOSFET with SiO2 dielectric under the tensile stress.
0.E+00
5.E-10
1.E-09
2.E-09
2.E-09
3.E-09
-12
-8
-4
0
4
8
-0.4 -0.2 0 0.2 0.4 0.6
Isu
b [
nA
]
Isu
b s
hif
t,
Isu
b [
%]
Gate voltage, Vg [V]
1
0
2
Isub
Isub
150 MPa tensile stress
30
Figure 2-6. GIDL shift under mechanical stress for n-MOSFET with SiO2 and high-κ gate dielectric at high (filled marks) and low (open marks) electric fields.
Conclusion
The GIDL current dominated by BTBT leakage in high electric field increases for
both tensile and compressive stress and the stressed enhancement of Si MOSFETs is
about 2-3 % per 100MPa in this measurement. Even for strained long channel devices,
the stress in the gate – drain overlap region is not negligible. This has a serious impact
on DRAM retention and off-state leakage of devices using narrow band gap materials
[24, 29]. In n-MOSFETs with high- dielectric, compressive stress reduces GIDL. Thus
strain on DRAM memory with high- MOSFETs shows potential in increasing retention
time.
-25
-20
-15
-10
-5
0
5
-200 -100 0 100 200 300 400
GID
L c
urr
en
t sh
ifts
[%
]
Stress [MPa]
Zero-built-in stress
compressive
built-in stress Lg=0.1m
Lg=0.5m
SiO2
High
31
Flash Memory Retention
Mirror bit Flash or SONOS (silicon-oxide-nitride-oxide-silicon) memory consists of
a trapping nitride layer, instead of the floating gate as the charge storage layer. In
retention mode electrons trapped in the nitride layer leaks back into the silicon substrate
through several mechanisms illustrated in Figure 2-7 [30]. Retention in these devices is
monitored by data retention bake followed by measuring the shift in threshold voltage.
At high temperature and in the absence of external electric field, thermal emission
followed by drift of electrons due to the internal field is the main leakage mechanism
[31].
Figure 2-7. Band diagram of NVM under retention
Experiment
A long strip of device wafer is cleaved and all the isolated devices are
programmed by applying high gate and drain bias for a few microseconds at room
Thermal excitation_
Electron drift
Nitride trap layerOxideSilicon
ET_
Trap to bandtunneling
_
Band to trap tunneling
ET
+trap to trap tunneling
32
temperature. Under these bias conditions, channel hot electrons are captured into the
nitride layer. This results in a shift in threshold voltage (VT) of the Flash cell. Next,
mechanical stress is applied on devices on one die of the sample by using four-point
bending jig. The sample along with the jig is then baked at 190 C for 24 hours. The
advantage of this experiment setup is that both stressed and unstressed samples are
baked at simultaneously. The VT before and after baking is monitored since the delta in
VT is directly proportional to the loss of electrons from the trapping layer.
Figure 2-8. Experiment setup for data retention bake under stress of NVM cell
Results and Discussions
Shift in threshold voltage before and after the baking for stressed and unstressed
devices is shown in Figure 2-9. As can be seen from Figure 2-9a, even for small values
of stress as those applied in this experiment, all devices under tensile stress show
improved retention (smaller VT shift) than unstressed devices. On the other hand
compressive stress is observed to deteriorate retention (Figure 2-9b).
The leakage current density due to thermal emission is given by equation similar
to Arrhenius relationship. The shift in threshold voltage is proportional to the integral of
33
current density over time. Thus the threshold voltage shift is exponentially proportional
to the inverse of trap activation energy.
Tk
E
Tb
TA
eATJV 2
(2-2)
From the threshold voltage shift data of device with W/L=0.16/1 at two different
temperatures at zero stress, we extracted the trap activation energy to be 1.54eV. This
value lies within the range reported in literature for electron traps in nitride layer [30].
This gives us confidence that thermal emission is in fact the dominant leakage
mechanism.
eVE
e
eT
T
TV
TV
TA
E
TTk
E
T
T
TA
b
TA
54.1
459
463
132
188
)(
)(
459
1
463
1
10615.8
2
2
112
2
2
1
2
1
5
21
(2-3)
Strain is known to alter trap activation energy (ETA) [32]. From the relationship
between VT shift and activation energy of traps, an increase in ETA under tensile stress
and a decrease in ETA of nitride traps under compressive stress may explain the
observed trend.
34
A
B
Figure 2-9 NVM cell retention after baking at 190C for 24h. A) Under Tensile stress and B) Under Compressive stress [33]
Summary
Effect of mechanical stress on retention time of DRAM and flash memory was
investigated. Stress deteriorated DRAM retention while tensile stress improved charge
trapping memory. Careful consideration needs to be given to process induced stress
while manufacturing memory devices to maintain device reliability.
35
CHAPTER 3 EFFECT OF STRAIN ON LATERAL POWER MOSFETS
Introduction
In 1970’s power MOSFETs replaced power Bipolar MOSFETs for high speed,
medium power applications. Their high input impedance, operating frequency and
excellent safe operating area make them ideal candidates for power, automotive and
telecommunications industry. These devices form the analogue shell that surrounds the
digital core and provides the link between the IC and real world. The main requirement
in these devices is high drive current and ability to withstand large voltages. Since the
total current and power dissipation in these devices is limited by the on-resistance and
the maximum voltage rating by the breakdown voltage, minimizing on-resistance and
maximizing breakdown voltage is the key to designing a high performance power
MOSFET. However the conflicting requirements needed to satisfy both these conditions
complicates the design of these devices. Hence scaling of these devices lags behind
the current CMOS technology.
Despite having lower power rating than vertical power MOSFETs, lateral power
MOSFETs are widely used because of their ease of integration. Following the
conventional way of reducing on-resistance by reducing dimensions has resulted in the
need for innovative techniques such as REduced SURface Field (RESURF) [16, 34],
field plating [15], and Superjunctions [35] to improve device breakdown.
Strained silicon technology is a novel technique that can enhance power MOSFET
performance by reducing the on-resistance (RON) without affecting the breakdown
voltage. Kondo et al [36] investigated biaxially stressed lateral double diffused
MOSFETs (LDMOSFETs) formed on strained silicon grown over relaxed Si0.85-Ge0.15
36
layer. 16-21% lower on resistance of was reported. Recently, Moens et al [37] reported
a strained trench power MOSFET. Tensile stress of the order of 200MPa was produced
in the drift region by trench oxide on either side. MicroRamanSpectroscopy was used to
verify the stress magnitude and direction. Strain induced mobility enhancement
reduced the on-resistance in the device by 10%. However no report on the effect of
industry preferred uniaxial stress on power MOSFET performance has been made till
date.
This chapter deals with the effect of strain on n and p type LDMOSFETs,
investigating the dependence on type of device isolation, voltage rating, channel
orientation, and high mechanical stress. A simple analytical model using channel and
bulk pi coefficients is used to explain the 4-point probe bending data. Based on the
experimental result conclusions regarding the best option for strain enhanced
LDMOSFET is reached.
LOCOS vs. STI technology
Introduction
The presence of isolation oxide in drift region reduces electric field and thus plays
a critical role in improving the breakdown voltage in power MOSFET devices. In older
analog technologies, LOCal Oxidation of Silicon (LOCOS) was used. Current
technologies use the Shallow Trench Isolation process for isolation. The cross-sections
of the devices using LOCOS and STI isolations are illustrated in Figure 3-1. The effect
of strain on the isolation technology is studied by monitoring its effect on On-resistance
and breakdown voltage of the device.
37
Experimental Approach
<110>-oriented N-LDMOS and DEPMOS on (100) substrate (Figure 3-1) with
shallow trench isolation and LOCal Oxidation of Silicon isolation were used in this study.
External mechanical stress was applied using four point wafer bending apparatus and
the I-V characterization was done using the Keithley 4200 SCS.
Linear device characteristics were measured by applying a constant DC bias of
0.1V at the drain and sweeping the gate bias from 0 to rated gate bias, while keeping
source and substrate grounded.
Breakdown characteristics were obtained by sweeping the drain bias till
avalanche breakdown occurred and the drain current was 10nA, while maintaining the
gate, source and substrate at 0V. In case of STI isolated devices, measuring the
breakdown voltage is complicated by the excessive charging of the STI oxide.
A
B
Figure 3-1. Cross section of lateral power MOSFET with LOCOS and STI. A) N-LDMOS and B) DEPMOS
Gate
Drain
POLYFOX N+
N-WELL
P-SUBSTRATE
Source
P-BODY
N+P+
POLY
Gate
Source Drain
P-BODY
STIN+
N-WELL
P-SUBSTRATE
POLY
N+P+
DrainBack Gate
p+
P-WELL
POLY1
n+
N-WELL
NBL
p+
Source
FOX
Drain
Gate
Back Gate
p+
P-WELL
POLY1
n+
N-WELL
NBL
p+ STI
Source
38
Results and Discussion
On-resistance
The percentage gain in linear drain current (IDLIN) with longitudinal tensile stress
on N-LDMOSFET with STI and LOCOS isolation at low and high gate bias (VG) is
shown in Figure 3-2a and Figure 3-2b shows a similar plot for DEPMOSFET. At low VG,
the piezoresistance coefficient (- coefficient) of LDMOS with STI and LOCOS is similar
to logic MOSFET (NLDMOS=-25 and NMOS=-31; DEPMOS=55 and PMOS=71). As VG
increases, the gain in IDLIN of N-LDMOS decreases. Also at high VG, the gain in IDLIN was
higher in LOCOS device (1.2% for 100 MPa) than STI device (0.9% per 100 MPa). No
VG or device isolation dependence was observed in the DEPMOS devices.
A
Figure 3-2. Drain current enhancement under low and high gate bias. A) NLDMOS B) DEPMOS
39
B
Figure 3-2. Continued
The above results can be understood by examining the effect of strain on the
individual components of RON of the power MOSFET. The -coefficient of a laterally
diffused power MOSFET is estimated based on its device model which consists of an
enhancement mode MOSFET in series with a resistor [38-40]. At low VG (weak
inversion), the channel resistance (RCH) dominates the on-resistance (RON) and is given
by
)(2 tGDnox
eff
CHVVWC
LR
(3-1)
Where, Leff - effective channel length, W- channel width, Cox- gate capacitance/unit
area, μn2-D- electron inversion layer mobility, VG- applied gate bias, and VT- Threshold
voltage of enhancement mode MOSFET. Thus the -coefficient of the power device is
predicted to be similar to the logic MOSFET. At high VG, RON is dominated by the drift
resistance (RD).
0
4
8
12
0 50 100 150
I DL
ING
ain
(%
)
Longitudinal Compressive stress (MPa)
STI
90nm Logic
PMOS
LOCOS
0
4
8
12
0 50 100 150
I DL
ING
ain
(%
)Longitudinal Compressive stress (MPa)
Smith
STI
LOCOS
Vg-Vt=0.3V Vg=Rated Voltage
40
WQq
LR
dnBulk
DD
(3-2)
Where, LD-drift region length, μn-Bulk- bulk electron mobility, W- channel width, and Qd-
drift region charge. Hence, the -coefficient is expected to be identical to bulk silicon
(Si) -coefficient. Based on this concept, the expected values for the -coefficient of
power MOSFET are listed in Table 3-1. The values for the logic MOSFET were taken
from [8] and Smith’s values were used for bulk [9].
From table 3-1 it can be observed that at low VG, the strained lateral power
device follows expectation. However at high VG the values of the N-LDMOS differs
significantly from bulk Si. On the other hand no such degradation of enhancement is
observed in DEPMOSFETs. This discrepancy can be understood by considering the
strain induced change in mobility of carriers that spread vertically into the drift region.
Table 3-1. Expected and measured longitudinal coefficients of <110> NLDMOS and DEPMOS
Longitudinal (x10-11Pa-1)
LOCOS STI
Low VG High VG Low VG High VG
NLDMOS -24 -12 -25 -9
Expectation -31 -31 -31 -31
DEPMOS 55 50 52 42
Expectation 71 71 71 71
For the LDMOSFET, RON is the sum of channel resistance (RCH), accumulation
resistance (RACC), spread resistance (RS), and drift resistance (RD) [41]. The -
coefficient of RCH is the same as logic MOSFET and the value of RD and RS is that of
41
of N-Bulk along that direction. The -coefficient of RS (S) is a function of the angle of
spread of carriers into the bulk of the drift region. For materials with cubic symmetry
such as Si, the -coefficient along any direction can be determined from the
piezoresistance tensor and direction cosines [42, 43]. The dependence of S on spread
angle for <110> n-channel device under longitudinal tensile stress shown in Figure 3-3
is derived as
212
2
4412112
SinCos
s (3-3)
Where 11, 12 and 44 are the three basic -coefficients, and represents the spread
angle.
Figure 3-3. Polar pi plot of n-Bulk under longitudinal tensile stress along <110> direction
Channel direction
Substrate
gate
DS
stress
N-well
0 10 20 30 40 50 60 70 800
10
20
30
40
50
60
70
80
-Coefficient
-C
oeff
icie
nt
10º
20º
30º
40º
50º
60º
70º80º90º
positive
0 10 20 30 605040 70 800
10
20
30
40
50
60
70
80
0 10 20 30 40 50 600
10
20
30
40
50
60
Coefficient
C
oeff
icie
nt
10º
20º
30º
40º
50º
60º
70º80º90º
positive
negative
0 10 20 30 6050400
10
20
30
40
50
60
<110>
<100>
42
From the polar plot for N-Bulk (Figure 3-3), it is easy to see that as electrons
spread more vertically into the substrate, the spread resistance increases with the
applied mechanical stress. At high VG where RD and RS dominate RON, the increase in
RS with stress results in the observed degradation of the coefficient of N-LDMOS.
In the case of low breakdown DEPMOS devices, there is no isolation present in
the drift region. However, even in the presence of isolation, the insignificant
coefficient of the spreading resistance results in DEPMOS IDLIN enhancement to be
independent of VG.
Breakdown voltage
From Figure 3-4 it is seen that the shift in breakdown voltage for lateral power
MOSFETs is only ~80 mV for 60 MPa, comparable to the amount of shift caused by
charging of the oxide from repeated measurements. Assuming a linear trend with
stress, this translates to ~1 V for 1 GPa stress. This shift is rather insignificant when
dealing with breakdown voltages of magnitude ~35 V.
43
Figure 3-4. Shift in breakdown voltage of N-LDMOS under tensile stress
From the measurement of piezoresistance coefficients of <110>-lateral power
devices, it is observed that the coefficients of power devices are not similar to logic
MOSFETs. This is due to the vertical spread of carriers in the drift region. The
enhancement for N-LDMOS device is not as high as expected. For 20% reduction in
RON the required amount of stress exceeds 1.5 GPa. This large value of stress makes
application of strained silicon technology not a very attractive option for <110>
NLDMOS devices.
Orientation dependence
Work from Kanda [36] reports that strain induced enhancement in a
semiconductor is dependent on the direction of current flow. For n-type logic devices,
determination of the best strained orientation was conducted by Uchida. From his plot
on mobility enhancement with stress, it is easy to see that <100> is the best orientation
for NMOSFET at low values of stress and <110> is the best orientation at high stresses.
1E-10
1E-09
1E-08
1E-07
1E-06
36 36.4 36.8 37.2 37.6 38
10-6
10-7
10-8
10-9
10-10
VBD~80mV
VBD at ID=10nA
VD (V)
I D(A
)0MPa
60MPa
44
However from the previous discussion, it is easy to see that <110> is not the best
orientation for strained N-LDMOSFET.
Figure 3-5. Mobility enhancement factors for (001)-surface n-MOSFETs under 100-
longitudinal, 110-longitudinal, and biaxial tensile stress [5]
Use of alternate orientations and hybrid wafer substrates in the manufacture of
power MOSFETs has been widely investigated especially for p-type power devices[44,
45]. From the comparison of hole mobility for different substrate and channel
orientations (Table 3-2), <110> direction on (110) substrate is the ideal orientation for p-
type power MOSFETs.
The piezoresistance of strained power LDMOSFET is a function of both MOSFET
and bulk value. A comparison of carrier mobility and coefficient of MOSFET and
bulk silicon along different orientations (Table 3-2) is useful in determining the best
orientation for strained lateral power MOSFET.
<110> Biaixial
<100> Uniaxial
<110> Uniaxial
<110> Biaixial
<100> Uniaxial
<110> Uniaxial
45
Table 3-2. Comparison of carrier mobility and coefficient in logic MOSFET and bulk along different orientations. [8, 9, 46]
Wafer/Channel Orientation
Channel Mobility Channel coefficient
Bulk coefficient
n p n p n P
(100) [110] n p -32 71 -31 71.8
(100) [100] ~n 108p -47 15 102 -6.6
(110) [110] 0.4n 2.6p -17 27 -31 71.8
(110) [110] 0.6n 1.7p -24 31.3 102 -6.6
From this table it is easy to see that <100> channel and <110> channel on (100)
wafer is the best orientation for strained N-LDMOSFET and DEPMOSFET respectively.
By simply rotating the wafer notch by 45 degrees, the same processing for the devices
with standard orientation will yield devices with channel along the <100> direction
(Figure 3-6). This enables the simultaneous production of both n- and p-type strained
power MOSFETs on the same wafer.
Figure 3-6. Channel orientation on (100) wafer
Experiment
The current-voltage characteristics of <100>-oriented N-LDMOSFET and
DEPMOSFET with STI on (100) wafer under mechanical stress was measured and
45o
1][01[100]
[010]
46
compared with the control <110>-oriented device. -coefficients were extracted at low
and high gate bias. coefficients of on-chip resistances were also measured to
accurately determine bulk values. From the measurement, an analytical model for the
piezoresistance of lateral power MOSFET was developed and the lowest value of stress
required for 20% reduction in on-resistance was calculated.
Results and Discussions
The linear drain current enhancement with applied mechanical stress for <100>
and <110> oriented n-type lateral power MOSFETs is shown in Figure 3-7 and the
extracted -coefficients is listed in Table 3-3. Both <110> and <100> channel device
showed lower enhancements of IDLIN at high VG (<110>= -9 x10-11 Pa-1 and <100>= -
20x10-11 Pa-1) than at low VG (<110>= -25 x10-11Pa-1 and <100>=-36x10-11 Pa-1). At
high VG, longitudinal tensile stress on <100> channel N-LDMOS shows the largest
improvement of ~2% per 100 MPa. Also, transverse stress on N-LDMOS is not as
beneficial as longitudinal tensile stress.
47
A
B
Figure 3-7. Linear Drain current enhancement versus stress for NLDMOS. A) <100>-oriented device B) <110> oriented device
Low gate overdrive
0
2.5
5
0 50 100 150 200
I DL
INE
nh
an
cem
en
t (%
)
Tensile Stress (MPa)
Longitudinal
Transverse
<110>
<110>
<100>
<100>
VGS-Vt=0.3V
<100>
VGS= rated voltage
High gate overdrive
-1.5
-0.5
0.5
1.5
2.5
3.5
0 50 100 150 200
I DL
INE
nh
an
cem
en
t (%
)
Tensile Stress (MPa)
<100>
<110>
Longitudinal
Transverse
<110>
48
In case of strained DEPMOSFET on a (100) wafer, at high VG the standard
orientation namely <110>, is the preferred channel direction. Nearly a 5% enhancement
is observed from Figure 3-8 for every 100 MPa of longitudinal compressive stress. For
the <100> channel DEPMOS, transverse compression is more beneficial than
longitudinal stress.
A
Figure 3-8. Linear Drain current enhancement versus stress for DEPMOSFET. A) <100> oriented device B) <110> oriented device
-4
0
4
8
0 50 100 150
I DL
INE
nh
an
cem
en
t (%
)
Compressive Stress (MPa)
Transverse
|VGS-Vt|=0.3V
Longitudinal
<110>
<110>
<100>
<100>
Low gate overdrive
49
B
Figure 3-8. Continued
Table 3-3. Expected and measured coefficients for <100> and <110> N-LDMOS and DEPMOS with the measurement uncertainty in brackets.
N-LDMOS
coefficient (x10-11Pa-1)
Longitudinal Transverse
Low EOX High EOX Low EOX High EOX
(100) <110> expected -3213 -32 -1513 -15
(100) <110> measured -25 (2) -9 (5) -19 (8) -6 (6)
(100) <100> expected -4713 -82 -2213 35
(100) <100> measured -36 (7) -20 (10) -15(8) 9 (11)
DEPMOS
coefficient (x10-11Pa-1)
Longitudinal Transverse
Low EOX High EOX Low EOX High EOX
(100) <110> expected 7113 71.816 -3213 -66.316
(100) <110> measured 52 (22) 51(24) -32 (7) -32 (6)
(100) <100> expected -114 6.616 23.814 -1.116
(100) <100> measured 7 (2) 11 (4) 26 (8) 19 (8)
Modeling: The -coefficient of a laterally diffused power MOSFET is estimated
based on the device model which consists of an enhancement mode MOSFET in series
High gate overdrive
-4
0
4
8
0 50 100 150
I DL
INE
nh
an
cem
en
t (%
)
Compressive Stress (MPa)
Transverse
VGS= rated voltage
Longitudinal<100>
<110>
<100>
<110>
50
with a resistor [38-40]. At low VG (weak inversion), the channel resistance (RCH)
dominates the on-resistance (RON). Thus the -coefficient of the power device is
predicted to be similar to the logic MOSFET. At high VG, RON is dominated by the drift
resistance (RD). Hence, the -coefficient is expected to be identical to bulk silicon (Si)-
coefficient. Based on this concept, the expected values for the -coefficient of power
MOSFET are listed in Table 3-3. The values for the logic MOSFET were taken from
[8]. Since the bulk -coefficient is dependent on the doping concentration [43],
measured values of n-well resistor on the wafer were used and these values were
found to be similar to Matsuda’s experimental values for n-bulk [47] and Smith’s
values were used for p-bulk [9].
As mentioned earlier, in order to accurately estimate the -coefficient of the power
MOSFET along different orientations, it is important to understand the effect of strain on
all components of RON. For the LDMOSFET, RON is the sum of channel resistance
(RCH), accumulation resistance (RACC), spread resistance (RS), and drift resistance (RD)
[41]. The -coefficient of RS (S) is a function of the angle of spread of carriers into the
bulk of the drift region. For materials with cubic symmetry such as Si, the -coefficient
along any direction can be determined from the piezoresistance tensor and direction
cosines [42, 43]. The dependence of S on spread angle for <110> n-channel device
under longitudinal tensile stress shown in Figure 3-9 is derived as shown in Equation 3-
3. Similar expressions can be derived for all stress type and directions and the result in
the form of polar plots are shown in Figure 3-9, 10.
51
A
B
Figure 3-9. N-bulk piezoresistance vs. angle of spread in drift region under stress. A) Longitudinal B) Transverse
0 10 20 30 400
10
20
30
40
10
30
20
100
co
eff
icie
nt
40
20 30 40
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
spre
adin
g
angle
[110]
<110> channel
negative
positive
0 20 40 60 800
20
40
60
80
20
60
40
200
c
oeff
icie
nt
80
40 60 80
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
spre
adin
g
angle
[100]
<100> channel
negative
positive
0 10 20 30 400
10
20
30
40
10
30
20
100
co
eff
icie
nt
40
20 30 40
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
[110]
<110> channel
negative
positive
0 10 20 30 400
10
20
30
40
10
30
20
100
co
eff
icie
nt
40
20 30 40
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
spre
adin
g
angle
[100]
<100> channel
posi
tive
52
A
B
Figure 3-10. P-Bulk piezoresistance vs. angle of spread in drift region. A) Longitudinal stress B) Transverse stress
At low VG, RON is almost completely dominated by RCH. At high VG the percentage
contribution of each component to RON for N-LDMOS is shown in Figure 3-11. Since
carriers are confined to the surface both in inversion (RCH) and accumulation (RACC), the
-coefficient of these resistances is similar to that of the logic MOSFET (MOSFET). On
the other hand the drift resistance is similar to a bulk Si resistor (Bulk). Utilizing the -
0 20 40 600
10
20
30
40
50
60
70
20
60
40
200
co
eff
icie
nt
40 60
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
spre
adin
g
angle
[110]
<110> channel
positive
0 2 4 60
1
2
3
4
5
6
7
2
6
4
20
co
eff
icie
nt
4 6
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
[100]
<100> channel
negative positive
0 20 40 600
10
20
30
40
50
60
70
20
60
40
200
co
eff
icie
nt
40 60
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
spre
adin
g
angle
[110]
<110> channel
negative
0 0.5 1 1.50
0.5
1
1.5
0.5
1.5
1
0.50
co
eff
icie
nt
1 1.5
[00-1]
coefficient
90o 80o70o
60o
50o
40o
30o
20o
10o
spre
adin
g
angle
[100]
<100> channel
nega
tive
53
coefficient of bulk Si and logic MOSFETs from Table 3-3, and associating a weight to
each of the contributing resistance from the resistance distribution, it is possible to
calculate the -coefficient of lateral power MOSFET for a given VG and channel
orientation. In case of N-LDMOSFET, for rated VG,
BulkSMOSFETLDMOS xx 56.044.0 (3-4)
Where, x is a fitting parameter representing the percentage contribution of the RS. For
the <110> channel N-LDMOS, LDMOS 9MOSFET= 32 and Bulk= 32. Since the
geometry of the STI causes the electrons to spread at an angle of ~80o, S from Figure
3-10 at this spreading angle is 34. Substituting these values into Equation 3-4 the value
of x is determined to be 0.21. With this value of x in Equation 3-4, the calculated
transverse -coefficient for <110> channel is -2 as opposed to the measured value of
6. Similarly using the polar plots in Figure 3-10 to determine S and using x=0.21, the
calculated longitudinal and transverse -coefficients for <100> channel N-LDMOS are -
26 and 10 respectively. These calculated values are very close to the measured values.
Figure 3-11. On-Resistance distribution of N-LDMOS at rated gate bias
Unlike the LDMOSFETs, DEMOSFETs have long channel lengths. Thus, in these
devices RCH remains the dominant contributor of RON even at high VG. This results in the
0
25
50
75
100
Rtotal
Perc
en
t (%
)
RDRIFT+RSPREAD
RACCUMULATION
RCHANNEL
54
high VG -coefficient of DEPMOS to be similar to that at low VG, as observed from Table
3-3.
High Stress
Experimentally measured linear drain current enhancement with stress on <100>=
oriented NLDMOS and <110>-oriented DEPMOS is shown in Figure 3-12. No saturation
effects or non-linearity was observed in lateral power MOSFETs even at stresses as
large as 500MPa. Thus performance predictions can be made using a linear
relationship between the -coefficient and applied stresses up to half a GPa.
Figure 3-12. Linear drain current enhancement under high stress
Device Voltage Rating
In order to increase the amount of voltage the device can withstand the length of
the drain extension or drift region is increased. This causes the drift resistance of the
device to become the dominating component of RON as device rating increases. An
increased RDRIFT means that the -coefficient of the power MOSFET becomes closer to
the bulk value.
VGS=rated voltage
|VGS-Vt|=0.3V
0
4
8
12
16
-350 -250 -150 -50 50 150 250 350 450
I DL
INE
nh
an
ce
me
nt
(%)
Longitudinal Stress (MPa)
<110> DEPMOS <110> N-LDMOS<100>
VGS=rated voltage
|VGS-Vt|=0.3V
0
4
8
12
16
-350 -250 -150 -50 50 150 250 350 450
I DL
INE
nh
an
ce
me
nt
(%)
Longitudinal Stress (MPa)
<110> DEPMOS <110> N-LDMOS<100>
55
Figure 3-13 shows the measured strain-enhanced drain current of <100>
NLDMOSFET and <110> DEPMOSFET with increasing drift length. As observed, IDLIN
of <100> channel N-LDMOS is seen to increase as the drift region length (LDrift) of the
device increases. With increase in LDrift the contribution of the RS to the total RON
reduces resulting in the -coefficient of the N-LDMOS to approach that of n-bulk.
For DEPMOSFETs, the low voltage rated device has no STI in the drain
extension region. Thus, the lack of RS results in of low breakdown device being similar
to the bulk value. As LDrift increases to increase breakdown voltage, a thick STI oxide is
introduced in the drift region to reduce surface field. Despite the increase in spread
resistance due to the STI geometry, no dependence with LDrift is seen from Figure 3-13
for the <110> channel DEPMOS. This is because longitudinal compressive stress does
not alter the spread resistance significantly as shown in Figure 3-11.
Figure 3-13. Linear drain current enhancement versus stress with increasing drift region length.
0
4
8
-200 -100 0 100 200
I DL
INen
han
cem
en
t (%
)
Longitudinal Stress (MPa)
DEPMOS N-LDMOS
Increasing
LDrift
56
Summary
Under 1GPa mechanical stress, the maximum expected IDLIN enhancement is
~20% for n-type and ~50% for p-type power MOSFET with the breakdown voltage
shifting < 1 V. The strain induced on-resistance improvement was largest for the <100>
N-LDMOS channel making it the preferred orientation for the strained n-type power
device. For DEPMOS devices on (100) wafer the large -coefficient along the <110>
direction makes it the preferred channel orientation. Modeling showed the contribution
of the spread resistance is significant and needs to be factored when predicting the
behavior of the strained lateral power device. With application of strain technology and
careful device design to minimize spreading, it is possible to significantly reduce on-
resistance for a given breakdown voltage.
57
CHAPTER 4 SIMULATION OF STRAINED MEMORY AND LDMOSFET
Introduction
From the previous chapters, it is clear that strain improves data retention in Flash
memory and reduces on-resistance in N-LDMOSFETs. It is also shown to deteriorate
retention in Dynamic Random Access Memory (DRAM). This chapter investigates the
incorporation of stress via process in the Flash and power MOSFET devices and
identifies the amount of process-induced stress in DRAM structures.
Current CMOS processing techniques include several methods to incorporate
strain into device structure. Uniaxial stress is introduced via capping layers and
embedded Source/Drain regions. Channel stress as high as 1GPa has been reported
[48, 49]. Biaxial stress on the other hand is produced by growing a silicon layer over
relaxed Si-Ge. The lattice mismatch introduces biaxial stress in the Si layer. The
industry has adopted uniaxial stress over biaxial stress because of the larger
performance improvement [50]. Although there has been significant discussion on the
effect of STI induced compressive stress on device behavior [51-54], logic technology
rarely uses STI induced mechanical stress for performance enhancement. This is due
to the irregular patterning of STI.
The structure and dimensions of Flash and power devices are very different from
logic devices. In general, flash has thick gate stack layer to store data and power
devices have large drift regions in order to withstand high voltages. Thus applying
processing techniques of logic devices to strain these devices may not be efficient.
Simulation is an effective and cost-saving method to investigate the various structures
to incorporate stress in these devices.
58
Overview of Simulation tool
S-Process (Sentaurus –process) and ISE FLOOPS (Florida Object Oriented
Process Simulator) are the two primary tools used to investigate the stress in device
structures. The main goal of the simulation is to determine the best method to effectively
strain the device structures that benefit from stress. For this reason simple structures
without the complication of actual processing conditions are used.
FLOOPS is a front end process modeling tool that is extremely useful in
determining process induced stress in strained silicon devices. It is based on C++ and
uses ALAGATOR as the scripting language. Stress in the device is determined by the
stress solve command. Elastic model is used, i.e. all the stress induced displacements
are within elastic limit. The boundary conditions are reflecting since the device stress is
assumed to be unaffected by the boundary.
Stress and strain in a complex device structure is obtained by solving basic
balance of force equation and Hooke’s Law using finite element method. In 2-D the
simulated structure is divided into triangles of area Δ, the material properties being
defined by matrix D and the node coordinates in matrix B. Hooke’s law is solved at each
node to obtain the displacement with the stiffness matrix given as equation 4-1. From
the displacement strain and stress at each node is obtained as below.
DBBk t (4-1)
Bx (4-2)
EBx (4-3)
S-Process is a multi-dimensional process simulation tool based on FLOOPS
developed by Synopsys. The scripting language is Alagator. Three dimensional
59
structures were simulated using this tool. Stress is determined by solving force
equilibrium equations at all nodes of the mesh consisting of tetrahedrons. Various
mechanics models are available for solving stress in materials such as: Viscous,
Viscoelastic, Elastic, etc. Elastic model is used in our simulations along with the default
Dirichlet boundary conditions which initializes the velocity normal to the plane as zero.
This boundary condition is applied to left, right, front and back surfaces. The strain
tensor in S-Process like FLOOPS, consists of two parts: Deviatoric- which describes the
material behavior under arbitrary deformation without change in volume and
Dilatational- which describes the behavior when there is a pure volume change. Built-in
stress in materials can easily be defined as well as stress caused by thermal and lattice
mismatch.
Simulation Setup
2D simulation using FLOOPS and 3D simulations using S-Process were executed.
Mesh was chosen such that the area of interest in the device had closely spaced nodes
(5-100nm) resulting in a tight mesh. Mechanical constants were initialized to the values
shown in Table 4-1. The stress in straining layer (oxide/capping layer) was incorporated
as an intrinsic isotropic stress. Stress in the device structures were analyzed using
Stress solve/ Mechdata command and stress contour plots were generated at various
device cross-sections.
Since the magnitude of stress changes with the material constants, amount of
intrinsic stress, layer thicknesses and presence of structures such as spacer, the
numerical results from these simulations may not be an exact reflection of that present
in the actual device. However, the trends obtained, gives insight into strained devices.
60
Table 4-1. Material Constants used in simulation
Material
Modulus (GPa) Poisson’s
ratio Bulk Shear Young’s
<100> Silicon 79 54 132 0.22
<110> Silicon 98 79 168 0.22
Nitride 185 122 300 0.23
Oxide 34 31 72 0.15
Strain in DRAM Transistor
One of the conclusions in Chapter 2 was that GIDL current in transistors increased
nearly 2-3% in for 100MPa of mechanical stress. This is a real concern in DRAM.
Historically the industry was focused on reducing the mechanical stress inherent to
fabrication to improve DRAM retention [55, 56]. However with the current technology
nodes incorporating strained silicon to boost device performance, the amount of stress
in the lowly doped drain (LDD) where GIDL takes place, becomes even more
significant.
The 2-D simulation structure involves a MOSFET with tensile CESL with isotropic
stress of 1.2GPa. Channel lengths ranging from 45nm-10um were studied. The mesh
was chosen so as to be fine near in the channel region and coarser deeper into the
substrate. The stress values were taken 50A below the surface of silicon at the channel
center.
61
Strained Flash Memory Device
Both floating gate and mirror bit flash memory retention shows improvement under
the application of tensile stress [33]. Currently, the structure shown in Figure 4-1 is
commercially available from Applied Materials. Unlike logic, Flash memory has
repeating patterns of STI. This makes STI stress an excellent option to strain these
devices.
Normally STI induced stress is compressive in nature. However by using High
Aspect Ratio Process (HARP) [57], it is possible to generate tensile stress using STI.
This method along with pre-metal dielectric stress is used in Figure 4-1.
Figure 4-1. Applied Materials scheme for strained NAND Flash. (Courtesy AMAT)
In this work, the effectiveness of HARP STI along with PMD on a multi-gate
structure shown in Figure 4-2 was simulated using 2D Floops. Tensile stress of 1GPa
magnitude was the intrinsic stress present in PMD and oxide layers. The stress in the
memory was monitored in the center of the array at 100A below the silicon/oxide
interface.
62
Figure 4-2. Multi-gate simulation structure with HARP STI and PMD
Strained LDMOSFET
From the measured -coefficient it is clear that the application of certain types of
mechanical stress reduces power MOSFET on-resistance without affecting its
breakdown voltage. In case of <100> N-LDMOSFET, longitudinal tension or transverse
compression can reduce device on-resistance. However, an important consideration in
moving to a newer technology is that the industry expects at least a 20% improvement
in device performance to justify the increase in manufacturing cost. It is evident from
table 4-2 that nearly 1 GPa stress is needed for the required 20% reduction in on-
resistance.
PMD
HARPSTI
Silicon
SiliconThickness=5mPoly GateLength=65nmThickness=100nmLdiff=200nmOxideThickness=27ASTIL, W=0.5mStressxx,yy =1GPa Pre Metal DielectricThickness =80nmStressxx,yy=1GPa
63
Table 4-2. Beneficial stress for N-LDMOSFET
Stress Type Strained Region Determination Reduction in RON/ GPa stress
Longitudinal Tension
Entire Device <100> N-LDMOS 20%
Transverse Compression
Drift region <100> N-Bulk resistor 17%
Measured bulk -coefficients indicate that for <100> N-LDMOSFET, transverse
compression on the bulk drift region can also significantly reduce RON (~1.7% for
100MPa). This is because nearly 50% of RON in LDMOSFET is contributed by drift
region. Further in <100> oriented device, even the carriers spreading into the bulk of the
drift region will experience transverse compression if the stress is along <110>. Thus all
carriers are benefitted by the applied transverse compression resulting in a reduction in
spreading resistance.
Nitride capping
Nitride capping layers can apply either compressive or tensile stress on the entire
device. However capping layers are most effective for short channel devices. Thus in
order to use this method to strain power devices which have large drift lengths, dummy
gates with short gate lengths are utilized throughout the drift region. This structure was
proposed in reference [58] and is shown in Figure 4-3.
64
Figure 4-3. N-LDMOSFET with dummy gates and nitride capping
The simulation nested gate structure (Figure 4-4) is similar to Figure 4-3 and the
dimensions are based on results from reference [59]. Channel stress dependence on
gate length illustrated in Figure 4-5 shows that above 50nm of gate length the stress in
the channel is virtually negligible. Also the channel stress increases with decreasing
gate length. Thus the dimension of the dummy gates is chosen to be 45nm. Since
nearly a Giga-Pascal of longitudinal tensile stress is required for 20% device
performance improvement, an in-built isotropic stress of 1GPa is present in the nitride
capping layer. The simulation is used to determine the stress contours along the drift
region.
STIn+p+
N--well
n+
P-well
Nitride Capping Poly Si
65
Figure 4-4. 2D capping layer on N-LDMOSFET simulation structure
Figure 4-5. Longitudinal channel stress vs. gate length in logic MOSFET with tensile capping layer [59]
Poly gate
Silicon substrate
Tensile Nitride
capping
Gate to gate distance
Direction of increasing
substrate depth
Si substrate: Thickness = 10m
Nitride Capping Layer Thickness = varying
Default = 80nm
Built-in stress = xx=1GPa,yy=1GPa
Poly Si GateGate length = 45nm
Thickness=140nm
Gate to gate distance = varying
Y
X
Y
Z
66
STI induced stress
DIELEC RESURF [60] is a structure that is currently being investigated, since it
has the potential to increase the breakdown voltage of the lateral power MOSFETs.
This structure shown in Figure 4-6 also has regular patterns of STI interleaving the drift
region. Presence of the STI increases the depletion width across the reverse-biased p-n
junction thus decreasing the electric field (Figure 4-7). The regular patterns of STI in this
structure can be utilized to strain the drift region of the power MOSFET. Since drift
region resistance (RD) accounts for more than half of the on-resistance (RON) of the
device, stressing the drift region so as to reduce its resistance is also an effective
method to reduce RON.
Figure 4-6. DIELER structure
STI
gate
source
drain
STI STI STI
STI STI STI STI
STI
STIGate
N-well
N+N+
P-Sub
67
Figure 4-7. Principle of Dielectric RESURF [60]
2D structure was simulated using FLOOPS and the three dimensional structure
shown in Figure 4-8 was simulated using Sprocess. Dependence on active area (moat
width) and STI dimensions was investigated along with the uniformity of stress along the
STI depth.
Figure 4-8. STI induced stress simulation structure for 2-D and 3-D
p-Si
VBD=21.5V
p-Si
n-Si n-Si oxide
VBD=22.5V
Wd Wd
STI oxide
Moat/STI width
Active spacing
Silicon
Moat/STI depth
Silicon Substrate:Depth = 10m
STI
Width=1m
Depth=1mBuilt in stress xx=yy=1GPA
Active regionWidth = 0.24m
oxide
N-Silicon
Z
Y
X
Silicon Substrate:Depth = 5m
Thickness = 1m
STI
Width=1m
Depth=1mBuilt-in stress xx=yy=zz=1GPa
Active regionWidth = 0.24m
68
A 17% reduction in on-resistance is estimated by 1GPa transverse compression
on the <100> oriented drift region. Even carriers that spread vertically into the substrate
experience the transverse compressive stress, thus there is no detrimental effect due to
the spreading of carriers.
Results and Discussion
Strain in DRAM Transistor
The magnitude of stress at the center and gate-edge in devices of different
channel length is shown in Figure 4-9. As is seen from figure, even long channel
devices suffer from nearly 100MPa of stress at gate edge even though the channel
stress is negligible. This means that the GIDL is 2-3% larger than a device without any
capping layer. Thus effect of stress needs to be considered when considering strained
transistors for DRAM.
Figure 4-9. A process simulation of built-in stress in the middle and the gate edge of the channel in a strained Si MOSFET with stressed silicon nitride CESL
-100
0
100
200
300
400
0.01 0.1 1 10
Bu
ilt-
in S
tre
ss
[M
Pa
]
Gate length, Lg [um]
Channel under
gate edge
Middle of channel
69
Strained Flash Memory
The simulation results (Figure 4-10) prove that as the distance between the STI
increases (number of bits increases) the stress starts to decrease. Also the stress from
the STI is maximum at its edges and progressively reduces as we move away from the
STI. This means that as the number of gates in the multigated flash memory increases,
the uniformity in the magnitude of the stress induced by the STI reduces. However this
is overcome by the tensile PMD. The simulation result shows that STI or PMD alone is
not as effective in straining the NAND flash as is the combination of the two. From the
measurement on Flash devices, it was seen that even a small amount of tensile stress
was able to make a measurable difference in retention. So straining the flash memory
using PMD and STI can successfully enhance performance in these devices.
Figure 4-10. Stress in NAND flash memory due to STI and PMD
Ten
sile
Str
ess
(M
Pa)
# of Bits
# of bits
Stress monitor device
Ten
sile
Str
ess
(M
Pa)
# of Bits
# of bits
Stress monitor device
70
Strained LDMOS
Nitride capping with dummy gates
As seen from Figure 4-5, even at 45nm gate length the channel stress is
~400MPa. So the stress in device through this method is small.
The dummy gate structure results in tensile stress beneath the gate but along the
distance between the two gates, the stress becomes compressive (Figure 4-11). Thus
stress uniformity is a concern in this structure especially since longitudinal compressive
stress is detrimental to device performance.
A
Figure 4-11. Stress in nested gate structure. A) Expected simulation result of LDMOS with tensile capping layer B) Actual simulation cross section from [60]
71
B
Figure 4-11. Continued
Gate to gate distance can be reduced to decrease the non uniformity of stress
type along the device. However this comes with the price of reducing the magnitude of
stress. Beyond pinch off (Figure 4-12), we can expect the stress to increase, however
this method is strictly limited by processing considerations. Increasing the thickness of
nitride layer might improve the stress magnitude as shown in inset. However as shown
in Figure 4-11, the stress magnitude over the entire device is insufficient to produce any
considerable gain in device performance.
72
Figure 4-12. Stress in device center as a function of gate to gate separation. The inset [59] shows the change in stress in device center as a function of capping layer thickness
Another issue in this method is that the magnitude of stress reduces drastically as
we go deeper into the substrate. This method is effective for producing stress on the
surface; however electrons spread vertically into the substrate in LDMOSFETs. So the
success of this method to effectively improve power MOSFET device performance is
questionable.
STI induced stres
From results reported in reference [59] (Figure 4-13), STI is an excellent method to
incorporate stress in devices. The type and magnitude of stress will depend on
processing conditions of the STI oxide and dimensions of active and STI regions
respectively. Stress produced via the STI interleaves is analogous to the channel stress
73
induced by the Si-Ge source drain in logic PMOSFETs. Thus significantly large value of
transverse compressive stress is expected.
Figure 4-13. STI induced stress in active region [59]
From literature the stress is expected to be uniform along the depth of the STI
region [61, 62] and thus in LDMOSFETs even the carriers that spread into the bulk of
the drift region can be strained by choosing the depth of STI taking the current flow
pattern into consideration.
2D floops simulation confirms the uniformity of STI induced compressive stress
along the depth direction. Also magnitudes of stress are ~650MPa. Deeper trenches are
more useful in straining LDMOSFETs since the current spreads up to a micron depth in
these devices.
74
Figure 4-14. 2D stress contours of STI induced stress in active drain extension fingers
S-process simulation of 3 D structure showed some interesting results. Not only
was there large magnitudes of transverse compression, but there was also equally large
out of plane tensile stresses present. Figures 4-15 through 17 show the stress contours
in the silicon fin across device cross-section taken in the center of the silicon fin of the
3-D simulation structure.
Y
X
028m
Y
X
1m
75
Figure 4-15. Transverse compression along the fin
Figure 4-16. Out of plane tension along the fin
Y
Z
yy
Z
Y
zz
76
Figure 4-17. Longitudinal tension along fin
Since drain extension or drift region contributes to nearly 50% on RON, 500MPa
transverse compression predicted would result in RON reducing by 17.5%. This
calculation is a result of using piezoelectric -coefficients measured previously. The
40MPa of longitudinal tension along the <100> oriented fin will result in a 3.2%
reduction in RON. However also present was 600MPa of out of plane tension. This is
equivalent to applying biaxial compression on the fin. This stress will degrade mobility
and cause an increase in RON by 21%. Thus the result is that there is no net change in
on-resistance under stress.
Summary
Using simulation tools the best method to incorporate stress into Flash and
LDMOSFET structure was investigated. The combination of PMD and STI stress proved
to be a successful method of straining NAND flash devices. Capping layer stress on
LDMOS with dummy gates, however, was not effective. Preliminary simulation results
77
on STI stress on drain extension fingers show the presence of a large out of plane
tensile stress apart from the compressive stress perpendicular to direction of current.
This stress counter-acts the enhancement in carrier mobility produced by the
compressive stress. Further investigation to overcome this stress will result in success
of STI strained power MOSFETs.
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CHAPTER 5 SUMMARY AND RECOMMENDATIONS FOR FUTURE WORK
Summary
The effect of stress on memory retention and power MOSFET performance was
measured and analyzed. Mechanical stress was applied using four point wafer bending
jig and I-V characterization was done using Keithley 4200 SCS. Memory retention as a
function of stress was analyzed by monitoring leakage and threshold voltage shift under
data retention bake for memory. Extracted piezoresistance and breakdown
characteristics were determined for power LDMOSFETs.
For memory, DRAM retention deteriorated with stress while Flash retention
improved with tensile stress. Power MOSFET on-resistance reduced with stress and no
significant shift in its breakdown voltage was observed. Under 1GPa mechanical stress,
the maximum expected IDLIN enhancement is ~20% for n-type and ~50% for p-type
power MOSFET with the breakdown voltage shifting < 1 V. The strain induced on-
resistance improvement was largest for the <100> N-LDMOS channel making it the
preferred orientation for the strained n-type power device.
Thus with careful consideration memory and power device performance can be
enhanced with mechanical stress.
Recommendations for future work
This work showed that stress was detrimental to DRAM retention. Future work in
this area needs to concentrate on the reduction of stress in these devices.
Strained retention can be studied in newly emerging Flash technologies such as
TANOS and FinFET SONOS. Also effect of strain can be examined on exotic memory
devices such as Magnetic RAM, FeRAM and phase change memory.
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In order to successfully incorporate stress in power MOSFETs, effect of strain on
novel structures and devices on hybrid wafers need to be studied. STI shows a lot of
promise to incorporate stress in DIELER structures. With proper choice of lining layers,
this structure can be successfully manufactured. Process and device simulations on
these structures will help understand the impact of strain and establish baseline
numerical values as to the expectation of device improvements.
80
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BIOGRAPHICAL SKETCH
Umamaheswari Aghoram (Uma) was born in Chennai, India. In 2003, she
graduated with distinction from the University of Madras receiving a Bachelors degree in
electrical engineering. She received her master’s degree and doctorate in electrical and
computer engineering from the University of Florida in 2005 and 2010 respectively. She
is currently employed as a process integration engineer in Texas Instruments
Incorporated. Her areas of interest include semiconductor device design and circuits.
