C Previous Page | Contents | Zoom in | Zoom out | Refer a...

DC

qqM

Mq

qM

MqM

Qmags®THE WORLD’S NEWSSTAND

DC

qqM

Mq

qM

MqM


Previous Page | Contents | Zoom in | Zoom out | Refer a Friend | Search Issue | Next Page


____________________

_______________

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM




http://www.levitronix.com


http://www.solid-state.com

http://www.qmags.com/SST/Referrals/refer_a_friend.asp

http://www.qmags.com




AUGUST/SEPTEMBER 2011

www.solid-state.com

Advances in Double-patterning p. 14

EUV OPC Flow Optimization p. 18

Scatterometry Measurement of28nm Metal Gates p. 11

Contents | Zoom in | Zoom out Search Issue | Next PageFor navigation instructions please click here

Contents | Zoom in | Zoom out Search Issue | Next PageFor navigation instructions please click here


CLEAN99% Particle Removal Efficiency at the 88mm, 65mm, and 45mm Nodes

STRIP & LIFT-OFFImmersion and Single Wafer Processing

High Velocity Spray Rotary PVA Brush Heated Solvent Immersion Heated High Pressure Scrub

WET ETCHUniform, Selective Etching on Multiple Process Levels

COAT / DEVELOPPhotolithography Clusters

Stream Etch for Films & MetalsWafer Thinning Low Impact DevelopingSpin Coating

SINGLE WAFER WET PROCESSORS & CLEANERS

FAB

RIC

AT

ION

EQ

UIP

ME

NT

FO

RT

HE

IN

TE

GR

AT

ED

CIR

CU

IT I

ND

US

TR

Y

ssecusa.com©2010 Solid State Corporation

Solid State Equipment

CorporationSINGLE WAFER WET PROCESSING AND CLEANING

SSEC 3308 SYSTEMS

3308 - 8 Process Modules

Eight station, fully automatic single wafer processing configured for higher

volume production with class 1 cleanliness environment for processing.

Processes may be complex, serial step

processing from station to station or

parallel processing, all in SEMI® Safety

and Ergonomic Compliant system.

Put the power of technology

to work for you, to increase

process yields and lower

operating costs. With SSEC’s

45 years of experience,

you can count on us.

3308 - 8 Process Modules

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM




http://www.ssecusa.com







FE AT U RES

C O N T E N T S

AU G /S E P T 2 011 Vol. 54 • No. 8

www.solid-state.com ■ August/September 2011 ■ Solid State Technology 1

RESISTS

Double-patterning, topcoat-less

photoresists and silicon hard masks

Double-patterning, spin-on silicon hard masks, and

topcoat-less resists are enabling immersion lithography

to meet today’s advanced technology node requirements.

Mark Slezak, Brian Osborn, JSR Micro, Inc.,

Sunnyvale, CA.

EUV MASKS

EUV OPC fl ow optimization

for volume manufacturing

EUV OPC fl ows can be optimized to meet stringent

production turn-around-time and accuracy

requirements of future nodes. Kevin Lucas,

Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys Inc.,

Mountain View, CA, USA

RESISTS

Improving line roughness

by using EUV assist layers

Because no single method is delivering the needed

reduction in LER, combining the benefi ts of an assist

layer material during EUV lithography and a smoothing

process aft er lithography might be the dual-prong

solution that is needed. Carlton Washburn,

Brewer Science, Inc., Rolla, MO USA

14

18

21

The interior of KLA-Tencor’s SpectraShape tool, which includes a multi-azimuth spectroscopic ellipsometer with broadband light extending into the deep UV portion of the spectrum and a polarized, enhanced UV refl ectometer.

CDS

Scatterometry measurement for gate

ADI and AEI CD of 28nm metal gates

Measuring CD Data show that a new generation SCD

tool has good sensitivity and measurement repeatability

for the 28nm HKMG ADI process. Y. H. Huang, et al.,

United Microelectronics Corporation,Tainan Science Park,

Taiwan, C. H. Lin, KLA-Tencor Corp., Milpitas, CA.CO

VE

R A

RT

ICL

E

11

World News 6

Tech News 8

■ Is 3D packaging where it needs to be?

■ AMAT’s DRAM fab tools for denser transistors

■ Samsung-Grandis spotlights MRAM potential—

and uphill climb

Web Exclusives 2

Ad Index 23

DEPA R TMEN T S

COLUMNS

Editorial 4

The 450mm transition:

many unanswered questionsPeter Singer, Editor-in-Chief

Industry forum 24

Leveraging collaborations to drive down

the LED cost curve Jeff Desroches, ATMI, Inc., Tempe, AZ USA

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











2 Solid State Technology ■ August/September 2011 ■ www.solid-state.com

Diane Lieberman, Group PublisherPh: 603/891-9441, [email protected]

Peter Singer, Editor-in-Chief Ph: 603/891-9217, [email protected]

Meredith Courtemanche, Editor, Digital MediaPh: 603/891-9176, [email protected]

Robert C. Haavind, Editor-at-Large Ph: 603/891-9453, [email protected]

Debra Vogler, Senior Technical Editor, Ph: 408/774-9283, [email protected]

James Montgomery, News Editor Ph: 603/891-9109, [email protected]

Laura Peters, Contributing Editor

Phil Garrou, Contributing Editor

Rachael Caron, Marketing Manager

Cindy Chamberlin, Presentation Editor

Katie Noftsger, Production Manager

Dan Rodd, Illustrator

Debbie Bouley, Audience Development Manager

Marcella Hanson, Ad Traffi c Manager

EDITORIAL ADVISORY BOARD

John O. Borland, J.O.B. Technologies

Jeffrey C. Demmin, Tessera Technologies Inc.

Michael A. Fury, The Techcet Group, LLC

Rajarao Jammy, SEMATECH

William Kroll, Matheson Tri-Gas

Ernest Levine, Albany NanoTech

Lars Liebmann, IBM Corp.

Dipu Pramanik, Cadence Design Systems Inc.

Griff Resor, Resor Associates

Linton Salmon, TI

A.C. Tobey, ACT International

EDITORIAL OFFICES

PennWell Corporation, Solid State Technology

98 Spit Brook Road LL-1,

Nashua, NH 03062-5737;

Tel: 603/891-0123; Fax: 603/891-0597;

www.solid-state.com

CORPORATE OFFICERS

1421 SOUTH SHERIDAN RD., TULSA, OK 74112

TEL: 918/835-3161

Frank T. Lauinger, Chairman

Robert F. Biolchini, President and CEO

Mark Wilmoth, Chief Financial Offi cer

TECHNOLOGY GROUP

Christine A. Shaw, Senior Vice President and Publishing Director

Gloria Adams, Senior VP, Audience Development

For subscription inquiries:Tel: (847) 559-7500; Fax: (847) 291-4816;Customer Service e-mail: [email protected];

Subscribe: www.sst-subscribe.com

We make portions of our subscriber list available to carefully screened companies that offer products and services that may be important for your work. If you do not want to receive those offers and/or information, please let us know by contacting us at List Services, Solid State Technol-ogy, 98 Spit Brook Road, Nashua, NH 03062. All rights reserved. No part of this publication may be produced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage retrieval system, without written permission of the copyright owner. Prices for bulk reprints of articles available on request. Solid State Technology articles are indexed in Engineering Information and Current Contents, and Applied Science & Technology Index and abstracted by Applied Science & Technology Abstracts.

Solid State Technology ONLINE

Web Exclusives

ONLINE AT WWW.SOLID-STATE.COM

SEMICON WEST 2011Th is year’s fl agship show felt a lot more optimistic

all around this year, judging by observations and comments from visitors and exhib-

itors and even SEMI itself. And SST was busier than ever: More than two dozen video

and podcast interviews with industry execs, researchers, and analysts. Half a dozen

bloggers—in addition to our own editors—reporting from all areas of the show fl oor

and conference sessions, from 3D integration to FinFETs to EUV, and high-growth

markets including LEDs and solar PV. We also rounded up of dozens of new products

launched at this year’s show, from front-end processes to backend testing to compo-

nents in between. Everything is online at electroiq.com/semicon_west_2011.

450mm transition: Must-know

changes, cost hurdlesBill Shaner from Entegris discusses key changes in the semiconductor manufacturing

industry’s move from 300mm to 450mm wafers: wafer fragility and sag, increased

weight, and more capital investment. And Crossing Automation’s Bob MacKnight

highlights the industry’s top three cost-related hurdles when it comes to the 450mm

wafer size transition—particularly how automation will mesh with new tools.

Renesas post-quake:

Rebuilt and revitalizedRenesas’ rebuilding eff orts following the March 11 disaster

are the epitome of courage, teamwork, dedication, and

learning from adversity—sometimes with unexpected

benefi ts.

CEA LETI ReviewCEA-LETI gave SST an exclusive look at this summer’s Annual Review, with discus-

sions on a variety of hot topics: sustaining Europe’s semiconductor industry, IDM’s top

challenges, III-V/Si integration, and maskless lithography progress.

When to outsource: Ask the right

questions and avoid pitfallsMark Danna from Owens Design shares a critical list of questions for companies

considering outsourcing a project. While outsourcing can benefi t mature (semicon-

ductor) and emerging (photovoltaics) markets, the wrong decisions or strategies can

destroy all of outsourcing’s proposed benefi ts.

Lithography CoO, and extending

with complimentary e-beamDavid K. Lam from Multibeam addresses lithography cost-of-ownership, and how

the industry does not have to “throw out” optical lithography as it proceeds to more

advanced nodes—complementary e-beam lithography (CEBL) is a strong option.

___________________

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM





http://www.sst-subscribe.com


http://www.electroiq.com/semicon_west_2011

http://WWW.SOLID-STATE.COM







Finding the right solution to your company’s materials’ needs has never been easier, because �� !��"��# �� #�� $ ��

Before.

�� % �� &�� %��&��!�� &�� !�'&!��(�� (�� )��(� ��$ ��(�� !�'&!��&(�'�*+�

After.

We’ve just made reaching your goals easier than ever.

_________

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM




http://www.materion.com







E D I T O R I A L


The move to a larger wafer size -- from 300mm to 450mm

– has been the focus of an interesting debate for the last

fi ve years. Th e largest semiconductor manufacturing

companies in the world – Intel, TSMC and Samsung – have

been strongly advocating the move, urging equipment

suppliers to start development (which has started) and

SEMI to create the necessary standards (which is done).

Equipment suppliers have been understandably slow to

embrace the change, given the long time for them to see

the return on their investment during the last wafer size

transition (200mm to 300mm).

Th e move to 450mm took on

some new urgency at this year’s

Semicon West. Applied Materials

announced that it would spend

$100 million on developing

450mm tools (which some say is

just the cost of doing feasibility studies),

companies such as EVG and KLA-Tencor

introduced new 450mm products, and several panel sessions

were devoted to the topic.

Many questions remain unanswered. Although most

people seem to agree that it’s no longer a question of “if”

but only “when,” there’s still a long way to go.

Speaking on one of the panels was Gartner’s Bob Johnson,

research vice president, semiconductor manufacturing, who

noted that the move is purely a cost play, with a target goal

of a 30% reduction in production costs. Th e problem, said

Johnson, is that there is a fundamental confl ict of interest

between semiconductor and equipment manufacturers.

“Th e way it looks right now is we’ve got the opportunity to

spend billions of dollars on R&D that could go for other

projects, and end up cutting the market (for equipment)

by about 30% going forward. Th is is not a heck of a lot of

incentive to put a lot of the R&D money out there.”

Johnson also questioned the real cost savings that have

been gained by previous wafer size transitions. “If you look

at the 30 year period from 1980 to 2010, we had 14 major

technology node changes, each one generating, over roughly

a two-year period, about a 50% reduction in cost. Th at’s

30% per year,” he said. During that time, there were three

major wafer size transitions. “Each wafer transition was

about the equivalent of one year’s worth of scaling. Wafer

size changes really didn’t have a lot with reduction of costs.

What happened instead was shrinks, scaling, cleverness

in making smaller cell sizes and a lot of the other things

that process engineers do to keep

driving things forward,” he said.

Presently, although some tools have already been intro-

duced, 450mm is still at the feasibility stage. “We don’t really

know if we can do it or not,” Johnson said. “Once we start

putting pilot tools in, the costs start going through the roof.

Th is is fairly standard. Feasibility is relatively cheap. Hopefully,

we can decide one way or the other whether this will be worth

it before we start spending cubic gigabucks on R&D.”

Another unanswered question is how many technology

nodes will be left by the time 450mm wafers

are in production. Intel is starting

22nm in production at the end of

this year or early 2012. Th at means

that they’ll be at 7nm right aft er

the fi rst 450mm production fab

is slated to be in operation. “We

hear people talking, ‘We can do 32nm,

we can do 22nm with some of these tools.’ So

what? When 450mm comes into production, we’re going to

be at 14nm or 10nm or below technologies. Th at means we

need EUV, immersion for mix-and-match, and probably dry

litho all to be economically viable,” Johnson said. “Th e next

question we have is how many nodes do we have? How long is

conventional silicon going to keep going aft er we pass 10nm

level, and I don’t think anybody knows the answer to that.”

Johnson provided an interesting look at ROI consid-

erations, comparing the market and thinking during the

transition to 300mm in 1997, to the way it is today. “In 1997,

we were convinced, looking in our rearview mirror, that

the industry growth that was going on at 17% per year was

going to continue forever. We didn’t realize that we already

passed the infl ection point two years earlier, and we weren’t

going to realize that for another for our fi ve years. Now we

know that the long term growth trend in the industry is

mid single digits, somewhere around 6%/year. If you look at

the ability of the industry to generate funding for fabs and

everything else, it’s much less than it was back in 300mm

days.” We could reasonably look at about ten nodes over

the product life of 300 mm tools. Now if we look forward,

maybe 3? Maybe one? I submit if 450mm is really going to

end up being a single node product, it ain’t worth it.” Truer

words have never been spoken. ■

Pete Singer

Editor-in-Chief

“If 450mm is really

going to end up being

a single node product,

it ain’t worth it.”

The 450mm transition: Many unanswered questions

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











��

��

��

�� !"!�# ��$%&'&��()��'*�(%$$�+�,-.�-,+��/��#!0�1-�

��2#�3-4!��+�!��0�#!�#�5!��!�607��8�9��!��/0!�6!:6 �;��1-�!#��59+1#�

��<�,!�0�#!=�#7#6!�#��8�#+0+1-� �1!��+1 ��-69!��4�,!��6!�+�0��5�6-�;$$��

��-��6��#5��!�6 �#!�+�6��#5��!�6��-5�>�!��?�4�,!��8+�@�

��2#�'$A�7!��#�-,�!:5!�+!�1!�5�-"+�+�@�#5!1+�0+B!��0�#!��1-�50!6!��8+�@�#-0�6+-�#�

��3-4!��+�!��&$��C�69!�,�#6!#6��-�/0!�9!��0�#!��8!��"�+0�/0!�4+69�-"!��%�$$��3��

��2#�-4��0�#!��6!19�-0-@7��<-�0�4+�! ��4��4+��+�@�1�#6-�!��#!�"+1!��;&D)�#�55-�6�

E��

�3��

��

_______________

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM




http://www.rofin.com







2010 2011 2010 2011

Monthly change

-10%

-5%

0%

5%

10%

15%

JMAMFJDNOSAJJ-20%

0%

20%

40%

60%

80%

JMAMFJDNOSAJJ

EuropeJapan

Asia PacificAmericas

EuropeJapan

Asia PacificAmericas

Yearly change

WaferNews sources: SIA, WSTS

*Based on a three-month moving average

W O R L D N E W S


■ BUSINESS TRENDS

Semi growth outlooks less rosy for 2011

Outlooks for 2011 semiconductor growth aren’t quite as

optimistic as they were just a few months ago. IC Insights

has halved its projection to 5% (vs. 10%), with only the OSD

segment (optoelectronics, sensors, and discretes) remaining

flat. IDC also has lowered its 2011 forecast, to the floor of

its previously projected 6%-8% range, and tweaked down

its outlook for global MPUs (9.3% vs. 10.3%) after seeing

shipments and revenues decline -4% in 2Q11. Those overall

forecast adjustments are more in line with the 5.4% the

WSTS and SIA have been predicting, even with a -2% decline

in 2Q11 chip sales. (Back in June iSuppli slightly raised its

outlook to 7%.)

What’s putting a damper on 2011 outlooks? Macroeco-

nomic headwinds, ranging from the Japanese March 11

disaster to Middle East unrest to continued economic uncer-

tainty in the US and Europe. GDP growth has been slowing for

about a year, notes IC Insights, though 2H11 should be “moderately

better” thanks to Japan’s rebound and rebuild from the March 11

disaster, lower gas prices, and tax breaks.

Note that these forecasts, as of press time, do not include any

long-term impact from the S&P’s Aug.5 downgrade of US credit

rating, nor similar action looming against some EU nations. IC

Insights’ end-of-July update predicted US and EU debt crises would

“lessen” in 2H11 to help its outlook—but that was before the S&P’s

move, which spawned a subsequent week of multi-hundred-point

volatility in major financial markets worldwide. ■

WORLDWIDE HIGHLIGHTSPhotoresist revenues will grow at about

5% for the next several years, says Techcet

Group, which says consolidation is long

overdue among resist suppliers, and EUV

may be the last straw.

Intermolecular has inked a deal with

GlobalFoundries to use its combinatorial

technology on R&D for semiconductor

manufacturing lines covering 45nm down

to 14nm.

Avantor and SACHEM have developed a

new selective etch chemistry that doubles

as wafer cleaner.

Ajit Manocha has been appointed interim

CEO at GlobalFoundries; both CEO Doug

Grose and COO Chia Song Hwee are

stepping aside.

Surging gold prices—especially given

recent US and EU economic turmoil—

are accelerating an increase in Cu wire

shipments, says Techcet.

A trio of companies dominates the $3.3B

set-top box IC market, which is expected

to flatten out over the next few years, says

ABI Research.

Silicon semiconductor wafer growth was

nearly flat year-over-year in 2Q11 says

SEMI, noting the “impressive” unbroken

supply chain in the aftermath of the Japan

earthquake,.

Cypress Semiconductor and UMC say they

have produced working silicon on 65nm

SONOS fl ash.

AMERICASA temporary stand-in process used in

solvent cleaning being started up for

the first time was behind a June fire at

Intel’s Fab 22 facilities in Chandler, AZ.

Brazil has given CEITEC the green light for

the nation’s fi rst chip fab.

KLA-Tencor has joined SEMATECH’s

lithography defect reduction program,

housed at the U. of Albany’s College of

Nanoscale Science and Engineering (CNSE),

to collaborate on several areas of EUV

lithography.

Veeco has dropped its CIGS tool business,

saying it hasn’t generated returns soon

enough.

Georgia Tech researchers have used zinc

oxide nanowires to create a new type of

piezoelectric resistive switching device,

which can be used to build self-powered

nanoelectromechanical systems.

Worldwide semiconductor sales by region, based on a 3-mo. moving average. (Source: SIA, WSTS)

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











Vistec Electron Beam Lithography Group I www.vistec-semi.com

Why should you use an electron beam lithography systemfrom Vistec?

Based on our broad experience gathered over many years of developing, manufacturing and world-wide servicing fi eld-proven electron beam lithography systems a team of highly-motivated employees, excellent researchers and high-quality engineers is constantly doing their best to fulfi l our customers’ requirements.

Your Dedicated Performance Partnerfor Electron Beam Lithography

Meet us at Semicon Europe in Dresden at booth 1.209


Two execs with Varian ties have new gigs:

former CEO Garry Rogerson is the new

CEO at Advanced Energy, while current

VSEA exec Stan Yarbro is now a FSII board

member.

ASIAFOCUSSMIC has appointed Tzu-Tin Chiu as

its new CEO, replacing David Wang

who resigned in July. Chiu most recently

was president/CEO of Hua Hong NEC.

Samsung has widened its lead on in the

NAND flash market to 40% market share,

vs. 28% for Toshiba and 13% for Hynix,

says DRAMeXchange. Samsung and

Hynix also are reportedly speeding devel-

opment of 2Xnm DRAM modules to ramp

production by year’s end.

Undeterred by two unsuccessful bids over

the past decade to kick-start domestic chip

manufacturing, the Indian government has

launched yet another bid to attract investors

for domestic chip fabs.

Hitachi has rolled out enterprise-class MLC

SSDs built with Intel’s 25nm NAND flash

technology.

A Samsung study finds no link between

its chip plants and cancer, though labor

advocates are challenging the study’s trans-

parency and independence.

Gigaphoton says its EUV (LPP source)

debris mitigation technology now achieves

93% Sn removal.

Nomura has sold all its shares in semicon-

ductor packaging substrate maker Eastern

Co. to the firm’s parent company.

Renesas has divested its audio processing

chip business to Murata Manufacturing.

Researchers in China report a “break-

through” in densely doping indium to give

coral-like SnO2 nanostructures, for use in

gas sensors.

Dongbu HiTek has ramped volumes of

Chinese firm BYD’s CMOS image sensors.

Tokyo Electron Device and Powercast have

jointly developed a cell phone chip that

converts RF energy to electricity.

EUROFOCUSEV Group has released a wafer bonding

system for 450mm SOI wafers; Soitec will

qualify the first one this fall.

SPTS management has completed a buyout

(enterprise value ~$200M) with backing

from EU private equity firm Bridgepoint.

EV Group is adding fl oorspace, equipment,

and recruiting 100 workers in an expansion

of its Austrian headquarters.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM





http://www.vistec-semi.com







Basic Process Flow:

1. Coat polymer adhesive on device

2. Create carrier: Release zone and stiction zone

3. Bond face to face

4. User processes: Thin, pattern, etc.

5. Remove stiction zone adhesive

6. Mount device side on film frame

7. Separate carrier from adhesive

8. Clean adhesive from device

Device

Carrier

Stiction zone

Release zone

Device

Polymer adhesive

Thin device

and

1

2

3

4

5

7

8

6

Carrier

Adhesive on device

ZoneBONDTM carrier

T E C H N O L O G Y N E W S


More than a hundred attendees gathered at a Suss

MicroTec workshop at this year’s SEMICON West (“3D

Integration: Are we there yet?”) to hear technical experts

from around the globe to present updates on the status

of 3D IC packaging.

Eric Beyne of IMEC addressed the technical issues of carrier

systems for 3D through-silicon via (TSV) thinning and backside

processing, pointing out that right now silicon carriers are favored

over glass because: (1) the glass must be CTE matched to silicon

over a large temperature range, (2) the

high cost of ground to tight TTV speci-

fication, and (3) a negative effect on

plasma-based post-grinding backside

processes due to its low thermal conduc-

tivity. After alignment and temporary

bonding, Beyne recommends the use

of use of in-line metrology to insure

bonding integrity before grinding occurs.

Rama Puligadda, division manager

for advanced materials R&D for Brewer

Science, indicated that their Zonebond

room-temperature debonding process is

meeting all customer requirements and

is moving toward full commercial intro-

duction. The Zonebond process basically

uses a 2.5mm ring of adhesive to hold the

wafer in place for grinding and backside

processing. This allows for easier subse-

quent debonding. The thin wafers are released from the carrier at

room temperature after mounting on a film frame.

Stephen Pateras, product marketing director at Mentor

Graphics, pointed out that TSVs can be used to create test access

paths so that all BIST resources can be accessed on any device.

Pateras also concludes that all EDA players need to support

common test access infrastructures since this will be required

to stack die from difference sources.

Eric Strid of Cascade Microtech revealed that the company

is producing lithographically printed probe cards by MEMS

techniques capable of 6μm sq. x 20μm high probe tips on 40μm

pitch for testing dense 3D IC pads. “Such technology allows

scalability to lower cost and finer pitches,” he said, adding that

these probe cards “are being sold in research quantities.” Standard

pad locations are required for vendor interchangeability, and

“standard materials specs for pads are needed in terms of materials,

thickness and fl atness,” he reported.

Stefan Lutter, bonder project manager for Suss MicroTec,

discussed the company’s open platform approach, which is capable

of using any of the following bond/debond technologies. They see

temporary bonding trending toward the newer room-temperature

(RT) release processes.

Suss’ new product introduction is a HVM debonder/cleaner line

for the new RT release processes. — Dr. Phil Garrou, contributing

editor

Applied Materials debuted three systems at SEMICON West

for next-generation DRAM chip manufacturing: the Centura

DPN HDTM system to improve the gate insulator scaling,

the Endura HAR Cobalt PVD system for high-aspect-ratio

(HAR) contact structures, and the Endura Versa XLR W PVD

system for reduced gate stack resistance. (Also at SEMICON West,

Applied decloaked a new Vantage Vulcan RTP tool for 2Xnm with

backside wafer heating, and a new deposition and UV curing toolset

for 22nm interconnects.)

Key transistor technologies, borrowed from logic devices, are

helping DRAM chips achieve better performance and speed,

overcoming a “memory wall:” the speed of the control circuitry

that transfers data between the memory cell array and external data

bus. These transistors are denser and more advanced, requiring new

toolsets, Applied asserts.

The Applied Centura DPN HD system incorporates nitrogen

atoms into the gate insulator to improve its electrical characteristics.

The high-dose gate stack system for oxynitride gate scaling is said

Is 3D packaging where it needs to be?

AMAT’s DRAM fab tools for denser transistors

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











Provides control

for on/off state

Oxynitride

Polysilicon

gate

SourceSource

CarriersCarriers

ChannelChannel

DrainDrainSilicon

Nitrogen

content

Insulates gate

electrode from

channel

1:1 ≤3:1 ≥7:1

HAR cobalt PVD

Step coverage

requirement

ALPS step coverage Co

→ 65nm

50nm 35nm

120nm

High aspect ratio PVD

for 2x DRAM

Aspect ratio

Aspect ratioDRAM

0 250 500 750

Versa PVD

Versa XLR PVD

20% reduction

1000 1250

Normalized resistivity

Thickness (Å)


AN EXCITING NEW CONCEPT INPLASMA TECHNOLOGY

PLASMA-PREEN��

Manufactured from a Microwave Oven

Hybrid Cleaning-Ceramic CleaningWire Bond Pad CleaningDie Attach Pad CleaningEpoxy Bleed RemovalFlux Residue RemovalPhoto Resist RemovalSurface Preparation for

Welding, Soldering and Inking

Plasmatic Systems, Inc.1327 Aaron Road

North Brunswick, NJ 08902TEL: (732)-297-9107FAX: (732)-297-3306

Email: [email protected]

to increase DRAM periphery speeds, which enhance DRAM output. The HD technique

builds on Applied’s decoupled plasma nitridation (DPN) technology for advanced logic

and memory fab. Decoupled plasma nitridation enables high surface nitrogen content

(Fig. 1). Higher nitrogen content leads to higher capacitance, thus enabling equivalent

oxide thickness (EOT) scaling, explained David Chu, global products management at

Applied Materials.

The other

members of the

product tr io

addressing 2Xnm

DRAM scaling

challenges are

the Endura HAR

Cobalt PVD tool

for periphery

contacts, and the

Endura Versa

XLR W PVD

tool for memory

gate electrodes.

Kevin Moraes,

director of product

management for

metal deposition

Figure 1. The gate dielectric/oxide. Decoupled plasma nitridation enables high surface nitrogen content. (Source: Applied

Figure 3. The Versa XLR W PVD chamber enables lower gate resistance required for 2Xnm.

(Source: Applied Materials)

Figure 2. Logic-derived expertise for fast DRAM implementation.(Source: AMAT)

AMAT’s continued from page 8 products, emphasized the impetus behind the

HAR Cobalt PVD chamber (Fig. 2) and the

need to transition from TiSi2 to cobalt. (Listen

to the interview at electroiq.com/podcasts).

Cobalt replaces titanium for transistor contact

metallization on the Endura Cobalt system,

depositing uniform films in high-aspect-ratio

contact structures with 50% lower contact

resistance than titanium. DRAM devices

fabbed with the lower-resisitivity element can

have faster switching speed and lower power

consumption, he explained.

Meanwhile, the Applied Endura Versa XLR

W PVD system is a tungsten-based tool that

is said to offer a 20% reduction in gate stack

resistivity (Fig. 3). Th e optimized reactor

design improves consumable component

lifetimes as well.

Together these two products (PVD Co)

replace the much cheaper TiCl4 process,

which has been used for many years but

has shortcomings. An interesting sidenote

to the introduction of these products is that

using PVD instead of CVD runs counter to

industry expectations. — D.V.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM





http://www.plasmapreen.com

http://www.electroiq.com/podcasts







1-800-USA-PUMP www.buschusa.com

A vacuum solution just for YOUR application.

The COBRA DS series dry screw vacuum pumps areideally suited for semiconductor and solar processes.These single-stage pumps maximize uptime, reduceenergy consumption, provide a high ROI and are capable of advancedmonitoring and interfacing between the pump and the process tool. Expect the best when you specify Busch.

To order: 714-578-6000

Fax: 714-578-6020

Low-Cost Solutions for High-Tech Industries

MODULAR CLEANROOMS

��

�� !�"#�$ �%�&��'�%��%�

�%�&��

��(�� )��*��$ �%�� %�$��

��(+��&��%�& � ��

Convert anyspace into a

ISO 4–8 facility

TECHNOLOGY NEWS continued from page 10


Korean semiconductor giant Samsung Electronics has acquired

Grandis, a maker of spin-transfer torque random access memory

(STT-RAM), a flavor of magnetic random-access memory (MRAM).

The only details disclosed were that it closed in July, covering “the

full scope” of Grandis technology, assets, and HR, and will be folded

into Samsung’s memory chip R&D operations.

MRAM’s promise is for its nonvolatility, power efficiency, and

operation at ultrahigh speeds, for applications requiring high-

density memory or lower power consumption (e.g. smart phones).

It’s also touted for its scalability, beyond 32nm or whenever current

memory technologies finally lose steam. However, current memory

technologies have continued to scale well enough to keep such

next-gen memory technologies at bay—Intel famously said back

in 2003 that NAND flash wouldn’t be able to scale past the 60nm

node, and now it’s at 20nm and counting, notes Jim Handy from

Objective Analysis, and Toshiba/Sandisk reportedly have a 19nm

device dubbed “1X” and another called “1Y” in the works suggesting

another node in the hopper.

Perhaps this Samsung-Grandis deal is no more than IP positioning,

“a preemptive move by Samsung to secure potential IP and technology

in the MRAM arena, and not necessary representing a significant

move forward in bringing the technology to mass production,” says

Michael Yang, principal analyst for memory and storage at IHS

iSuppli. Note that Toshiba and Hynix recently announced their

own MRAM partnership, aiming to eventually create a production

JV and cross-license patents, joining forces to minimize risk and

accelerate MRAM’s pace toward commercialization. Hynix CEO

Oh Chul Kwon called MRAM “our next growth platform,” while

Toshiba’s Kiyoshi Kobayashi pledged to “strongly promote initiatives”

integrating products from MRAM to NAND to HDD.

Keep in mind that Samsung already has put its bet down on phase-

change memory (which it calls PRAM), and claims to be shipping

actual devices. (Others touting improvements in PCM over the past

few months: an IBM/industry/academiaconsortia, Numonyx/Micron,

Samsung, and KAIST.) Buying Grandis suggests Samsung is at least

covering its IP bases in next-gen memory tech—or maybe it’s even an

outright change of strategic direction, Handy speculates.

In the end, it all comes back to scalability. As long as memory

makers continue to extend existing memory technologies’ limits—and

at higher volumes and lower costs—next-gen memory technologies

won’t get the hard push they need to prove manufacturing cost-

competitiveness and achieve commercialization. — J.M.

Samsung-Grandis spotlights MRAM potential—and uphill climb

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM





http://www.buschusa.com

http://www.terrauniversal.com







PR

Si

BARC2

BARC1

HM_HT

Poly_HT

Poly_TCD

Poly_WA

MG_recess

HK_recess

HM_recess

HM

Poly

MG

HK


Scatterometry measurement for gateADI and AEI CD of 28nm metal gates

MEASURING CDs

For reduced gate leakage and enhanced

device performance, many IC manufacturers utilize novel metal gate tech-

nologies instead of traditional poly silicon gates. The new materials and

geometries required to form metal gates mean that new parameters con-

trol the optimization of device performance [1]. Traditional gate process

control has relied heavily on scatterometry for ensuring that variation in

structural dimensions remain in control, as some dimensional deviations

can strongly affect device performance. A new-generation scatterometry

tool with multiple extensions to traditional scatterometry technology is

evaluated as a production process monitor for complex metal gate struc-

tures at the 28nm device node and beyond.

E XECUTIVE OVE RVIE W

Inline control and monitoring of the dimensions of the high-k

metal gate (HKMG) structure are critical for device perfor-

mance [2]. This paper focuses on dimensional measurement and

control of a 28nm high-k metal gate for two layers: after-develop

inspection (ADI) and after-etch inspection (AEI). For ADI, critical

measurement parameters include side wall angle (SWA) and critical

dimension (CD). The ADI structure is very challenging for traditional

scatterometry measurements because the six different films under the

photoresist (Fig. 1a) result in high correlation among measurement

parameters. For the AEI process, nanometer-sized variations in the

high-k and metal gate recess relative to poly Si width (Fig. 1b) affect

device performance [3]. This recess represents another challenge

for traditional scatterometry tools because nanometer-sized varia-

tions are difficult to detect. To qualify for production process control

of these structures, the metrology tool must not only be sensitive

to variations in all key structural parameters, but also be precise,

non-destructive, and capable of production-worthy throughput.

Critical dimension scanning electron microscopy (CD-SEM)

nearly qualifies—except that not just CD but also shape metrology

is required. Scatterometry emerges as the only near-term option.

We decided to evaluate a new-generation spectroscopic critical

dimension (SCD) metrology tool, KLA-Tencor’s SpectraShape

8810, to determine if it had the sensitivity and precision required

for measurement of critical parameters on metal gate structures.

The new tool’s core technologies include a multi-azimuth (“multi-

AZ”) spectroscopic ellipsometer with broadband light extending

into the deep UV portion of the spectrum [4] and a polarized,

enhanced ultra-violet reflectometer (eUVR).

The multi-AZ and multi-channel capabilities

of this new tool promised enhanced critical

parameter sensitivity and reduced correlation

between parameters. We planned to gather data

from process of record (POR), focus-exposure

matrix (FEM) and design of experiment (DOE)

wafers to characterize the performance of this

new SCD tool on metal gate ADI and AEI struc-

tures. We also planned to compare metal gate

AEI scatterometry measurement results to trans-

mission electron microscopy (TEM) reference

measurements. This evaluation process was designed to demon-

strate the ability of this new-generation scatterometer to serve as

a production process monitor for complex metal gate structures

at the 28nm node and beyond.

Experiment and results

High-k metal gate ADI. The first study was designed to determine

the sensitivity and precision of scatterometry measurement for a

28nm high-k metal gate ADI layer. Two wafers were used in the study.

The first was exposed with a focus-exposure matrix (FEM), while

the second was exposed with constant, standard (POR) lithography

conditions. For the same DOE conditions, there were two targets

in one field: one for an NMOS structure and a second for a PMOS

structure. AcuShape2 advanced modeling software was used to

break the parameter correlation. The floating parameters used in

the model (the measurement parameters) include the critical param-

Y. H. Huang, C. H. Chen, K. Shen, H. H. Chen, C. C. Yu, J. H. Liao, United Mi-croelectronics Corporation, Tainan Science Park, Tainan County 741, Taiwan, R.O.C. C. H. Lin,KLA-Tencor Corporation, One Technology Drive, Milpitas, CA, USA

Figure 1. a) ADI model and stack information; and b) AEI model and parametric description

for HKMG.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











53.00

48.00

43.00

38.00

33.00

53.00

48.00

43.00

38.00

33.00

F+1 F+2 F+3 F+4 F+5 F+6 F+7 F+8

F+1 F+2 F+3 F+4 F+5 F+6 F+7 F+8

E+1 E+2

E+3

E+4

E+5

E+6

E+7

E+8

E+9

E+10

E+1E+2

E+3

E+4

E+5

E+6

E+7

E+8

E+9

E+10

MCD (nm)

MCD (nm)

Focus

Focus

SCD NMOS PR MCD Bossung curve

SCD NMOS PR MCD Bossung curve

NMOS PMOS

FEM

Baseline

PR MCD

PR SWA

PR MCD

PR SWA

Measured CDs continued from page 12


eters photoresist height (PR_HT), middle CD (MCD) and sidewall

angle (SWA); plus the heights of BARC1, BARC2, hardmask and poly.

The scatterometry measurement requirements included: 1) dynamic

precision <0.1nm or <0.1degree; 2) sensitivity to dose and focus on

the FEM wafer; and 3) baseline wafer verification.

The MCD measured by scatterometry versus focus and energy

exposure for both NMOS and PMOS targets are displayed in Fig. 2.

The Bossung curves for the NMOS and PMOS structure indicate that

scatterometry has good sensitivity to focus and exposure variations

during photolithography.

The MCD and SWA of whole wafer map plots for the FEM wafer

and the baseline wafer are shown in Fig. 3. Th e wafer maps show

that MCD decreases from left to right for both NMOS and PMOS

targets and the SWA is increasing from left to right. These results are

consistent with the FEM DOE pattern. For the baseline wafer there

is no clear pattern observed, as expected.

The dynamic precision of MCD, SWA and resist height (PR_HT)

was measured on the baseline wafer: ten repetitions with wafer load

and unload for 11 sites. The results showed that scatterometry has

excellent precision with a demonstrated 3 sigma of less than 0.1nm

for MCD and resist height, and less than 0.1 degree for SWA.

High-k metal gate AEI. To demonstrate the new tool’s sensi-

tivity and precision for the HKMG AEI profile, seven DOE wafers

with varying process conditions were prepared. The DOE wafer

varied three critical parameters, metal gate recess (MG_recess),

high-k recess (HK_recess) and poly side wall angle (SWA), and two

non-critical parameters, poly Si CD and hard mask (HM) height

(Fig. 1b). The scatterometry measurement requirements for this

HKMG AEI process layer were: 1) dynamic precision <0.1nm or <0.1

degree; 2) metal gate and high-k DOE sensitivity; and 3) correlation

to the TEM reference measurement.

The high-k recess and metal gate recess are the most critical param-

eters in this application. Because the metal gate and high-k layer

thickness under poly is very low, the sensitivity of the scatterometer

to variations in the MG and HK recess is also very low. To improve

the scatterometry measurement sensitivity and precision for the HK

recess and MG recess, the multi-AZ and multi-channel approaches

were used. 2D contour maps of MG recess and HK recess revealed

that the variations in MG recess and HK recess across the wafer were

within 1nm and followed a concentric pattern. The edge of the wafer

had a higher MG recess and a lower HK recess.

HK recess and MG recess data from all DOE wafers showed that

the SCD tool was able to recognize the MG recess and HK recess DOE

splits. Poly BCD and SWA data were also collected for all wafers on

the DOE list. The results showed that the new tool is able to distin-

guish poly BCD and poly SWA DOE splits.

The dynamic precision of critical parameters for HKMG AEI was

measured on the POR wafer. As before, the 11-site measurement was

performed ten times with wafer load and unload. The results showed

that the tool has excellent precision for the critical parameters. The

average of 3 sigma dynamic precision is less than 0.05nm for MG

recess, 0.07nm for HK recess and less than 0.03 degree for SWA.

Metal gate AEI: correlation to TEM. To verify in-line

scatterometry measurement accuracy, a transmission electron

microscope (TEM) was used as a reference. The TEM measured

two sites on each wafer, at the center and at the edge, for a total

of 14 TEM data points in the DOE wafer set. The scatterometry

measurement values were compared with the corresponding TEM

values. The MG/HK CD and MG/HK recess results are shown in

Figure 2. MCD as function of focus and exposure for NMOS target (top) and PMOS

target (bottom).

Figure 3. Wafer maps of MCD and SWA for DOE wafer and baseline wafer.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











35 35

30

25

20

15

30

25

20

15

15 20 25 30 35 15 20 25 30 35

TEM (nm) TEM (nm)

1.6 2.5

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

1.2

1.4

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4-1.0 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5-0.5 0.0 0.5 1.0

TEM (nm) TEM (nm)

SCD (nm) SCD (nm)

MG CD HK CD

y = 1.0538x + 0.1107

R2 = 0.9693

y = 0.9761x + 0.4332

R2 = 0.9617

y = 1.0267x – 0.4459

R2 = 0.9763

y = 1.0167x – 0.1789

R2 = 0.9544

MG recess HK recess

SCD (nm) SCD (nm)


Fig. 4. Th e R2 correlation of metal gate CD and high-k CD is about

0.97 and the slope is around 1.05. MG recess and HK recess are the

most critical and challenging parameters. The SCD correlation with

TEM shows an R2 greater than 0.96 for MG recess and 0.95 for HK

recess, and a slope around 1.0 +/- 0.03. For all critical parameters the

R2 correlation was greater than 0.95 and the slope was 1.0 +/- 0.05.

These TEM correlation results confirm that the new generation

SCD tool can be used as an in-line monitor for the 28nm high-k

metal gate etch process in production.

Conclusion

As semiconductor structures become increasingly complex, they

require ever more sophisticated metrology for characterization

and process control. A new-generation SCD tool combines

multi-AZ and multi-channel optical signals, providing the

metrology performance required for advanced structures in

metrics such as precision and accuracy. Data presented in this

paper has demonstrated that this new tool has good sensitivity and

measurement repeatability for the 28nm HKMG ADI process. For

AEI, this tool has the sensitivity to track DOE conditions, and the

measurement results correlate very well with the reference TEM

measurements. With its high sensitivity, high throughput, and

nondestructive measurement capabilities, the new scatterometry

dimensional metrology system has proven to be suitable as a 28nm

HKMG ADI and AEI process monitor. ■

Acknowledgments

The authors thank Xiafang (Michelle) Zhang, Russell Teo, Zhi-Qing

(James) Xu, Sungchul Yoo, Chao-Yu (Harvey) Cheng and Jason Lin

of KLA-Tencor Corporation for their contributions to this article.

A more detailed version of this manuscript originally appeared in

Metrology, Inspection, and Process Control for Microlithography XXV,

ed. Christopher J. Raymond, Proc. of SPIE Vol. 7971, 79712O, 2011.

References

1. M. Sendelbach, A. Vaid, P. Herrera, T. Dziura, X. Zhang, A. Srivatsa, “ Useof multiple azimuthal angles to enable advanced scatterometry applications,”Proc. SPIE Vol. 7638, (2010).

2. M. Sendelbach, W. Natzle, C.N. Archie, B. Banke, D. Prager, D. Engelhard,J. Ferns, et al., “Feedforward of mask open measurements on an integratedscatterometer to improve gate linewidth control,” in Metrology, Inspection,and Process Control for Microlithography XVIII, edited by Richard M. Silver,Proc. of SPIE Vol. 5375 (SPIE, Bellingham, WA 2004) pp. 686-702.

3. N. Collaert, M. Demand, I. Ferain, J. Lisoni, R. Singanamalla, P. Zimmer-man, et al., “Tall triple-gate devices with TiN/HfO2 gate stack,” 2005 Symp.VLSI Tech. Dig. of Papers, paper 7A-2.

4. T. G. Dziura, B. Bunday, C. Smith, M. M. Hussain, R. Harris, X. Zhang, J. M.Price, “Measurement of high-k and metal fi lm thickness on FinFET side-walls using scatterometry,” Proc. SPIE Vol. 6922, (2008).

Contact author

Yu-Hao Huang is a senior engineer at United Microelectronics Cor-

poration, Tainan Science Park, Tainan County 741, Taiwan, R.O.C.;

ph.: 886-6-5054888 ext.11637; email [email protected]

Figure 4. MG/HK CD and MG/HK recess correlation between SCD tool and TEM reference.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











1st litho.

Post develop

bake

2nd litho.


Double-patterning, topcoat-lessphotoresists and silicon hard masks

RESISTS

Double-patterning has allowed us to

push the limits of 193nm imaging, and is where leading edge photoli-

thography stands today. The blend of incredibly low k1 imaging, improve-

ments in scanner alignment capabilities, the ability of mask houses and

designers to provide extremely complicated pattern stitching, and the

move toward one directional mask layouts, have all paved the road for

new and exciting materials solutions in double-patterning. The integra-

tion of double-patterning has also allowed more opportunities in the

ancillary area of specialty materials with technologies such as spin-on

hard masks, freezing/shrinking/slimming agents, along with immersion

topcoats and topcoat-less resists.


The semiconductor industry is relying on materials innovation

more and more as we begin to run into fundamental limits

of physics. Photolithography anxiously awaits the implemen-

tation of EUV, as its 13.5nm wavelength

of light will allow lithographers to work under

more relaxed k1 imaging. The reality, however,

is that there are many challenges associated

with EUV, such as light source reliability,

masks (and the ability to inspect them), photo-

resist sensitivity and line edge roughness. The

good news is that EUV is making strides

and the first full-field EUV tools are being

delivered now. The bad news is that it will

be awhile before the lithography community

relies on EUV as the workhorse solution for

critical layer lithography.

Double-patterning

Double-patterning is a technique that has

served well as an interim process between

ArF immersion and EUV. Double-patterning

has taken on many mantles within the lithog-

raphy community, but at its most basic, it is two

patterning steps done for one layer. There are

a variety of ways to accomplish this, such as:

Double-patterning. Th is technique uses

two resists and two consecutive sequences of resist patterning,

exposure and development.

Double exposure. In this technique, the same photoresist layer

is exposed twice, using either different or offset

masks, and/or altogether different illumination

conditions.

Dual-tone resists. These photoresists have

both positive and negative tone aspects, which

are patterned based on the relative exposure dose,

being cross-linked (negative tone) in high dose

areas and positive tone in lower dose areas.

Self-aligned spacer. This typically involves

patterning a semidense pitch (1 line to 3 spaces)

using a conventional ArF or ArFi (immersion)

resists, followed by either chemical-vapor

deposition (CVD) or spin-on SiO2, which creates an oxide layer

atop the resist pattern. The top of the resist pattern is revealed via

etch, then the photoresist removed, leaving an equal line space (1

line 1 space, 1:1) relief image

of oxide as the final, trans-

ferred pattern. Depending on

the mask layout, an additional

lithography step (often called

a cut mask) is needed to trim

the ends of the lines that were

deposited with SiO2.

Litho-etch, litho-etch

(LELE). This technique is

perhaps the least time and

cost effective, but easiest to

immediately implement.

The LELE process does two

complete lithography and

etch sequences for a single

device layer. While lengthy

and costly, it can be done now

with existing materials, tools

and mask sets.

The primary technique for

double-patterning is: the first

resist is patterned in a typical

lithography process, and will then have the second resist coated

directly on top of it and subsequently patterned – hence, the double

patterns. However, this means that there cannot be any chemical

intermixing due to solvent or chemical component miscibility

between the first and second resists.Mark Slezak, Brian Osborn, JSR Micro, Inc., Sunnyvale, CA USA

Figure 1. Thermal freeze double-patterning cuts down on processing steps and

provides a better overall cost of ownership over many other double patterning

techniques.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











Layer 1

24.85nm

50.89nm

54.44nm

31.95nm

Layer 2


Chemical freeze reagents/thermal cure resists

Two compelling methods to minimize the potential for intermixing

in double patterning are the use of chemical freeze reagents or

thermal cure resists. Chemical freeze employs a separate material

that is dispensed on the first resist pattern, cross-linking (“freezing”)

the outside or entirety of the resist. A thermal cure process is where

the first resist can be effectively cross-linked, or otherwise rendered

solvent insoluble, with a high temperature bake after initial patterning

is complete. The thermal route is more advantageous than chemical

freeze within a manufacturing environment, as the introduction of

an additional bake step (and subsequent cool step) is the only process

change necessary for thermal cure (Fig. 1).

Recent work with the thermal freeze method using JSR thermal

curable first resist, and the specially designed second resist, was

presented at the 2011 SPIE Advanced Lithography conference. Initial

pitch split work at a targeted 64nm pitch was demonstrated, showing

the capability and robustness of the designed system (Fig. 2). Work

at smaller pitches and tighter CDs is ongoing.

Negative tone development

Finally, negative tone development (NTD) is a relatively new

technique that is showing much promise in double-patterning.

Instead of the usual tetramethylammonium hydroxide (TMAH)

developer used in lithography, an organic solvent is used instead.

Photoresists that are traditionally rendered soluble in the exposed

areas are instead soluble in the unexposed areas, leaving a negative

tone image of a positive tone resist. It takes some time to navigate

and conceptualize this new NTD technique with the milieu of double

patterning schemes, but NTD shows strength in theory and practice.

We have found that an NTD process can work better than positive

tone develop (PTD) in certain cases, such as contact holes, due to

the higher aerial image contrast seen for these features. This “bright

field” application has a better aerial image than does the conven-

tional contact hole, which is done on a mask area with high chrome

coverage (“dark field”). The downside is that using solvent as

developer automatically incurs an initial increase in materials, and

hence process cost. There can also be tool or even infrastructure costs

associated using with this process.

Whereas NTD can show significant improvements in conven-

tional resist patterning schemes, it can be more powerful in a

double-patterning process. Low k1 imaging that was previously

too difficult in single patterning, let alone double-patterning, can

be accessed with NTD and then further sized down with double-

patterning. The combinations of techniques available for double-

patterning (thermal cure, chemical freeze, LELE, NTD, et al) make

it a very attractive choice for manufacturers trying to bridge the

gap between immersion and EUV.

Immersion resists and topcoat materials

An immersion topcoat is an additional layer atop the photoresist that

protects the scanner from possible contamination. Additionally, this

topcoat is used to manage the wafer / scanner interface through the

manipulation of the contact angle of the film that comes in contact

with the water lens from the immersion scanner. While, topcoats are

in wide use today, there can be technical and economic drawbacks.

Most topcoats are somewhat acidic and this can create more dark

loss or resist top rounding of the profile. The extra processing steps

incurred by the topcoat use are not minute and must be taken into

consideration for throughput of a process flow. Finally, the cost-of-

ownership of topcoats must be acknowledged: they add extra cost to

an immersion process due to use of an additional material. However,

these upfront costs can be balanced against the preservation of

the immersion tool integrity, overall lower defect counts, and the

enabling of a higher resolution patterning process that ultimately

yields less expensive device production.

Beyond the use of topcoats is the advent of topcoat-less

resists (Fig. 3). Here, no topcoat is used, but the photoresist

is still qualified as immersion-capable with similar or better

levels of defectivity and tool protection. The solution lies in the

engineering of the topcoat-less photoresist formulation, which, if

done correctly creates an in situ topcoat.

Topcoat-less immersion photoresists have the same set of

Figure 2. This figure demonstrates the use of thermal freeze where line 1 and line 2 are 32nm features at a 64nm pitch.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











RCA (deg)

RCA behavior

Total defects: ~10,000

After SB

After dev.

Total defects: ~500

Conventional non-topcoat

photoresist

Modified non-topcoat

photoresist

Resist

Topcoat

Non-topcoat resist

WaterWater

Topcoat process

Pros: Allows conventional ArF resist chemistry use

Cons: Adds an additional process

Pros: Shorter process cycle time

Cons: Need to develop immersion specific resist

Non-topcoat process

Topcoat


Resists continued from page 15

requirements and properties as a photoresist that requires a

topcoat but come as an added component to the resist and

does not necessitate extra track processing steps to create an

immersion barrier. However, while the economical cost benefits

are readily apparent, technical challenges exist for topcoat-

less resists. Examples of these challenges come in the need to

precisely engineer the receding contact angle (RCA) of topcoat-

less photoresist films to match the needs of advanced immersion

tools sets and their scan-speed requirements of >500mm/s, while

still making the film hydrophilic enough after exposure to have

favorable dissolution rates in TMAH developer (Fig. 4).

Spin-on silicon hard masks

As numerical apertures (NA) and ultimate resolution increase, depth-

of-focus decreases, often leading IDM lithography layer owners to

reduce photoresist thickness to gain back focus depth. This leaves less

etch resistance for the pattern transfer into the underlying substrate.

The aforementioned double-patterning, depending on which scheme

is used, relies a great deal on advanced etch techniques to transfer

resist, self-aligned spacer (oxide) or thermally/chemically cured resist

patterns into the desired substrate. A simple bottom anti-reflective

coating (BARC) does not typically offer sufficient etch resistance or

selectivity for any of these processes.

One solution to these issues in immersion lithography and double-

patterning is to use a hard mask directly beneath the photoresist

that functions both as a pattern transfer layer and an antireflective

material. Usually, a BARC layer provides reflectivity control, but it

does not always have the necessary etch resistance. Ideally a silicon-

containing layer with good reflectivity control would work best and

such materials have been implemented in advanced development

lithography groups around the world.

The spin-on silicon anti-reflective coating (or SiARC) material

is placed between the resist and an underlying organic planarizing

layer, also called carbon underlayer, forming a tri-layer scheme for

ArF immersion lithography processes. The optical properties for the

Figure 3. By tuning the contact angles of topcoat-less resists, material companies are able to improve the defect density seen on wafer post develop.

Figure 4. A summary of the pro’s and con’s of the use of topcoat in immersion lithography vs. the use of topcoat-less resists

continued on page 22

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











____________

_____________

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM




http://www.sil-ledjapan.com

http://www.sil-ledjapan.com








EUV OPC fl ow optimization for volume manufacturing

EUV MASKS

Extreme ultraviolet (EUV) lithography is

a leading contender for patterning of the 2X node memory and 14nm

logic manufacturing and will provide signifi cant relaxation in k1 factor

versus existing 193nm lithography. However, EUV does add additional

diffi culties to mask synthesis fl ows such as across-slit shadowing variation,

across-reticle fl are variation, new resist effects, and signifi cant increases

in fi le size. This article will investigate EUV-specifi c issues and solution

options for a production mask synthesis fl ow, including different correc-

tion and fl ow automation approaches. Improved methods help enable

EUV optical proximity correction (OPC) tapeout fl ows to achieve compa-

rable or better metrics than existing 193nm lithography fl ows.

E XECUTIV E OVE RV I E W

The 14nm logic node will have features at a minimum half-pitch

of approximately 24 to 28nm, and the industry’s fi rst high-

volume manufacturing (HVM) for these nodes will likely start

in 2015. Several 1.35NA 193nm optical lithography options

have been considered for patterning at the 14nm node, including

double patterning, triple patterning, and self-aligned double

patterning. Another option is to lower the light wavelength to 13.5nm

with 0.32NA EUV scanners. Th is enables relatively high k1 lithog-

raphy and may off er the resolution required for the 10nm device

generation by increasing projection system numerical aperture (NA).

With leading semiconductor manufacturers receiving beta EUV

scanners in 2011-12, the pace of EUV integration development

will rapidly accelerate. Th erefore, the demand for accurate and fast

EUV OPC soft ware to synthesize reticle patterns will substantially

increase in the near future. However, there are several fl ow issues

to resolve before OPC is ready to meet integration and production

needs. Th is article will examine those fl ow issues and some state-of-

the-art solutions [1].

Introduction to EUV OPC

Th ere are several new physical eff ects that need to be considered in

EUV OPC. Several of the most important are:

• Long-range fl are (scattered light from roughness in the lens

elements), which varies in intensity across the exposure fi eld [2-4];

• Long-range refl ected light from the large EUV mask absorber

regions at the edges and corners of the exposure fi eld, which are

in between the reticle bladed-off region and the desired exposure

area [5];

• Long-range exposure position-dependent

and scan-dependent asymmetric fl are eff ects

modifi ed by fl are apertures in the scanner

[6,7]; and

• Shadowing eff ects from the interactions of mask

absorber topography and the non-normal main

optical exposure angle which varies across the

reticle [3].

Th ere are a number of technical challenges in

adapting OPC for long-range eff ect correction. Th e

radius over which fl are and shadowing eff ects are

calculated may be in the 20+mm range compared

to the typical OPC kernel range of 1-2μm. Brute-force methods of

incorporating these long-range eff ects into OPC will not be fast

enough to meet the turn-around-time (TAT) requirements of mask

synthesis fl ows. For fl are, clever approximations are required to

speed up the computations while achieving accuracy requirements

of approximately 0.10% 1σ fl are error for development applications

and 0.05% 1σ fl are error for production. Additional reticle scale

and scanning-dependent fl are and shadowing eff ects must also be

accurately encapsulated into compact models, which can run quickly

on extremely large layouts.

EUV mask synthesis full fl ows and issues

Th ere are several major OPC issues that result from correction

of signifi cant long-range physical eff ects. One issue is that each

chip placement is now lithographically distinct and must receive a

unique OPC modifi cation. For reticles with only one or a few place-

ments of a very large chip, the impact on OPC is not great. However,

for the typical case where there are many placements of a medium-

sized or small chip, the impact on OPC is very large, i.e., many

chips will have to be OPC processed in order to defi ne a reticle. A

related issue is that we can no longer assume multiple placements of

a single cell inside a chip design are lithographically identical. Th is

is due to the diff erent magnitudes of fl are and shadowing eff ects

across each individual chip placement. Th e combination of these

two issues results in the requirement that OPC must produce a fi nal

post-OPC data fi le with little or no design hierarchy (i.e., fl at) that

covers the entire exposure fi eld of the reticle. Th e resulting TAT

and post-OPC fi le size will then be much larger than is typically

handled with OPC for 193nm lithography.

A fl ow diagram of a typical EUV mask synthesis total fl ow is

shown in Fig. 1. Th is fl ow includes the following steps: pre-OPC Kevin Lucas, Jonathan Cobb, Johnny Yeap, Munhoe Do, Synopsys Inc., Mountain View, CA, USA

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











Input design received,

pre-OPC, tiling, etc.

Reticle layout defined,

flare map created

OPC with MB shadowing

and MB flare

EUV reticle verification

Mask data prep and fracture

FTP to mask shop

Buried defect avoidance

per mask blank

Y

X

Y Y

X X


(biasing for device and process considerations); reticle layout creation

(placement of individual chips in the reticle field); OPC (including

both model-based flare and model-based shadowing compensation);

full model-based OPC verification; MDP (mask data prep and

fracture to create the final reticle data); FTP (to either an internal or

external maskshop); and mask defect avoidance (shifting the layout

pattern relative to the mask blank to avoid irreparable EUV buried

mask defects from printing on a critical layout feature [8]). The TAT

to meet fab cycle-time goals for the same advanced mask synthesis

flow are typically 12 to 24 hours for OPC, OPC verification and MDP/

fracture steps; and less than a few hours for other steps. Because of

the across-reticle effects that need to be handled in EUV, traditional

OPC methods may lead to missing these TAT goals by many hours

or even by several days.

OPC improvements for EUV

Significant improvements are needed to enable EUV mask synthesis

flows to meet overall TAT requirements. Improvements in TAT can

be obtained by optimizing the methods used to compute new EUV

physical effects. To illustrate this, several different methods were

investigated for EUV flare computation across the reticle (e.g., [1,2,

9-10]) and a method implemented that exhibited both high accuracy

and speed. Accuracy was benchmarked against a rigorous lithog-

raphy EUV simulator’s full-chip flare computation for different

layouts. The flare error between the OPC model computed flare and

the rigorous simulator was found to be lower than the production

target accuracy of 0.05% 1σ for a scanner with a flare TIS of 4.5%.

This method of flare calculation can enable recalculation of the

flare map in just a few minutes from a density map.

Increasing speed without sacrificing model accuracy is possible

by optimizing long-range shadowing modeling. Figure 2 illustrates

a new faster mask-based shadowing compensation methodology.

This method enables fitting both the ideal shadowing bias across

the reticle scan and empirically observed process and tool specific

characteristics. These shadowing model speedups and accuracy

enhancements also benefit the full-reticle, full-model-based OPC

verification step.

New EUV mask synthesis flows to improve TAT

The TAT improvements described above offer significant benefits

for individual components in the mask synthesis flow. However,

further improvements are necessary to make up for a) the large

increases in TAT flow expected due to the full flattening of reticle-

level data as input to OPC; and b) the very large data files, which

take considerable time to be passed between components in the

flow. Another problem with the large data files in EUV is that any

steps in the flow that are not highly distributable (across many

processor cores) quickly become bottlenecks and begin to dominate

the overall TAT. MDP/fracture tools do not distribute linearly to

many hundreds of processors, as OPC does. In addition, read-in/

out steps of tools are generally poorly distributable. Therefore, as

data volumes continue to rise into multiple terabytes of data per

layer [11], lower scalability steps can lead to significant flow delays.

To counteract these issues, a parallelized combined OPC + MDP

flow for EUV can be implemented that utilizes the massive parallel-

ization capability of data cells/templates that have finished all OPC

and cell context updating. Completely finished cells/templates can

be passed in a pipeline to start MDP/fracture modification well before

the full OPC job has completed. This effectively enables massive

Figure 1. Typical EUV mask synthesis flow containing pre-OPC, OPC, OPC verification, MDP and

EUV mask defect avoidance steps. Sample graphical examples for each flow step are shown at

right. [1] Used with permission of SPIE.

Figure 2. Example of a new mask-based shadowing compensation methodology. The different

wafer contours across the reticle slit for the same input mask pattern can be clearly seen. [1]

Used with permission of SPIE.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











EUV-OPC

Application

concurrency

LRC

I/O

operations

I/O

operations

Time savings

I/O and

file

transfer

MDP FTP

Traditional flow

Parallelized flow

Time

Time


EUV Masks continued from page 19

parallelization of read-in/out and MDP/

fracture steps (Fig. 3).

Experimental results show sizeable

TAT savings with such a parallel approach

[10]. For a large (600mm2 area, 16nmlogic)

test case running in standalone mode,

MDP took approximately 16hrs. Running

the same test case in parallel mode took

exactly 1 hour − 15-hour savings in

reticle data availability for mask write. In

a moderate sized 3X node DRAM chip

example running in standalone mode,

MDP took 1.5 hours, but running the

same test case in parallel mode took only

3 minutes. As this DRAM chip would be

repeated 15 times in the reticle field, the

estimated TAT for a full reticle case is 22.5

hours vs. 45 minutes, achieving a savings

of over 21hrs in data availability for mask

write. TAT savings will further increase

for denser 10nm node logic and 2X/1X

node memory cases.

Unfortunately, EUV’s large post-OPC

and post-fracture file sizes causes the FTP

transfer between different groups within a

company or to the mask shop to take many

hours of user time. Currently, FTP of a 40nm mask set (all layers)

that is 1 terabyte (TB) post-fracture often takes 12hrs on a fast FTP

connection to the mask shop. Thus, the FTP step alone for a single

1X node RAM single layer file of 3.3TB would take more than 36hrs.

To meet these requirements, existing MDP/fracture functionality can

be reused, parallelizing the FTP of huge post-fracture data files well

before fracture has completed. Results on very large fractured files

show that FTP time can be reduced to less than one hour with this

parallel method.

Conclusion

Several new physical effects are impacting EUV OPC and mask

synthesis flows. The impact of these effects on accuracy and TAT

of flows was evaluated, especially the large increase in data file sizes

for EUV mask synthesis and the risk this poses for meeting strict

modern mask synthesis flow TAT requirements. After review of

several options for improving the TAT and accuracy of individual

flow components and the entire fl ow, results show that EUV flows

can be optimized to meet stringent production TAT and accuracy

requirements of future nodes. ■

Acknowledgements

The authors would like to thank the following people for their helpful

work and support:

Hua Song, Lin Zhang, Jim Shiely, Robert Lugg, Yan Ping, Stephen

Jang, Lena Zavyalova, Lantian Wang, Kunal Taravade, Thomas

Schmoeller, Uli Klostermann of Synopsys

Sunghoon Jang, Junghoon Ser, Insung Kim, Young-Chang Kim,

Sooryong Lee of Samsung

Eric Hendrickx, Gian Lorusso of imec.

References

1. [1] J.Cobb, et al., “Investigation of EUV tapeout flow issues, requirementsand options for volume manufacturing,” Proc. of SPIE Advanced Lithog-raphy Vol. 7969-26, 2011.

2. [2] J. Cobb, et al., “Flare compensation in EUV lithography,” Proc. of theEUV Symposium, Antwerp, 2003.

3. [3] J. Yeo, “EUVL projection on Samsung’s device roadmap,” presentationat Sematech EUV Symposium, 2009.

4. [4] I. Kim et al., “Flare mitigation strategies in extreme ultraviolet lithogra-phy,” Microelectronic Eng. Vol. 85, Issues 5-6, May-June (2008).

5. [5] E. Van Setten, et al., “EUV mask stack optimization for enhanced im-aging performance,” Proc. of SPIE BACUS, vol. 7823, 2010.

6. [6] G. F. Lorusso, et al., “Extreme ultraviolet lithography at IMEC: Shad-owing compensation and flare mitigation strategy,” Vac. Sci. Technol. B25, 2127 (2007).

7. [7] M. Shiraishi, et al., “EUV mask stack optimization for enhanced imag-ing performance,” Presentation at MNC, 2010.

8. [8] J. Burns, et al., “EUV buried defect avoidance,” Proc. of SPIE BACUS,vol. 7823, 2010.

9. [9] S. Jang, et al., “Requirements and results of a full-field EUV OPC flow,”Proc. of SPIE Vol. 7271-46, 2009.

10. [10] L. Zavyalova, et al., “OPC flare and optical modeling requirementsfor EUV,” presentation at 2008 International workshop of EUV Lithog-raphy, May, 2008.

11. [11] International Technology Roadmap for Semiconductors (ITRS) road-map for EUV masks; http://www.itrs.net

Contact author:

Kevin Lucas, Corporate Applications Engineer, may be reached at

Synopsys, Inc., 1301 S. Mopac Expressway, Austin, TX, 78746; ph.:

512-372-7584; email [email protected].

Figure 3. Parallelized combined component flow for EUV. The flow utilizes massive parallelization of cells/templates of data that

have finished all previous component processing and cell context updating. Cells/templates completely finished by the previous compo-

nent can be passed in a pipeline for modification by the next flow component to start well before the previous component has complet-

ed the entire layout. [1] Used with permission of SPIE.

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM





http://www.itrs.net







Resist and HMDS

40 nm features

Resist and HMDS

32 nm features

AL412 and resist

40 nm features

AL412 and resist

32 nm features

Improving line roughnessby using EUV assist layers

RESISTS

EUV lithography is facing several chal-

lenges, including line roughness. The cause of line roughness is complex

and several approaches to prevent or smooth lines have been explored.

The individual approaches are compared and a dual approach of a

material and process solution is proposed.


As the semiconductor industry has maintained the pace set

by Moore’s law, it has driven development in all areas of

semiconductor manufacturing. This progress can easily be

tracked when looking at lithography development

over time. G-line exposure tools led to i-line scanners and

then to 248nm scanners. Achievements at these wavelengths,

in turn, drove research into ArF technology and then to

193nm immersion lithography. Currently, the industry is

focused on advancing EUV technology.

We have been developing materials for EUV lithog-

raphy for the past 5 years. Through this research, many

unique challenges facing EUV patterning were identified

as it moves closer to production. In particular, patterning

features smaller than 100nm poses an uncommon set

of challenges compared to previous lithography genera-

tions. Sub-100nm technology enters the quantum realm

in which most classical models break down. One reason

for the departure from traditional models is that at these

feature sizes, the sizes of the molecules that compose

the materials become important, along with geometric

changes such as surface area versus volume adjustments.

It is not surprising then that feature sizes of less than

30nm have suffered from irregularities in feature width

and line edge smoothness [1]. These irregularities are

commonly referred to as line width roughness and line

edge roughness, or LWR and LER, respectively.

The stochastic imperfections measured as LWR and

LER have a direct impact on the performance of a transistor.

Most material metrology is focused on LER, whereas LWR

has a larger effect on device performance. Research into

the on-off current fluctuations using 45nm devices has shown a

direct correlation of Ioff with LWR [2]. As feature sizes decrease,

it is expected that the impact of line roughness on device perfor-

mance will increase.

Research has shown that some of the causes

of LWR and LER are partly from the blur of the

pattern connected to secondary electron emission,

partly from the optical flare, partly from out-of-band

radiation, and largely from the acid diffusion that

occurs during the post-exposure step [3-5]. With

several root causes, a multifaceted solution is needed.

We have seen two logical approaches to managing roughness,

either preventing it or smoothing the lines after the pattern has

formed. Within these two approaches, several methods are being

explored, some of which are a combination of prevention and

smoothing. However, industry research has focused mostly on the

process of minimizing roughness before it forms. This solution

appears more attractive because it is easier to avoid or minimize

a problem, and usually less costly, than to troubleshoot it after the

issue has materialized.Carlton Washburn, Brewer Science, Inc., Rolla, MO USA

An example of smoother lines from using the E2Stack AL412 assist layer coated under the

photoresist. The assist layer “assists” the photoresist during the lithography patterning process to produce

smoother lines.


DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM












SiARC and underlayer can be individually

tuned to match a particular lithography

setup, minimizing substrate refl ectivity into

the resist as much as possible, typically below

0.5% or lower. When considering double

patterning, a tri-layer approach can yield

better combinations of refl ectivity control

for the second resist patterning step, where

the fi rst resist pattern now impacts and

contributes to the local optical environment.

Where SiARCs separate themselves from

BARCs is with the silicon content of their

polymer. Utilizing variations of resins, such

as siloxanes and silsequioxanes, the silicon

content of the polymer can be >40%, which

is nearly the same amount of silicon as

chemical-vapor deposited (CVD) SiO2 fi lms.

Polymers with silicon content >40% results

in a very hard etch mask compared to any

organic spin-on BARC and enables the use

of fl uorocarbon etches that would not be of

use with a BARC.

Modern SiARC materials off er much

more than refl ectivity control and better

etch resistance. Early SiARCs, like BARCs

before them, used high temperature post-

application bakes, but are now baked in

the 200-250°C range, to better complement

process fl ows. SiARCs can even incorporate

additives into their formulations to combat

resist poisoning, increase resist adhesion,

and reduce footing profi les – all giving a

lithographer more fl exibility when setting

up the process.

Th e spin-on silicon hard mask material is

packaged with spin-on organic hard masks

(underlayers) to make process development

easier and more tolerant of diff erent resists

or process conditions (Fig. 5).

It is evident that SiARCs, in combi-

nation with underlayers, are at the forefront

of leading edge lithography film stack

solutions because of the multitude of benefi ts

they impart. Today’s hyper-NA immersion

systems necessitate the use of very thin

resist coatings, and along with complex

double-patterning schemes, require a more

advanced anti-refl ectivity solution than

single or dual layer BARCs. Th e new SiARC

materials are satisfying these needs, encom-

passing the requirements of refl ectivity

control, planarization over topography, etch

resistance and selectivity, along with resist

adhesion and poisoning prevention.



One approach to minimizing roughness during the lithography step is to use

non-chemically amplifi ed photoresists. Because much of the roughness comes from acid

diff usion, it was thought that eliminating the amplifi cation would decrease the roughness.

Th is concept has been explored with similar conclusions. By using a non-chemically

amplifi ed photoresist, the LER was reduced. However, a large increase in dose was needed

to reach the target CD size [6,7].

Our approach to minimizing line roughness is to assist the photoresist during the

lithography step. Th is method improves line roughness by using an assist layer (AL)

under the photoresist. Th e Figure shows top-down SEM images of a process using HMDS

with photoresist, and the same photoresist with 40nm of E2Stack AL412 assist layer

material. A clear improvement in performance can be seen when the assist layer is used.

Researchers at imec have confi rmed the benefi ts of this assist layer using a 20nm fi lm

thickness, with 3-sigma LER values in the range of 3.5 to 4nm [8].

Th e improvement seen by using our assist layer is apparent, but the LER must be further

improved to meet the ITRS target of 2.5nm for 2012. Smoothing techniques involve ion

milling, ablation, reactive ion etching, and resist refl ow methods. Ion milling has shown

solid improvement [9]. Resist refl ow processes have also shown promise [10]. Smoothing

processes, however, have still not delivered a solid solution.

Because no single method is delivering the needed reduction in LER, combining the

benefi ts of an assist layer material during lithography and a smoothing process aft er lithog-

raphy might be the dual-prong solution that is needed. By using separate steps, additional

processing conditions will present options for optimization over a single step. One way this

solution could work is that the assist layer would mitigate roughness during the lithog-

raphy step by improving absorbance of EUV photons and secondary electrons, while post-

imaging processes would burnish the lines to the needed smoothness [11]. Th e LER and LWR

targets would then be possible, while diff erent processing options would be available to ease

integration and process tuning. ■

Acknowledgment

E2Stack is a registered trademark of Brewer Science.

References

1. C. Gustin, L. A. H. Leunissen, et al., ”Impact of line width roughness on the matching performances of next-generation devices,” Proc. Int Symp Dry Process, 6, pp. 177-178 (2006).

2. C. Gustin, L. A. H. Leunissen, et al., “Impact of line width roughness on the matching performances of next-generation devices,” Th in Solid Films, 516, pp. 3690–3696 (2008).

3. R. L. Brainard, J. Cobb, J, C.A. Cutler, “Current status of EUV photoresists,” Jour. of photopolymer science and tech., 16(3), pp. 401-410 (2003).

4. H. Oizumi, et al., “Patterning capability of new molecular resist in EUV lithography,” Microelectronic Eng., 84, pp. 1049–1053 (2007).

5. C.C. Higgins, et al., (2011), “Coeffi cient of thermal expansion (CTE) in EUV lithography: LER and adhe-sion improvement,” SPIE: Advances in Resist Materials and Processing Technology XXVIII, 7972 (2011).

6. R. Gronheida, et al., “Characterization of extreme ultraviolet resists with interference lithography,”Microelectronic Eng., 83, pp. 1103–1106 (2006).

7. A. Yu, et al., “Patterning of tailored polycarbonate based non-chemically amplifi ed resists using ex-treme ultraviolet lithography,” Macromolecular Rapid Comm., 31, pp. 1449-1455 (2010).

8. F.V. Roey, et al., imec: internal communication, May 5, 2011. 9. C.R.M. Struck, et al., “Grazing incidence ion beams for reducing LER,” SPIE: Lithography Asia, 7140

(2008).10. I.W. Cho, et al., “Reduction of line width and edge roughness by resist refl ow process for extreme ul-

tra-violet lightography,” SPIE: Advances in Resist Materials and Proc. Tech. XXVI, 7273 (2009).11. D.J. Guerrero, et al. “Organic underlayers for EUV lithography,” Jour. of Photopolymer Science and

Tech., 21, pp. 451-455 (2008).

Biography

Carlton Washburn received his bachelor of science in physics and mechanical engi-

neering from Illinois College and the U. of Missouri-Rolla, respectively. Carlton is a se-

nior applications engineer at Brewer Science, 2401 Brewer Drive, Rolla, MO 66401 USA;

ph.: 573-364-0300; email [email protected].

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











Substrate

JSR ArFi photoresist JSR ArFi photoresistJSR spin-on silicon HM

JSR spin-on organic HM

EXECUTIVE OFFICES

PennWell, 98 Spit Brook Rd, Nashua, NH 03062-5737

Tel: 603/891-0123

ADVERTISING

Marcella Hanson—Ad Traffic Manager

Rachael Caron—Marketing Communications Manager

ADVERTISING SALES OFFICES

Group PublisherDiane Lieberman, 98 Spit Brook Rd, Nashua, NH 03062-5737;

Tel: 603/891-9441; Fax: 603/891-9328;

e-mail: [email protected]

Regional Sales ManagerEast Coast US and Eastern Canada, MidwestKaren Watkins, 98 Spit Brook Rd. Nashua, NH 03062-5737

Tel: 603/891-9118; Fax: 603/891-9328;


Regional Sales ManagerWest Coast US, Western CanadaLisa Zimmerer, 190 Cecil Place, Costa Mesa, CA 92627

Tel: 949/515-0552; Fax: 949/515-0553;


List RentalKelli Berry, 1421 South Sheridan Rd., Tulsa, OK 74112;

Tel: 918/831-9782; Fax: 918/831-9758;


Austria, Germany, Liechtenstein, Russia,N. Switzerland, Eastern EuropeHolger Gerisch, Hauptstrasse 16,

D-82402 Seeshaupt, Germany;

Tel: 49/8801-302430; Fax: 49/8801-913220;


France, Netherlands, Belgium, W. Switzerland,Spain, Greece, PortugalLuis Matutano, Adecome+, 1, rue Jean Carasso,

F-95870 Bezons, France

Tel: 33/1-30 76 55 43; Fax: 33/1-30 76 55 47;


United Kingdom & ScandinaviaTony Hill, PennWell Publishing UK Ltd., Warlies Park House,

Horseshoe Hill, Hill, Upshire, Essex, U.K. EN9 3SR

Tel / Fax: 44-1442-239547


IsraelDan Aronovic, Allstar Media Inc.,

3/1 Hatavas St., Kadima, 60920, Israel

Tel / Fax: 972/9-899-5813


JapanManami Konishi, Masaki Mori, ICS Convention Design, Inc.,

Chiyoda Bldg., Sarugaku-cho 1-5-18,

Chiyoda-ku, Tokyo 101-8449, Japan

Tel: 3-3219-3641; Fax: 3-3219-3628;


[email protected]

TaiwanDiana Wei

Arco InfoComm, 4F-1, #5 Sec. 1

Pa-Te Rd. Taipei, Taiwan R.O.C. 100

Tel: 866/2-2396-5128 Ext. 270


China, Hong KongAdonis Mak, ACT International, Unit B, 13/F, Por Yen Building,

478 Castle Peak Road, Cheung Sha Wan, Kowloon, Hong Kong

Tel: 852/2-838-6298; Fax: 852/2-838-2766;


Aug/Sept 2011, Volume54, Number 8•SolidState Technology©2011 (ISSN

0038-111X) Periodicals postage paid at Tulsa, OK 74112, & additional mail-

ing offices. Published 10x per year by PennWell Corp., 1421 S. Sheridan Rd.,

Tulsa, OK 74112.Subscriptions:Domestic: one year: $258.00, two years:

$413.00; one year Canada/Mexico: $360.00, two years: $573.00; one-year

international airmail: $434.00, two years: $691.00; Single copy price:

$15.00 in the US, and $20.00 elsewhere. Single copy rate for the spe-

cial March issue that contains the Resource Guide Supplement:

$139.00 in the U.S; $155.00 in Canada; $176.00 international air-

mail. Digital distribution: $130.00. You will continue to receive your

subscription free of charge. This fee is only for air mail delivery. Ad-

dress correspondence regarding subscriptions (including change of

address) to: Solid State Technology, PO Box 3425, Northbrook, IL

60065-9595, [email protected], ph 847-559-7500 (8 am – 5 pm, CST).

PRINTED IN THE USA. GST NO. 126813153. Publication Mail Agreement

No. 40052420. POSTMASTER: Send address changes to Solid State

Technology, PO Box 3425, Northbrook, IL 60065-9595. Return Undeliv-

erable Canadian Addresses to: P.O. Box 122, Niagara Falls, ON L2E 6S4.The Advertiser’s Index is published as a service. The publisher does not assume any liability for errors or omissions.

A D I N D E XAdvertiser Pg Advertiser Pg

BUSCH USA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

LED Japan Conference . . . . . . . . . . . . . . . . . . . . . . . .17

Levitronix GmbH . . . . . . . . . . . . . . . . . . . . . . . . . . . C4

Materion Corporation . . . . . . . . . . . . . . . . . . . . . . . . 3

Plasmatic Systems, Inc . . . . . . . . . . . . . . . . . . . . . . . . 9

Rofin-Baasel, Inc.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Solid State Equipment Corp. . . . . . . . . . . . . . . . . . . C2

Terra Universal Inc.. . . . . . . . . . . . . . . . . . . . . . . . . . 10

The Confab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C3

Vistec Electron Beam GmbH . . . . . . . . . . . . . . . . . . . 7


Figure 5. A trilayer stack of photoresist, SiARC, and organic underlayer. These stacks are utilized to improve reflectivity control,

provide planarization over topography, as well as provide etch selectivity to the underlying substrate.

Conclusion

The chemistry of lithography is changing at a rapid rate to keep up with device scaling

demands. While EUV is not yet ready for high volume manufacturing, a multitude of

materials-based approaches have arisen to fill the exposure tool gap. Using immersion lithog-

raphy to meet today’s advanced technology node requirements can only go so far. Double-

patterning, spin-on silicon hard masks, and topcoat-less resists are taking the industry the

rest of the way. In a world where lithographic tools are standing (relatively) still, materials

are leading the charge to meet and beat Moore’s Law. And as always, the next generation of

device requirements is already upon us, but materials development stands ready to answer

the challenge. ■

References

1. S. J. Holmes, C. Tang, M.E. Colburn, M. Slezak, B. Osborn, N. Fender, et al., “Optimization of pitch-split double-patterning photoresist for applications at 16nm node,” Proc. of SPIE-The InternationalSociety for Optical Engineering 2011, (Advances in Resist Technology and Processing XXVIII).

2. B. P. Osborn, K. Goto, V. Pham, M. Slezak, “Non-topcoat immersion resist advancements (poster),”LithoVision 2010 Nikon Precision Symposium, San Jose, CA, February 21st, 2010.

Biographies

Mark Slezak received his bachelor degree from California Polytechnic State Univer-

sity San Luis Obispo in Engineering and is the Director of Lithography Technology at

JSR Micro, 1280 N. Mathilda Ave., Sunnyvale, CA 94089 USA; ph.: 408-543-8800; email

[email protected]

Brian Osborn received his PhD and undergraduate from the University of Texas at Austin

in Chemistry and is the Lithography Technology Supervisor at JSR Micro, 1280 N. Mathilda

Ave., Sunnyvale, CA 94089 USA; ph.: 408-543-8800; email [email protected]

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM












INDUSTRY FORUM

F or many years, IDMs, OEMs and

materials suppliers in the semiconductor

industry have faced the increasingly

diffi cult challenges of device scaling by

sharing knowledge with one another and

combining their respective skill sets in a

collaborative environment. While these

collaborations oft en bring their own challenges from a

commercial and cultural standpoint, there is no doubt

that technical benefi ts have helped the industry continue

down the performance and cost path laid out several

decades ago by Gordon Moore. Well-

known examples of collaborative eff orts

that have delivered valuable solutions

to the industry abound in almost every

module application, especially those of

lithography, CMP, deposition and plating.

Consortia, such as SEMATECH, imec, etc.,

have also proven to be eff ective models.

Th e LED industry, although decades old,

has only seen explosive growth over the past

few years with increasing demand for display

backlighting and solid-state lighting (SSL).

To support the performance and cost-reduction roadmap

dictated by Haitz’s Law (LED’s version of Moore’s Law), it’s

likely that the industry will need to incorporate many of the

same methodologies utilized by its more mature brethren.

In conversations with key market players, it is clear that

while some of the best known methods of the semicon-

ductor industry have found their way into the LED industry,

numerous opportunities for improvement still exist. In fact,

many industry observers have expressed that they believe

the most accessible cost-reduction opportunities have

already been harvested, such as migrating to larger wafer

sizes, maximizing use of commodity materials, etc., and that

further improvements will take signifi cantly more eff ort.

If we think of any collaborative eff ort as a group of

somewhat overlapping sets of competencies – a Venn

diagram if you will – then the areas of overlap should

highlight the best opportunities for collaboration to

realize signifi cant technological breakthroughs. For

example, equipment manufacturers have a set of capabil-

ities, let’s call them “levers,” which they can utilize to adjust

and optimize hardware performance. Th ese may include

fl ow rates, chamber design, materials of construction,

temperature control and many others. Similarly, materials

suppliers have their own unique set of levers that they can

adjust to modify and optimize their materials, including

stoichiometry, viscosity, reactivity and many others. If

the respective Venn diagrams for these levers can be

combined such that the collaboration exploits the advan-

tages of the overlapping capabilities, optimized solutions

can be delivered to end users. Of course, the end-user

IDMs typically bring their own key levers, most critically

in the area of process integration.

As a strong proponent of collaborative engagements,

ATMI oft en refers to delivering “process

efficiency” to customers. While these

activities may include reducing price over

time as scale and other factors allow, more

oft en than not they focus on joint devel-

opment activities with a device and/or an

equipment maker to drive process improve-

ments that lead to higher yields, increased

throughput, and/or less non-value-added

steps. A promising example of an oppor-

tunity for innovation through collaboration

in the LED industry is around epitaxial

deposition processes.

Th e U.S. Department of Energy, in a recent report on

the SSL industry, highlighted MOCVD processes as a key

area for improvement. Th e yield and throughput of the

MOCVD process has a signifi cant impact on fi nal LED

device cost. Methodologies utilized by the semiconductor

industry to improve their process effi ciency, many origi-

nally driven by collaborative eff orts, include improve-

ments in stoichiometric control of reactants, improved

fl ux stability, increased material utilization, and reduced

downtime through the use of bulk material delivery.

Solving diffi cult technology challenges is oft en best,

and sometimes only, achieved through concerted eff orts

by partners who combine their respective capabilities to

deliver more value than the sum of the parts. As the LED

industry matures, it seems exceedingly likely that many

of the future breakthroughs in performance and cost will

come through collaborative engagements. ■

Jeff Desroches is Business Development Manager at

ATMI, Inc., 2151 East Broadway Road, Suite 101, Tempe,

AZ 85205, 480-736-7600, [email protected]

Leveraging collaborations to drive down the LED cost curve

Jeff Desroches,ATMI, Inc., Tempe, AZ USA

The most

accessible

cost-reduction

opportunities

have already

been harvested

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM











BUILD ALLIANCES

TO CAPTURE YOUR

SHARE OF THE

$94 BILLION MARKET

Hear a World-Class Conference Program

Built for the Benefit of Device

Manufacturers and Their Global Suppliers

Meet Senior-Level Executives

from the Semiconductor

Supplier and Manufacturing Community

Participate in Private Face-to Face

Boardroom Meetings with Guaranteed ROI

New Venue in 2012!

June 3-6, 2012

ENCORE AT THE WYNN

LAS VEGAS, NEVADA

2012

www.theconfab.com

THE POWERof ONE EVENT

“In this market it’s critical to be aligned with theindustry leaders and The ConFab provides theunique opportunity to meet them face-to-face

and discuss the critical issues.”–Pall Microelectronics

“The one-on-one meetings are great. We plan,prepare and meet with industry leaders fromvarious segments and in just a few short days,

we cover the globe.”–Novellus

FOR MORE INFORMATION ON

SPONSORSHIP OPPORTUNITIES,

Contact Jo-Ann Pellegrini, Sales Manager,

at 650-946-3169 or email: [email protected].

Not a supplier? If you are a senior-level decision maker

from a semiconductor manufacturing or fabless company,

you may qualify to attend The ConFab as our complimentary

VIP guest. Contact Luba Hrynyk at [email protected]

for your invitation to attend this conference and

high-level networking event.

Flagship Media Sponsors: Own Owned and Produced by:

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM




http://www.theconfab.com







____________________

_______________

DC

qqM

Mq

qM

MqM


DC

qqM

Mq

qM

MqM












Date post:	07-Oct-2020
Category:	Documents
Upload:	others
View:	10 times
Download:	0 times

C Previous Page | Contents | Zoom in | Zoom out | Refer a...

Documents