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User’s View of a Computer

The user sees software, speed, storage capacity,and peripheral device functionality.

Real Course Goal: No Mysteries

The goal is to treat the design and architecture of computer systems at a level of detail that leaves “no mysteries” in computer systems design.

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Summary of Digital Logic

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Units and Conventions

Term

k (kilo-)

M (mega-)

G (giga-)

T (tera-)

10 3

10 6

10 9

10 12

2 10 = 1024

2 20 = 1,048,576

2 30 = 1,073,741,824

2 40 = 1,099,511,627,776

Normal Usage As a power of 2

1 MiB = 220 bytes1 GiB = 230 bytes

P (peta 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏), E (exa 𝟏𝟏𝟏𝟏𝟏𝟏𝟖𝟖), Z (zetta 𝟏𝟏𝟏𝟏𝟐𝟐𝟏𝟏), Y (yotta 𝟏𝟏𝟏𝟏𝟐𝟐𝟐𝟐)

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Units and Conventions

Term Usage

m (milli-)µ (micro-)

n (nano-)p (pico-)

10 -3

10 -6

10 -9

10 -12

Units: Bit (b), Byte (B), Nibble, Word (w), Double Word, Long Word

Second (s), Hertz (Hz)

d (deci 10−1), c (centi 10−𝟐𝟐),

f (femto 𝟏𝟏𝟏𝟏−𝟏𝟏𝟏𝟏), a (atto 𝟏𝟏𝟏𝟏−𝟏𝟏𝟖𝟖), z (zepto 𝟏𝟏𝟏𝟏−𝟐𝟐𝟏𝟏), y (yocto 𝟏𝟏𝟏𝟏−𝟐𝟐𝟐𝟐)

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Definitions

Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder.

Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit.

Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller.

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Combinational Logic Unit

Translates a set of inputs into a set of outputs according to one or more mapping functions.

The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change.

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Truth Tables

Developed in 1854 by George Boole Further developed by Claude Shannon (Bell Labs)

Consider a room with two light switches. Claude Shannon (1916-2001)The father of Information Theory

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All Possible Functions of Two Binary Variables

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Logic Gates and Their Symbols

Note the use of the “inversion bubble.”

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Logic symbols for Boolean functions

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Variations of Basic Logic Gate Symbols

A Negated Input

Complementary Outputs

3 inputs

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Basic Properties of Boolean Algebra

Postulates

Theorems

A, B, etc. are Literals; 0 and 1 are constants.

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Principle of Duality

The dual of a Boolean function is achieved by changing AND to OR OR to AND constant 1s to 0s constant 0s to 1s

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Positive vs. Negative Logic

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Positive and Negative Logic (Cont’d.)

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꽃 김춘수

내가그의이름을불러주기전에는

그는다만

하나의몸짓에지나지않았다.내가그의이름을불러주었을때

그는나에게로와서

꽃이되었다. 내가그의이름을불러준것처럼

나의이빛깔과향기(香氣)에알맞은누가나의이름을불러다오. 그에게로가서나도

그의꽃이되고싶다. 우리들은모두

무엇이되고싶다. 너는나에게나는너에게

잊혀지지않는하나의눈짓이되고싶다.

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DeMorgan’s Theorem

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DeMorgan’s Theorem

The complement of a Boolean function is obtained by changing Literal A to A’

constant 1s to 0s constant 0s to 1s

AND to OR OR to AND

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Sum-of-Products (SOP) Form

transform the function into a two-level AND-OR equation implement the function with an arrangement of logic gates from the

set {AND, OR, NOT}

Truth Table for The Majority Function

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SOP Form of the Majority Gate

The SOP form for the 3-input majority gate is:

M = ABC + ABC + ABC + ABC = m3 + m5 +m6 +m7 = Σ (3, 5, 6, 7) Each of the 2n terms is called a minterm, running from 0 to 2n - 1

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2-Level AND-OR Circuit for the Majority Function

F = ABC + ABC + ABC + ABC

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2-Level OR-AND Circuit for the Majority Function

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Programmable Logic Arrays (PLAs)

A PLA is a customizable AND matrix followed by a customizable OR matrix:

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Using a PLA to Implement the Majority Function

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Using PLAs to Implement an Adder

Figs A.34-36

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PLA Realization

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Multi-Bit Ripple-Carry Adder

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Multiplexer

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Implementing the Majority Function with an 8-1 Mux

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More Efficiency: Using a 4-1 Mux to Implement a function.

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Demultiplexer (DEMUX)

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Demultiplexer is a Decoder with an Enable Input

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2-4 Decoder

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Using a Decoder to Implement the Majority Function

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Priority Encoder

Ai has a higher priority than Ai+1

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Sequential Logic

The combinational logic circuits have no memory. The outputs always follow the inputs.

There is a need for circuits with a memory, which behave differently depending upon their previous state.

These are referred to as finite state machines, because they can have at most a finite number of states.

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Classical Model of a Finite State Machine (FSM)

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NOR Gate with a Lumped Delay

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S-R (Set-Reset) Latch

The S-R latch is an active high (positive logic) device.

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Converting NOR SR to NAND SR

Active HighNOR Impl.

Push Bubbles(DeMorgan’s)

RearrangeBubbles

Convertfrom Bubblesto Active LowSignal Names

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A Circuit with a Hazard

It is desirable to be able to “turn off”the latch so it does not respond tosuch hazards.

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Clocked S-R latch

The clock signal, CLK, turns on the inputs to the flip-flop.

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Clocked D (Data) Latch

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Master-Slave D Flip-Flop

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Negative Edge-Triggered D Flip-Flop

When the clock is high, the two input latches output 0, so the Main latch remains in its previous state, regardless of changes in D.

When the clock goes high-low, values in the two input latches will affect the state of the Main latch.

While the clock is low, D cannot affect the Main latch.

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Register and Register File

Register : Multiple flip-flops that are accessed at the same time, being

regarded as a single unit.

Register File : A set of registers that are grouped together. Only a few of them can be accessed at a time depending on

the number of ports supported. For example, 2 read ports and 1 write port.

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Basic J-K Latch

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Master-Slave J-K Flip-Flop

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T (Toggle) Flip-Flop

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Mealy vs. Moore Machines

Mealy Model: Outputs are functions of Inputs and Present State.

• Both are equally powerful.

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Tri-state Buffers

There is a third state: High impedance. This means the gate output is essentially disconnected from the circuit.

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Register with Tri-state Output

Gate-Level View

Chip-Level View

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Left-Right Shift Register with Parallel Read and Write

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Modulo-8 (3-bit) Ripple Counter

Note the use of T flip-flops. They are used to toggle the input of the next flip-flop when its output is 1.