qq SAB 8xC166SAB 8xC166qq C167xC167xqq C165C165qq C163C163qq C164xC164xqq C161xC161x
SAB-C167CRSAB-C167CR
XRAMXRAM1KByte1KByte
XRAMXRAM1KByte1KByteRAMRAM
1KByte1KByte
RAMRAM1KByte1KByte
PWMPWM
ADCADC
CANCAN
BUS-BUS-CONTROLCONTROL
INTERRUPTINTERRUPTUNITUNIT
CAPCOMCAPCOM1+ 21+ 2
SSCSSC
USARTUSARTGPTGPT1+ 21+ 2
IR+ PEC-IR+ PEC-CONTROLCONTROL
ROMROM
WDTWDT
CORECORE
The Reference ClassThe Reference Class1
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 2Microcontrollers
WDTOSC.PEC
CPUROM /
RAM
PORTS
CAPCOM
ADCBus
Ext..
Processor -System
Interrupt-System
USART GPTs
Peripheral-System
Flash
Control
X-Bus
Sync Communication PWMPeripheral.
C166 FamilyThe Three Subsystems
The Reference ClassThe Reference Class1
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 3Microcontrollers
Four Bus Modular SystemX BusX Bus Modules Modules
RAM1k
RAM1k
NewModules
Timers USART SSC
Ports NewModules
WDT
ADC
CAPCOM
XRAMSSP
NewModules
CAN
I²C
NewModules
ROM 8K
ROM 32K
Flash32K
Flash128K
NewModules
OTP 64K
Flash64K
CoreCore
32 b
it32
bit
16 - b i t16 - b i t
2x16
bit
2x16
bit
16 - b i t16 - b i t
BasicBasic Library Modules Library Modules
The Reference ClassThe Reference Class1
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 4Microcontrollers
C166-C166-CoreCore
167CR
PLL(input: 5MHz)OSC(output: 20MHz)
2KB XRAM
Por
t 6P
ort 0
Por
t 4
Port 1 Port 5 Port 3 Port 2 Port 8 Port 7
CPU
Dua
l Por
t
RAM
2 KByte
Interrupt ControllerWatchdog
PeripheralData
ExternalInstr./Data
Instr./Data
MultiFunktional
10-BitADC
USART
ASCBRG BRG
SSC
Sync.Channel
(SPI)
GPT1
T3
T4
GPT2
T2
T5
T6
CAPCOM1, 2
32Channels
Tim
er7
Tim
er1
Tim
er0
Tim
er8
PWM ModulePT 1
PT 2
PT 3
PT 4
16 16 16 16 8 8
16
8
8
16
16
16
1632
PEC
Interrupt Bus
Data
Data
128KByteROM/
EPRONFLASH
XB
US
(16
-bit
NO
N M
UX
Dat
a /
Add
ress
es)
External Bus,XBUS Control,5 * CS Logic
CAN2.0 B active
16 Channels
36 ext. IR
XTAL
3OverviewOverview - - C167CR Block Diagram
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 5Microcontrollers
OnOn-Chip-Chip(EP)ROM(EP)ROM
SP
STK OV
STK UV
Block DiagramROM / RAM interaction
CPUCPU
MDL
MDH
Mul./Div.-HW
Bit-Mask Gen.
ALUALU16-bit
Barrel-Shifter
Code Seg.Ptr
Data PagePointer
OnOn-Chip-ChipStaticStaticRAMRAM
R15
R0
STK OV
STK UV
General
R15
R0
Purpose
Registers
Context Ptr.
4-StagePipeline
Exec. Unit
Instr. Ptr.
Instr. Reg.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
PSWSYSCONBUSCON 0
32
16
16
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
4CPUCPU
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 6Microcontrollers
qq Up to 16Up to 16 GPRs GPRs = 1 Register = 1 Register bank bankConsisting of maxConsisting of max..-- 8 Word-Registers8 Word-Registers-- 8 Word-Registers8 Word-Registers with lower and higher with lower and higher Byte Byte access access
qq The GPRs are bitThe GPRs are bit--addressableaddressableqq AnyAny Register Register bank can be freely allocated bank can be freely allocated in in internal internal RAM RAMqq The location of the activeThe location of the active Register Register bank is determined by bank is determined by
Context PointerContext Pointer (CP) (CP)qq CPCP can be easily switched can be easily switched, to, to select another select another Register Register bank bankqq SWTC (SWTC (one instruction cycleone instruction cycle))
General Purpose Register(GPR)
4CPUCPU
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 7Microcontrollers
0F600
R8R8R9R9
R10R10R11R11R12R12R13R13R14R14R15R15
RH0RH1RH2RH3RH4RH5RH6RH7
RL0RL1RL2RL3RL4RL5RL6RL7
Context pointerContext pointer
0FDFE
2KBytesinternal RAM
R0R0R1R1R2R2R3R3R4R4R5R5R6R6R7R7
STKOV
STKUV
R15R15
R0R0
0FC00
Stackpointer UnderflowStackpointer
Stackpointer Overflow
STKUV
STKOV
Block DiagramROM / RAM interaction with 2K RAM
4CPUCPU
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 8Microcontrollers
Four Stage Instruction Pipelineat 20 MHz
4CPUCPU
qq Effective execution time of most instructionEffective execution time of most instruction in 100 in 100 ns nsqq Three word prefetch queueThree word prefetch queue ( (buscontrollerbuscontroller) to) to support support
only one additional machine cycle is normally requiredonly one additional machine cycle is normally required to tofetch target instructionfetch target instruction
qq JumpJump Cache Cache-- For loop processing no additional machine cycle is requiredFor loop processing no additional machine cycle is required
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 9Microcontrollers
Processing of each instruction is partitioned in 4 stages
Fetch
Decode
Execute
Write Back
1. Instr. 2. Instr. 3. Instr. 4. Instr.
Time 1 Machine Cycle = 100 ns at 20 MHz CPU clock
Four Stage Instruction Pipelineat 20 MHz
4CPUCPU
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 10Microcontrollers
Instruction Set at 20 MHz
qq Data manipulationData manipulation-- Arithmetic and boolean instruction inclArithmetic and boolean instruction incl. fast. fast multiply multiply//dividedividein 0.5/1.0usin 0.5/1.0us
--Multiple (up to 15)Multiple (up to 15) bit shift and rotate bit shift and rotate in 100 in 100 ns ns-- Bit toBit to bit manipulation bit manipulation in in internal internal RAM RAM and SFR’s and SFR’s
qq Data movementData movement--MOVMOV instructions with instructions with all all important addressing modes important addressing modes-- Byte toByte to word conversion word conversion-- SystemSystem stack stack (PUSH, POP) (PUSH, POP) with over with over-- and underflow and underflow
controlcontrol--User stackUser stack (MOV (MOV with auto increment and decrement with auto increment and decrement))
qq ......
4CPUCPU
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 11Microcontrollers
qq Program manipulationProgram manipulation-- Jumps and callsJumps and calls / / conditional jumps under conditional jumps under 16 different 16 differentconditionsconditions
-- Software-Software- and hardware and hardware--TrapsTraps-- FastFast context switching context switching in 100 in 100 ns ns
qq Special instructions forSpecial instructions for-- PowerPower consumption reduction and system Control consumption reduction and system Control--NonNon--interruptable instruction sequencesinterruptable instruction sequences-- Extended addressing accessExtended addressing access
...Instruction Set at 20 MHz
4CPUCPU
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 12Microcontrollers
Address Space...
qq Complete address spaceComplete address space-- “von Neumann”“von Neumann” architecture with architecture with multiple multiple internal bus internal busstructurestructure to to avoid bus bottlenecks avoid bus bottlenecks
-- 64KByte64KByte non non--segmented address spacesegmented address space-- up to 16 MBytesup to 16 MBytes-- segmented address spacesegmented address space: 64KB: 64KB code segments and code segments and 16K 16K
data pagesdata pages
qq Internal address spaceInternal address space-- up to 128 KBytes ROM /up to 128 KBytes ROM / Flash Flash-EPROM-EPROM--maxmax 4 KByte 4 KByte SFR's SFR's
qq FlexibleFlexible ext ext.. bus configurations bus configurations to to simplify system simplify systemintegrationintegration-- up to 24-up to 24-bit Addressbit Address / 8- / 8-bit Databit Data (MUX (MUX and and NMUX) NMUX)-- up to 24-up to 24-bit Addressbit Address / 16- / 16-bit Databit Data (MUX (MUX and and NMUX) NMUX)-- Five completely independent configuration registersFive completely independent configuration registers-- Five programmable chip selects and programmable busFive programmable chip selects and programmable bus
control signalcontrol signal to to save external glue save external glue--logiclogic-- ProgrammableProgrammable HOLD/HOLDA/BREQ HOLD/HOLDA/BREQ bus arbitration bus arbitration
function for multifunction for multi--master operationsmaster operations
...Address Space
MemoryMemory5
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 14Microcontrollers
Bit Addressable Space
Segment 0Segment 0 includes Internal Memory includes Internal Memory
512 BytesSFR’s
InternalRAM
1K
1KInternalRAM
ExternalMemory
Internal ROM /Flash E²PROM
(mappable to Seg. 1)
512 BytesExt. SFR’s
00000
0E800
08000
0FE00
0FA00
0F200
100007 0
128K
0.5K
0.5K
Reserved
up to 16 Mup to 16 M BytesBytesCode Segments Data Pages
0
1
2
3
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
InternalROM/
FLASH
10000
20000
30000
3FFFF
Internal and externalMemory Map - C167CR
MemoryMemory
0F000
X-Bus Peripheral
Full - CANFull - CAN
0F600Reserved
5
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 15Microcontrollers
Code and Data Addressing via Segmentationand Paging on 16 Mbyte address range
MemoryMemory
15
Data addressing with Data Page Pointer (DPP) Code addressing with Code Segment Pointer
D P P 0 = 0 0D P P 1 = 0 1D P P 2 = 1 0D P P 3 = 1 1
Data Addressing viaData Page Pointer (DPPx)
MemoryMemory5
DPP
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 17Microcontrollers
Data Addressing via Extended Mode
Examples: Override Segment Number
EXTS RN,#data2 ;data2:No. of instructionsMOV [RM],Ri ;to be used for Ext.Addr.Mode
EXTP RN, #data2MOV [RM], Ri
RN RM RN RM
Physical address, where the contents of Ri is moved to Physical address, where the contents of Ri is moved to
15 0 0 0 015 1515
0 0 0 013
A13 A0A14A23A0A15A16A23
9157
Override Page Number
qq Overrides standardOverrides standard DPP DPP addressing scheme addressing scheme to to ease large ease large(up to 32-(up to 32-bitbit)) address calculation address calculation-- SegmentSegment or or Page Page override by override by an an immediate value immediate value-- SegmentSegment and and Page Page override by override by a Register a Register contents contents
MemoryMemory5
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 18Microcontrollers
qq Interrupt ControllerInterrupt Controller-- Extremely short interrupt response time ofExtremely short interrupt response time of minimal 250ns minimal 250nstypicaltypical: 400ns: 400ns
-- InterruptInterrupt execution execution in in small time segments small time segments-- Ensures highestEnsures highest real- real-time performancetime performance--Comprehensive prioritization schemeComprehensive prioritization scheme
-- Easy scheduling of complexEasy scheduling of complex real- real-time systems bytime systems byusingusing up to 64 up to 64 priority levels priority levels (4 (4 groups within groups within 16 16levelslevels))--NonNon--maskable interrupt inputmaskable interrupt input (NMI) (NMI)
--Hardware-Hardware-Traps on runtime errors andTraps on runtime errors and Software- Software-TrapsTrapsqq ......
Interrupt SystemInterrupt System
Overview at 20MHz...
8
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 19Microcontrollers
qq CPUCPU independent interrupt independent interrupt--serviceservice via viaPeripheral EventsPeripheral Events Controller (PEC) Controller (PEC)--OffOff--loads theloads the CPU CPU from from simple simple but frequent interrupt but frequent interrupt--
servicesservices-- Interrupt-Interrupt-drivendriven “DMA- “DMA-likelike”” data transfer data transfer to to any location any location in in
segmentsegment 0, 0, without task switch of the without task switch of the CPU CPU--Makes peripheral data transfers Independent of runningMakes peripheral data transfers Independent of running
Interrupt Control Register of the appropriate peripheralINTR Service:
Save PSW, CSP, IP
Set new priorityin PSW.
Set CSP, IPaccording toperipheral vector or Trap no.
PECService
* External Interrupts are possible, e.g. instead of the Capture Input
36 ext. Interrupts(+ NMI) including 8 which are sampled every 50 ns55 Peripheral Interrupts
4 Groups
Group Check
ClearINTR Flag
8Interrupt SystemInterrupt System
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 22Microcontrollers
Interrupt has passed priority and group check
Interrupt priority < 14Interrupt priority 14 or 15and Data Counter > 0
Interrupt service PEC service
PEC
8 PECChannel
Data Counter
SRC PointerDEST Pointer
Contr. Reg.
IR request if Data Counter = 0
MemoryMemory Segment 0 Segment 0
0FFFF
00000
Byte orWordTransfer
INTR Service:
Save PSW,CSP, IP
Set new priorityin PSW.
Set CSP, IPaccording toPeripheralvector orTrap No.
IR request if Data Counter = 0priority & groupcheck
Peripheral Event Controller (PEC)
8Interrupt SystemInterrupt System
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 23Microcontrollers
qq 2 General2 General Purpose Timer units Purpose Timer units (GPT1 & GPT2) (GPT1 & GPT2)-- 55 Timers Timers (200/400ns) (200/400ns) with enhanced with enhanced Input/Output, Input/Output, Reload Reloadand Capture functions and complex concatenationand Capture functions and complex concatenationcapabilitiescapabilities
qq 22 Capture Capture//Compare unitsCompare units (CAPCOM1 & 2) (CAPCOM1 & 2)-- 44 Timers Timers (400ns) (400ns) with Reload register and with Reload register and 32 32 independent independent16-16-bit Capturebit Capture//Compare channels programmableCompare channels programmable to 6 to 6modes of operationmodes of operation
qq 4 high4 high resolution resolution PWM PWM channels channels-- each with independent timeeach with independent time--base ofbase of up to 50ns up to 50ns resolution resolutionand programmable operation modesand programmable operation modes ( (edgeedge--alignedaligned,, center center--alignedaligned,, burst and single burst and single--shot modeshot mode))
qq ......
Peripherals Set of theC167...
9PeripheralsPeripherals
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 24Microcontrollers
qq IndependentIndependent USART USART--maxmax 625 625 KBaud asynchronous and max KBaud asynchronous and max 2.5 2.5 Mbit Mbit/sec/secsynchronous data transfersynchronous data transfer
qq FastFast Serial Synchronous Communication interface Serial Synchronous Communication interface (SSC) (SSC)--maxmax 5 5 Mbit Mbit/sec/sec full full duplex duplex transfer transfer rate, SPI rate, SPI compatible compatibleqq FastFast and accurate and accurate A/D A/D Converter Converter-- 10-Bit10-Bit resolution resolution, 16, 16 input channels input channels, 9.7µs, 9.7µs conversion time conversion time,,
enhanced continuous and scan modes withenhanced continuous and scan modes withchannelchannel--injection capabilityinjection capability..
qq I/O PortsI/O Ports-- 8 Ports8 Ports provide provide 111 I/O 111 I/O lines linesqq WatchdogWatchdog: 16-Bit: 16-Bit Reload Reload--timer causes reset on overflowtimer causes reset on overflow
...Peripherals Set of theC167
9PeripheralsPeripherals
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 25Microcontrollers
qq ThreeThree 16- 16-bitbit up/down up/down timers timers::22 auxiliary timers auxiliary timers(T2,T4)(T2,T4) and and 1 1 core timer core timer(T3)(T3)
qq InputInput mode mode-- Timer modeTimer mode:: Internal clock input with prescaler Internal clock input with prescaler up to up to2.5 MHz / 4002.5 MHz / 400 ns ns;; Clock can be gated with external signal Clock can be gated with external signal
--Counter Mode:Counter Mode: external clock external clock up to 1.25 MHz up to 1.25 MHz--Cascading of core timer and any auxCascading of core timer and any aux.. timer timer (33-Bit (33-Bit timer timer))
qq Count directionCount direction ( (onlyonly T3 ) T3 ) can be changed externally can be changed externallyqq OutputOutput mode mode-- InterruptInterrupt possibility and toggle function at the core timer possibility and toggle function at the core timer T3 T3
-- InterruptInterrupt possibility at auxiliary timers possibility at auxiliary timers T2 T2 and and T4 T4qq ReloadReload:: Core timer can be reloaded with the contents of Core timer can be reloaded with the contents of
any auxany aux.. timer timerqq CaptureCapture:: Contents of the core timer can be latched into Contents of the core timer can be latched into
any auxany aux.. timer timer
General Purpose Timer 1(GPT 1)at 20 MHz
10GPT 1GPT 1
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 26Microcontrollers
GPT 1 Function Diagramat 20 MHz
Clk max2.5 MHzClk max2.5 MHz
Gate
InputMode
Control Core Timer T3 Core Timer T3
ToggleLatch
INTR Flag INTRINTR Flag Flag
Clk max2.5 MHzClk max2.5 MHz
Gate
InputMode
ControlAux Timer T2 / T4Aux Timer T2 / T4
Capture
RunEnable
INTR Flag INTRINTR Flag Flag
Outp.enables
Gate
InputMode
ControlAux Timer T2 / T4Aux Timer T2 / T4
up / down
RunEnable
INTR Flag INTRINTR Flag Flag
Reload
RunEnable Clk max
2.5 MHzClk max2.5 MHz
33-bit cascaded path
max.
1.25 MHz
max.
1.25 MHz
max.
1.25 MHz
up / down
up / down
10GPT 1GPT 1
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 27Microcontrollers
qq TwoTwo 16-Bit up/down 16-Bit up/down timers timers (T5, T6) (T5, T6)qq Input Input mode mode-- Timer modeTimer mode:: Internal clock input with prescaler Internal clock input with prescaler up to 5MHz up to 5MHz
(200ns)(200ns)--CounterCounter mode mode:: External clock External clock up to 2.5 MHz up to 2.5 MHz-- T5T5 can can also also be clocked with the toggle bit of be clocked with the toggle bit of T6 T6
qq OutputOutput mode mode-- InterruptInterrupt possibility and toggle function of possibility and toggle function of a a port line port line (via a (via atoggle bittoggle bit))--OutputOutput of of T6 T6 can be used can be used to to clock clock CAPCOM CAPCOM timers timers
qq Count direction ofCount direction of all all timers can be dynamically changed timers can be dynamically changed(C167)(C167)
qq Cascading of timerCascading of timer T6 T6 with timer with timer T5 T5qq OneOne 16-Bit 16-Bit Capture Capture((forfor T5) / T5) / Reload Reload((forfor T6) T6) register register--Reload register forReload register for T6, T6, Capture register for Capture register for T5 T5
General Purpose Timer 2 (GPT 2)at 20 MHz
11GPT 2GPT 2
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 28Microcontrollers
GPT 2 Function Diagramat 20 MHz
11GPT 2GPT 2
Capture / ReloadCapture / Reload
Clk max5.0 MHzClk max5.0 MHz Input
ModeControl
Aux Timer T2 / T4Aux Timer T2 / T4
RunEnable
Enable
InputMode
Control Timer T5 Timer T5
RunEnable Clk max
5.0 MHzClk max5.0 MHz
ReloadEnable
Clear
Outp.enables
to CAPCOMTimer T0, T1
ToggleLatch
Enable
33-bit cascaded path
INTR Flag INTRINTR Flag Flag
INTR Flag INTRINTR Flag Flag
INTR Flag INTRINTR Flag Flag max.
2.5 MHz
max.
2.5 MHz
up / down
up / down
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 29Microcontrollers
qq FourFour 16- 16-bit timersbit timers (T0/T1 & T7/T8), 16- (T0/T1 & T7/T8), 16-bit reload regbit reload reg.. each each-- Timer modeTimer mode:: Int Int.. clock input with clock input with up to 2.5 MHz (400ns) up to 2.5 MHz (400ns)--CounterCounter mode mode:: External clock input External clock input to T0/T7 up to 1.25 to T0/T7 up to 1.25
MHz, OutputMHz, Output from from T6 T6 can be used as clock input can be used as clock input--CAPCOM 2CAPCOM 2 can be synchronized can be synchronized via T0 to CAPCOM 1 via T0 to CAPCOM 1
qq Two units with sixteenTwo units with sixteen 16-Bit 16-Bit Capture Capture//Compare registersCompare registers-- Individually programIndividually program.. for Capture or any Compare mode for Capture or any Compare mode-- Individually allocatableIndividually allocatable to to timer timer T0/T1 T0/T1 or or T7/T8 T7/T8
qq Various Compare modes forVarious Compare modes for flexible flexiblePulsePulse Width Width Modulation(PWM) Modulation(PWM)--Output-Output-Pin toggles if Compare is truePin toggles if Compare is true-- 11 or or 2 2 Compare registers can operate Compare registers can operate to to one one Output- Output-PinPin--One or more Compare events can be detectedOne or more Compare events can be detected in in one timer one timer
periodperiod-- InterruptInterrupt only mode only mode
qq 44 completely indep completely indep. PWM. PWM channels each with its own time channels each with its own time--basebase-- 50ns50ns or or 12.8µs 12.8µs timer timer--resolution providesresolution provides a a very wide very wide
frequency rangefrequency range to to generate generate PWM PWM signals signals-- Programmable output polarityProgrammable output polarity--Up to 78Up to 78 KHz at KHz at 8- 8-bitbit PWM PWM resolution resolution
qq Four operation modesFour operation modes-- Standard,Standard, edge edge--alignedaligned PWM PWM-- SymmetricalSymmetrical,, center center--alignedaligned PWM PWM for asynchronous motor for asynchronous motor
controlcontrol-- BurstBurst--mode for modulatedmode for modulated PWM PWM signals signals-- Single-Single-shot modeshot mode
FPWM =1
2 x 50ms 8-bit
12
=78 KHz
PWMPWM generation generation - PWM - PWM unit unit
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 36Microcontrollers
PWM unitFrequencies and Resolution
PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL)(SYMMETRICAL)
PMW Unit Frequencies and Resolution in Mode 0 Operation (EDGE-ALIGNED)(EDGE-ALIGNED)
Resolution Resolution
Input Input Clock Clock (CPU @ 20 MHz)
8 Bit 10 Bit 12 Bit 14 Bit 16 Bit
CPU Clock (50ns Resolution)
CPU Clock / 64 (3.2µs Res.)
39.1 KHz
610 Hz
9.77 KHz
152.6 Hz
2.44 KHz
38.15 Hz
610 Hz
9.54 Hz
152.6 Hz
2.4 Hz
Resolution Resolution
InputInput Clock Clock (CPU @ 20 MHz)
8 Bit 10 Bit 12 Bit 14 Bit 16 Bit
CPU Clock (50ns Resolution)
CPU Clock / 64 (3.2µs Res.)
78.1 KHz
1.22 KHz
19.5 KHz
305 Hz
4.88 KHz
76.3 Hz
1.22 KHz
13.1 Hz
305 Hz
4.77 Hz
12PWMPWM generation generation - PWM - PWM unit unit
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 37Microcontrollers
RunEnable
Timer PT0-PT3
Comparator
Shadow Register
INTR Flag INTRINTR Flag Flag
PWM unitFunction Diagramm
InputMode
Control
Pulse Width Reg. PW0-PW3
Shadow Register
4 identical PWM Channels with common Interrupt Control Register
Period Register PP0-PP3
Output PolarityEnable
20 MHz
78 KHz
at 20 MHz CPU Clock
PWMOutputs
Comparator
up/down,clear
12PWMPWM generation generation - PWM - PWM unit unit
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
HL MC AT, lehmann16x_all.ppt26.04.99, 18:20
- 38Microcontrollers
PWM unitMode 0 and 1...
Contents of the PWx Register
Interrupt Request andLatch of the Shadow Register
Contents of the PWxRegister
IR and Latch of theShadow Register
Timer Period
Timer Perio
d Timer Period
Contents of the Period Register (PPx)
PWM Mode 0: Standard PWM’s or Edge-Aligned PWM’s
PWM Mode 1: Symmetrical or Center-Aligned PWM’s
PWM Signal
If all channels are programmed to mode 0,edge-aligned PWM signals will be generated.A duty cycle from 0 to 100% is programmable
If all channels are programmed to mode 1,center-aligned PWM signals will be generated.A duty cycle from 0 to 100% is programmable
PWM Signal
Possible PWM Signals from other channels programmed to the same mode:
PWMx
PWMy
12PWMPWM generation generation - PWM - PWM unit unit
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 39Microcontrollers
... PWM unitModes
Burst Mode :Burst Sequence by combiningPWM channel 0 and 1
Single Shot : Only one PWM Pulse is generated Mode available for channel 2 and 3
Period Value Period Value
Pulse widthValue
PeriodValue
Internal Signalof Channel 0
Period ofTimer PT1
Int. Signalof Channel 1
Output Result: Channel 1 is modulated by Channel 0
OutputSignal
Timer isautomatically
stopped
Timer isreleased by
Software again
The Timer can be dynamically changed tolengthen (retrigger) or shorten the output pulse
Tim
er Perio
d
Timer Period PT0
12PWMPWM generation generation - PWM - PWM unit unit
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 40Microcontrollers
Analog Digital Converter(ADC)
qq 10-Bit ADC10-Bit ADC based on the successive approximation based on the successive approximationprincipleprinciple-- 9.7µs9.7µs conversion conversion--timetime--OnOn--chip samplechip sample- & hold-- & hold-circuitcircuit (1.6 (1.6 us sample us sample--timetime))-- 1616 Multiplexed input channels Multiplexed input channels-- Automatic selfAutomatic self--calibration after conversioncalibration after conversion
qq FlexibleFlexible operation mode operation mode-- Single-Single-channel and singlechannel and single--channelchannel--continuous for periodiccontinuous for periodicdata acquisitiondata acquisition
-- Auto-Auto-scan and autoscan and auto--scanscan--continuous forcontinuous for permanent permanent data datatrackingtracking
--ChannelChannel--injection mode with own resultinjection mode with own result--register can beregister can beusedused to to interrupt the scan modes interrupt the scan modes
qq Easy error handling and channel identificationEasy error handling and channel identification-- 10-10-bit result and channel numberbit result and channel number in in result register result register--Overrun error checkOverrun error check
13ADCADC
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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AnalogInputs
Channel and Mode Control Conversion ControlChannel and Mode Control Conversion Control
ReferenceVoltage
8 (16)ChannelAnalogMUX
C-NETSwitch
Tree
Com-parator
INTR Flag INTRINTR Flag Flag
INTR Flag INTRINTR Flag Flag
10-Bit A/D ConverterBlock Diagram
13ADCADC
Timing Controland SuccessiveApproximation
Register
ChannelInformation Result Register
ChannelSelection Result Register for Channel Injection Mode
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 42Microcontrollers
qq SynchronousSynchronous / / asynchronous serial channel with its own asynchronous serial channel with its ownbaudbaud-rate--rate-generatorgenerator
qq Asynchronous mode with maxAsynchronous mode with max 625 625 KBaud transfer KBaud transfer rate rate-- Full duplex (Full duplex (receive and transmit at the same timereceive and transmit at the same time))-- programmable featuresprogrammable features::-- 11 or or 2 stop 2 stop bits bits, 7, 8, 7, 8 or or 9 9 data bits data bits--GenerationGeneration of parity of parity-- or wake or wake-up-up bit at data transmission bit at data transmission--Odd or even parityOdd or even parity-- Error detectionError detection ( (parityparity,, overrun overrun,, framing framing))--WakeWake-up-up check check ( (receive intreceive int.. flag is set if wake flag is set if wake-up-up bit is true bit is true))
qq Synchronous mode with maxSynchronous mode with max 2.5 2.5 Mbit Mbit/sec/sec transfer range transfer range--Half duplexHalf duplex operation operation ( (only transmit or receive possibleonly transmit or receive possible))-- EasyEasy I/O I/O expansion with external shift register expansion with external shift register--Overrun error detectionOverrun error detection
USARTUSART
Asynchronous / SynchronousSerial Channel (USART) at 20MHz
14
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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INTR Flag
Transmit
INTRINTR Flag Flag
TransmitTransmit
INTR Flag
Receive
INTRINTR Flag Flag
ReceiveReceive
INTR Flag
ERROR
INTRINTR Flag Flag
ERRORERROR
to internal Bus
CPU CLK Baud Rate Generator
Control Reg.
ControlUnit
Transmit Shift Register
Receive Shift Register
Receive Buffer
from internal Bus
Shift CLK
Asynchronous/Synchronous
Port Pin
Port Pin
USARTBlock Diagram
14USARTUSART
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 44Microcontrollers
Synchronous Serial Channel(SSC), SPI compatible at 20 MHz
qq Full duplexFull duplex Synchronous Serial Channel Synchronous Serial Channel (SSC) (SSC) with its with itsown baudrate generator forown baudrate generator for high high speed communication speed communication
qq Up to 5Up to 5 Mbit Mbit/sec/sec transfer transfer rate rateqq SPISPI compatible compatibleqq MasterMaster ( (clock is outputclock is output)) or slave mode or slave mode ( (clock is inputclock is input))qq Programmable featuresProgrammable features to to satisfy various communication satisfy various communication
requirementsrequirements--MSBMSB or or LSB LSB first first--Data frame from oneData frame from one to 16- to 16-bitbit--Clock polarity and phaseClock polarity and phase
14USARTUSART
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 45Microcontrollers
Synchronous Serial Channel - BlockDiagram
Baud RateGenerator
ClockControl
Control Unitwith Controland StatusRegisters
Shift Registerprogrammable from 1 - 16-bit
MSB- / LSB-First Selection
Receive Buffer
Transmit Buffer
Internal Bus
InterruptRequest
Slave ModeMaster Mode SSCCLKCPU
Clock Master / Slave Selection
SSCDI
SSCDO
15SSPSSP
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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qq DevelopedDeveloped in in the mid the mid--eighties byeighties by BOSCH BOSCHqq Asynchronous serial bus withAsynchronous serial bus with linear linear bus structure and bus structure and
equal nodesequal nodes (Multi (Multi Master bus Master bus))qq CANCAN does does not not address nodes address nodes ( (address information isaddress information is
inside the messages combined with message priorityinside the messages combined with message priority))qq Two bus statesTwo bus states: dominant: dominant and recessive and recessiveqq BusBus logic according logic according to " to "WiredWired-AND"-AND" mechanism mechanism::
dominantdominant bits bits (Zeros) (Zeros) override recessive bits override recessive bits ( (OnesOnes))qq Bus Access via CSMA/CDBus Access via CSMA/CD with with NDA ( NDA (CarrierCarrier Sense Sense
Multiple Access/Multiple Access/ Collision Detection with Non Collision Detection with Non--DestructiveDestructiveArbitrationArbitration))
Some things worth knowing aboutCAN...
CAN BusCAN Bus18
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 47Microcontrollers
Typical CAN node structure
CAN_H
CAN_L
e.g.SAE81C90
CAN- Transceiver
CAN-Bus
CAN-Controller
Host-Controller
Application
e.g.80C166
e.g.ABS
e.g.C167CR
orC515C
e.g.EMS
Node A Node B
(more nodes)
UDiff
CAN
CAN BusCAN Bus18
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 48Microcontrollers
Features of the CAN Module onC167CR / C164CI...
19
qq Functionality correspondsFunctionality corresponds to toAN 82527AN 82527
qq Complies withComplies with CAN CAN spec specV2.0BV2.0B active active(Standard- und(Standard- und Extended Extended-CAN)-CAN)
qq Maximum CAN Transfer RateMaximum CAN Transfer Rate(1(1 MBit MBit/s)/s)
qq Full CANFull CAN Device Device-- 15 Message15 Message Objects with Objects withtheir own identifier and theirtheir own identifier and theirown statusown status-- and control bits and control bits
-- EachEach Message Message Object can Object canbe definedbe definedas Transmitas Transmit-- or Receive or ReceiveObjectObject
qq ......
CAN ModuleCAN Module
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 49Microcontrollers
Connecting the to CAN
19
CAN-BusTransceiver
Receive
Transmit
CAN_H
CAN_L
P4.5
P4.6
CAN_L
P2.0
Pa.b
Pc.d
C167CR/C161CI
CAN_H CAN_RxD
CAN_TxD
R(opt)
(Standby)
Vref
n.c.
Connectionto the
Application
CAN ModuleCAN Module
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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- 50Microcontrollers
Watchdog Timer(WDT) at 20 MHz
qq 16-Bit16-Bit timer overflow results timer overflow results in: in:-- SoftwareSoftware reset reset-- PullsPulls RSTOUT RSTOUT Pin low Pin low-- SetsSets identification bit and leaves identification bit and leaves WDT WDT enabled enabled
qq Programmable input clockProgrammable input clockqq High ByteHigh Byte reload register reload registerqq Timer period fromTimer period from 25.6µs to 470ms 25.6µs to 470msqq Can be reloaded withCan be reloaded with a a special instruction special instruction
WatchdogWatchdog22
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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serviceWDT
8-bitreload zero
RSTOUT
SoftwareReset
16-bit Timer
high Byte low Byte
WDT control
CPU CLK / 2 onoverflow
WDTBlock Diagram
CPU CLK / 128
22WatchdogWatchdog
C161C161
C166C166
C163C163
C164C164
C165C165
C167C167
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Overview Port Structure
qq TheThe Port Port lines provide the connection lines provide the connection to to the external world the external world-- 77 Port77 Port lines on the lines on the SAB 80C166 SAB 80C166-- 111 Port111 Port lines on the lines on the C167 C167-- 77 Port77 Port lines on the lines on the C165/C163 C165/C163-- 59 Port59 Port lines on the lines on the C164 C164-- 64 Port64 Port lines on the lines on the C161V/K/O C161V/K/O-- 77 Port77 Port lines on the lines on the C161RI C161RI
qq All PortAll Port lines are individually addressable and lines are individually addressable and all I/0 all I/0 lines linesare independently programmable for input or outputare independently programmable for input or output
qq EachEach Port Port line is dedicated line is dedicated to to one or more peripheral one or more peripheralfunctionsfunctions
qq EachEach Port Port is protected with is protected with fast fast diodes diodesqq Programmable open drain buffersProgrammable open drain buffers-- P2, 3, 6, 7, 8P2, 3, 6, 7, 8 on the on the C167 C167
