UDP C8051F850 MCU CARD USER’S GUIDE FOR C8051F85X/86X MCUS
1. IntroductionThe Unified Development Platform (UDP) provides a development and demonstration platform for SiliconLaboratories microcontrollers, short-range wireless devices, and software tools, including the Silicon LaboratoriesIntegrated Development Environment (IDE).
Figure 1. Unified Development Platform Block Diagram
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2. Relevant Documents
This document provides a hardware overview for the Unified Development Platform (UDP) system C8051F85x/86xMCU card. Additional information on the UDP system and the Silicon Labs 8-bit MCUs can be found in thedocuments listed in this section.
2.1. Motherboard User’s GuideThe UDP Motherboard User’s Guide contains information on the motherboard features and can be found atwww.silabs.com/udp.
2.2. Card User’s GuidesThe UDP MCU, I/O, and radio test card user’s guides can be found at www.silabs.com/udp.
2.3. Application NotesAll 8-bit Application Notes can be found at www.silabs.com/8bit-appnotes.
3.1. Using the MCU Card AloneRefer to Figure 2 for a diagram of the hardware configuration when using the MCU card without a UDPmotherboard.
1. Connect the USB Debug Adapter to the 10-pin debug connector (J23) on the MCU card using the 10-pin ribbon cable.
2. Connect the USB Debug Adapter to a USB Port on the PC.
3. Move the SW1 VDD Select switch to the top +3.3V_VREG position.
4. Verify that the JP2 Imeasure jumper is populated.
5. Power the MCU card through the power connector (J6) using the supplied 9 V ac/dc adapter.
Notes:Use the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.
Remove power from the MCU card and the USB Debug Adapter before connecting or disconnecting the ribbon cable from the MCU card. Connecting or disconnecting the cable when the devices have power can damage the device and/or the USB Debug Adapter.
Figure 2. Hardware Setup Using the MCU Card Alone
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3.2. Using the MCU Card with the UDP MotherboardRefer to Figure 3 for a diagram of the hardware configuration when using the MCU card with a UDP motherboard.
1. Connect the MCU card to the UDP motherboard slot.
2. (Optional) Connect an I/O card to the UDP motherboard slot.
3. (Optional) Connect a radio test card to the radio test card slot in the UDP motherboard.
4. (Optional) Connect an EZLink card to the EZLink card slot in the UDP motherboard.
5. Connect the USB Debug Adapter to the 10-pin debug connector (J23) on the MCU card using the 10-pin ribbon cable.
6. Connect the USB Debug Adapter to a USB Port on the PC.
7. Move the SW1 VDD Select switch to the lower MB position.
8. Verify that the JP2 Imeasure jumper is populated.
9. Connect the ac/dc power adapter to power jack J20 on the UDP motherboard. The board can also be powered from the J16 USB, J1 mini USB connectors, or J11 battery connector socket.
10. Move the S3 power switch on the UDP motherboard to the ON position.
11. Update the motherboard firmware as described in Section 3.3.
Notes:Use the Reset button in the IDE to reset the target when connected using a USB Debug Adapter.
Remove power from the target board and the USB Debug Adapter before connecting or disconnecting the ribbon cable from the target board. Connecting or disconnecting the cable when the devices have power can damage the device and/or the USB Debug Adapter.
The MCU card can be used alone without the motherboard. However, the motherboard must be powered if an MCU card is connected.
Figure 3. Hardware Setup Using the Unified Development Platform
USB Debug Adapter
Power Adapter
(J20)
USB Connector
(J16)
Power SelectSwitch
ImeasureJumper
VirtualCOM Port
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3.3. Updating the UDP Motherboard FirmwareTo ensure the UDP Motherboard supports the C8051F85x/86x MCU card, run the UDP Motherboard FirmwareUpdate Utility shown in Figure 4. This utility can be downloaded from www.silabs.com/udp.
1. Connect the UDP motherboard to a PC using a regular USB cable connected to the UDS connector (J16).
2. Run the utility.
3. Select the desired motherboard if more than one is connected to the PC.
Simplicity Studio greatly reduces development time and complexity with Silicon Labs EFM32 and 8051 MCUproducts by providing a high-powered IDE, tools for hardware configuration, and links to helpful resources, all inone place.
Once Simplicity Studio is installed, the application itself can be used to install additional software anddocumentation components to aid in the development and evaluation process.
Figure 5. Simplicity Studio
The following Simplicity Studio components are required for the C8051F850 Development Kit:
8051 Products Part Support
Simplicity Developer Platform
Download and install Simplicity Studio from www.silabs.com/8bit-software or www.silabs.com/simplicity-studio.Once installed, run Simplicity Studio by selecting StartSilicon LabsSimplicity StudioSimplicity Studiofrom the start menu or clicking the Simplicity Studio shortcut on the desktop. Follow the instructions to install thesoftware and click Simplicity IDE to launch the IDE.
The first time the project creation wizard runs, the Setup Environment wizard will guide the user through theprocess of configuring the build tools and SDK selection.
In the Part Selection step of the wizard, select from the list of installed parts only the parts to use duringdevelopment. Choosing parts and families in this step affects the displayed or filtered parts in the later deviceselection menus. Choose the C8051F85x family by checking the C8051F85x/86x check box. Modify the partselection at any time by accessing the Part Management dialog from the WindowPreferencesSimplicityStudioPart Management menu item.
Simplicity Studio can detect if certain toolchains are not activated. If the Licensing Helper is displayed aftercompleting the Setup Environment wizard, follow the instructions to activate the toolchain.
4.1. Running BlinkyEach project has its own source files, target configuration, SDK configuration, and build configurations such as theDebug and Release build configurations. The IDE can be used to manage multiple projects in a collection called aworkspace. Workspace settings are applied globally to all projects within the workspace. This can include settingssuch as key bindings, window preferences, and code style and formatting options. Project actions, such as buildand debug are context sensitive. For example, the user must select a project in the Project Explorer view in orderto build that project.
To create a project based on the Blinky example:
1. Click the Simplicity IDE tile from the Simplicity Studio home screen.
2. Click the Create new project link from the welcome screen or go to FileNewSilicon Labs MCU Project.
3. In the Kit drop-down, select C8051F850 Development Kit, in the Part drop-down, select C8051F850, and in the SDK drop-down, select the desired SDK. Click Next.
4. Select Example and click Next.
5. Under C8051F850 Development Kit in the Blinky folder, select F85x-86x Blinky and click Finish.
6. Click on the project in the Project Explorer and click Build, the hammer icon in the top bar. Alternatively, go to ProjectBuild Project.
7. Click Debug to download the project to the hardware and start a debug session.
8. Press the Resume button to start the code running. The LED should blink.
9. Press the Suspend button to stop the code.
10. Press the Reset the device button to reset the target MCU.
11. Press the Disconnect button to return to the development perspective.
4.2. Simplicity Studio HelpSimplicity Studio includes detailed help information and device documentation within the tool. The help containsdescriptions for each dialog window. To view the documentation for a dialog, click the question mark icon in thewindow:
This will open a pane specific to the dialog with additional details.
The documentation within the tool can also be viewed by going to HelpHelp Contents or HelpSearch.
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4.3. Simplicity ConfiguratorThe Simplicity Configurator is a configuration and code generation tool. This utility helps accelerate developmentby automatically generating initialization source code to configure and enable the on-chip resources needed bymost design projects. In just a few steps, the wizard creates complete startup code for a specific Silicon Labs MCU.
To create a new Simplicity Configurator project:
1. Click the Create new project link from the welcome screen or go to FileNewSilicon Labs MCU Project.
2. In the Kit drop-down, select C8051F850 Development Kit or None, in the Part drop-down, select C8051F850, and in the SDK drop-down, select the desired SDK. Click Next.
3. Select Simplicity Configurator Program and click Next.
4. Fill in the Project name and select the desired device. The C8051F850-C-GU-QSOP device is on the C8051F850 Target Board. Click Finish.
The Simplicity Configurator project displays properties for each peripheral. To configure a peripheral, click on theDefaultMode Peripherals tab at the bottom and click on a peripheral. Checking the box for a peripheral will add itto code generation. Once a peripheral is selected, configure the registers using the Properties view. Select a newvalue for a property with either an input box or a drop-down menu and press Enter to set it.
To configure pins, click on the DefaultMode Port I/O tab at the bottom of main window. Clicking on a pin brings upa property window for the pin. Clicking anywhere else in the main window opens a property window for thecrossbar. Select multiple pins with Ctrl + left click or mouse dragging over the desired set of pins. The packagediagram displays the configured peripherals on the pins, including non-crossbar signals (i.e. ADC inputs).
Code generation updates every time the configuration project saves. After configuring the device, add any non-initialization code, build, and debug the same as with any other project.
More information on Simplicity Configurator can be found in AN0823: Simplicity Configurator User’s Guide andAN0821: Simplicity Studio C8051F85x Walkthrough. Application notes can be found on www.silabs.com/8bit-appnotes.
Figure 7. Simplicity Configurator – Configuring Port I/O
4.4. Legacy 8-bit IDENote: Using the Simplicity Studio tools with the C8051F850 Development Kit is recommended. See section 4. "Software
Setup‚" on page 6 for more information.
Download the 8-bit software from the website (www.silabs.com/8bit-software) or use the provided installer on theCD-ROM to install the software tools for the C8051F85x/86x devices. After installation, examples can be found in...\Examples\C8051F85x_86x in the installation directory. At a minimum, the C8051F850 DK requires:
Silicon Labs IDE—Software enabling initial evaluation, development, and debugging.
Configuration Wizard 2—Initialization code generation software for the C8051F85x/86x devices.
CP210x Drivers—Virtual COM Port (VCP) drivers for the CP210x COM interface. More information on this installation process can be found in Section 4.5.
Other software available includes:
Keil µVision Driver—Driver for the Keil µVision IDE that enables development and debugging on C8051Fxxx MCUs.
Flash Programming Utilities and MCU Production Programmer—Programming utilities for the production line. More information on the available programming options can be found on the website:http://www.silabs.com/products/mcu/Pages/ProgrammingOptions.aspx.
ToolStick Development Tools—Software and examples for the ToolStick development platform. More information on this platform can be found at www.silabs.com/toolstick.
The development kit includes the latest version of the C51 Keil 8051 toolset. This toolset is initially limited to a codesize of 2 kB and programs start at code address 0x0800. After registration, the code size limit is removed entirelyand programs will start at code address 0x0000.
To register the Keil toolset:
1. Find the Product Serial Number printed on the CD-ROM. If you no longer have this serial number, register on the Silicon Labs website (www.silabs.com/8bit-software) to obtain the serial number.
2. Open the Keil µVision4 IDE from the installation directory with administrative privileges.
3. Select FileLicense Management to open the License Management window.
Figure 8. Keil µVision4 IDE License Management Window
4. Click on the Get LIC via Internet... button to open the Obtaining a License IDE Code (LIC) window.
5. Press OK to open a browser window to the Keil website. If the window doesn’t open, navigate to
6. Enter the Silicon Labs Product Serial Number printed on the CD-ROM, along with any additional required information.
7. Once the form is complete, click the Submit button. An email will be sent to the provided email address with the license activation code.
8. Copy the License ID Code (LIC) from the email.
9. Paste the LIC into the New License ID Code (LIC) text box at the bottom of the License Management window in µVision4.
10. Press the Add LIC button. The window should now list the PK51 Prof. Developers Kit for Silabs as a licensed product.
11. Click the Close button.
4.5. CP210x USB to UART VCP Driver InstallationThe MCU Card includes a Silicon Labs CP210x USB-to-UART Bridge Controller. Device drivers for the CP210xneed to be installed before the PC software can communicate with the MCU through the UART interface. Use thedrivers included CD-ROM or download the latest drivers from the website (www.silabs.com/interface-software).
1. If using the CD-ROM, the CP210x Drivers option will launch the appropriate driver installer. If downloading the driver package from the website, unzip the files to a location and run the appropriate installer for the system (x86 or x64).
2. Accept the license agreement and follow the steps to install the driver on the system. The installer will let you know when your system is up to date. The driver files included in this installation have been certified by Microsoft.
3. To complete the installation process, connect the included USB cable between the host computer and the COM PORT USB connector (J5) on the MCU Card. Windows will automatically finish the driver installation. Information windows will pop up from the taskbar to show the installation progress.
If needed, the driver files can be uninstalled by selecting Windows Driver Package—Silicon Laboratories... option in the Programs and Features window.
The C8051F850 MCU card enables application development on the C8051F85x/86x MCU device family. The cardconnects to the MCU card expansion slot on the UDP motherboard and provides complete access to the MCUresources. Each expansion board has a unique ID that can be read out of an EEPROM or MCU on the board,which enables software tools to recognize the connected hardware and automatically select the appropriatefirmware image. The target MCU card can also be detached from the UDP and used alone as a development ordemonstration tool.
Figure 9 and Figure 10 highlight the C8051F850 MCU card features.
Figure 9. C8051F850 MCU Card Features—Front
PotentiometerAnalogTerminals
Push-Button Switches
Mini-B USB Connector
for VCP
Power
Debug Connector
Prototyping Area
Reset Push-Button
LEDs
VCP-Enabled LED
VDD Select Switch and Power LED
Current Measure Jumper
Port Access
Voltage and Ground Reference Access
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Figure 10. C8051F850 MCU Card Features—Back
Electronic Board ID (EBID)
Virtual COM Port
Port Pin Isolation Resistors
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5.1. Push-Button Switches and LEDs (S1-2, DS5-6)The UDP C8051F850 MCU Card has two push-button switches and two LEDs. The two LEDs connect to P1.0 andP1.1, and the two switches connect to P1.7 and P2.1. The switches are normally open and pull the pin voltage toground when pressed. The LEDs connect to VDD through a current-limiting resistor and turn on when thecorresponding port pin is low.
The header J27 can be used to disconnect the switches and LEDs from the GPIO pins.
5.2. Analog Terminals (J34)Several of the C8051F850 port pins used for analog functions are connected to the J34 terminal block. Refer toTable 2 for the J34 terminal block connections.
5.3. Potentiometer (R13)The potentiometer is available on P1.2 (ADC0.10). To use the potentiometer, install a shorting block on J27 pins 9and 10 to connect P1.2 to the potentiometer.
5.4. Voltage and Ground Reference (J32)The C8051F850 has options to use an external voltage reference on the P0.0 / VREF pin and an external analogground reference on the P0.1 / AGND pin. The J32 header allows an external supply to clip to pin 1 for AGND andpin 2 for VREF. These signals can then be connected to the MCU by populating a shorting block between pins 3and 5 for AGND and pins 4 and 6 for VREF. Populating this shorting block for VREF connects P0.0 to the requiredcapacitors for the external reference.
Table 1. Switch and LED Pin Descriptions
MCU Pin FunctionPB1.0 Red LED DS5 (LED1)
PB1.1 Red LED DS6 (LED2)
PB1.7 Switch S1
PB2.1 Switch S2
Table 2. Terminal Block Pin Descriptions (J34)
Terminal Pin MCU I/O1 VREF / P0.0
2 GND
3 ADC0.9 / P1.1
4 ADC0.12 / P1.4
5 ADC0.10 / P1.2
6 ADC0.13 / P1.5
Table 3. Terminal Block Pin Descriptions (J25)
MCU Pin Analog Signal DescriptionP0.0 VREF Clip external source to J32 pin 2, apply shorting block
between pins 4 and 6 to connect to the MCU
P0.1 AGND Clip external ground to J32 pin 1, apply shorting block between pins 3 and 5 to connect to the MCU
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5.5. VDD Power Select Switch (SW1)The VDD power supply has two power options: UDP motherboard (PWR_VDD_OUT) and on-board +3.3 Vregulator power. The VDD Power Select switch is used to select between the two options. The +3.3 V regulatorpower option is the upper +3.3_VREG position and allows the board to be powered from a diode-OR of four powersources: 9 V Power Adapter (J6), the USB connector labeled COM PORT (J5), the USB Debug Adapter (J23), orfrom the UDP motherboard bulk supply (PWR_5.0V_BULK).
5.6. Power LED (DS9)The blue power LED provides visual feedback when the board is powered through USB, the 9 V power adapter, theUSB Debug Adapter, or from the UDP motherboard. The power LED indicates that power is available on the boardand the VDD Power Select switch must be configured properly to power the MCU.
5.7. Imeasure Jumper (JP2)The Imeasure jumper (JP2) allows for easy access to measure the VDD current of the MCU. The shorting block forthis header is populated by default, and the direction of current is shown with a silk screen arrow. To measure thesupply current, remove the corresponding shorting block and connect a current measurement device across theunpopulated header.
The voltage supply prior to the Imeasure jumper is the VDD pre-measure (VDD_PM) net, which supplies all of theexternal LEDs, switches, USB COM, and reset pull-up. The VDD after the Imeasure jumper only connects to theMCU.
5.8. Debug Header (J23)The shrouded 10-pin debug header supports the Silicon Labs USB Debug Adapter. This connector provides a C2debug connection to the C8051F85x/86x on the MCU card.
5.9. Reset Button (S5)The reset push-button switch is just below the debug header (J23). Pushing this button will always reset the MCU.Note that pushing this button while the IDE is connected to the MCU will result in the IDE disconnecting from thetarget.
5.10. UART Connection Options (J7, U2, U4, U5)The MCU card features a USB virtual COM port (VCP) UART connection via the mini-B USB connector (J5)labeled COM PORT. The VCP connection uses the CP210x USB-to-UART bridge chip (U2). The GPIO pinsconnected to the CP210x device can be enabled or disabled through the J7 header. Table 4 shows the GPIO pinsthat are routed to the CP210x.
In addition to the CP210x USB-to-UART connection, the MCU card can connect the C8051F850 UART signalswith the UDP Motherboard UART signals UART_TX_SYS and UART_RX_SYS using U5. The signals to switchbetween the two interfaces are UART_VCP_EN and UART_SYS_EN and are controlled by the motherboard. Thedefault selection with or without the motherboard is the CP210x VCP interface using a pull-down resistor R20.
5.11. Port Pin Headers (J24, J24, J26)All of the MCU port pins are available on the 0.100-inch headers on MCU card. Each connector providesconnections to each port, VDD, and ground. Any unused pins on the P2 header are not connected. Some of theseport pins are shared with other functions on the board and may be modified as explained in Section 5.13.
Table 4. CP210x Controlled GPIO Pins
MCU Pin COM FunctionP0.4 UART Transmit
P0.5 UART Receive
VDD COM VIO
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5.12. Electronic Board ID (EBID) (U1, J35)The MCU card has a unique ID that can be read out from the Silicon Labs C8051F990 MCU (U1). This MCUenables software tools to recognize the connected hardware and automatically select the appropriate firmwareimage.
The EBID device uses two I2C signals to communicate: UDPBUS_SDA_A and UDPBUS_SCL_A. These signalsare connected to P0.6 and P0.7 on the C8051F850 MCU through the J25 header. These signals can bedisconnected from the MCU during power measurements.
5.13. MCU Port Pin ConnectionsThe MCU card has many UDP connections for use with different I/O cards and the UDP motherboard. Table 6describes all functions connected to each pin on the C8051F850 MCU. All of the UDP connections are made withpopulated 0 ohm resistors on the back of the MCU card. To disconnect a signal from the pin, remove the 0 resistor.
Table 5. Terminal Block Pin Descriptions (J25)
MCU Pin EBID / UDP SignalP0.6 UDPBUS_SDA_A
P0.7 UDPBUS_SCL_A
Table 6. MCU Card and UDP Pin Functions
MCU Pin MCU Card Function or UDP SignalP0.0 VREF SPI_SCK_EZR ADC_VREF GPIO05
6. Using the C8051F850 MCU Card with the UDP Motherboard
6.1. MCU Card Header ConnectionsThe MCU card has four connectors with 100 pins each. These 400 pins are directly tied to the UDP motherboardand I/O cards. These signals are named and designed to support a wide variety of features and applications, andthe C8051F850 MCU card implements a subset of these connections.
The MCU cards and I/O cards are designed so that a maximum number of functions are shared between eachcard. This allows a particular type of I/O card to be shared amongst all MCU cards that connect to the samesignals.
The MCU card slot includes the following components:
The C8051F850 MCU card implements the signals described in Table 8, Table 9, Table 10, and Table 11 in theAppendix.
6.2. Shorting Blocks: Factory DefaultsThe C8051F850 MCU card comes from the factory with pre-installed shorting blocks on several headers. Figure 11shows the positions of the factory default shorting blocks.
Figure 11. Shorting Blocks: Factory Defaults
A shorting block is installed across the JP2 Imeasure header to enable power to the MCU. Shorting blocks areinstalled on J7 to enable the virtual COM port. Shorting blocks are also installed on J27 to enable the switches,LEDs, and potentiometer to be connected to GPIO pins.
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7. Power Measurement
The C8051F850 MCU card includes a JP2 Imeasure jumper for MCU power measurement purposes. The VDDsupply on pin 2 of the header connects only to the MCU on the board. The VDD pre-measure (VDD_PM) supply onpin 1 of the JP2 header powers the external LEDs, switches, reset switch, potentiometer, and VCP COM.
7.1. Measuring Power with Fixed VDDTo measure the power of the C8051F850 MCU using the MCU card at a fixed 3.3 V:
1. Connect a USB Debug Adapter to the 10-pin shrouded debug connector (J23).
2. Remove the three shorting blocks from J7.
3. Remove the JP2 Imeasure shorting block.
4. Connect a multimeter across (positive side on the left pin, current flow indicated by the silk screen arrow).
5. Move the VDD Select switch (SW2) to the upper +3.3V_VREG position.
6. Connect the 9 V power adapter to POWER (J6).
7. Download the code to the board.
8. Remove the debug adapter connection.
9. Measure the power of the device.
Figure 12. C8051F850 MCU Card Power Measurement Configuration— Fixed VDD
+000.500 µADC
USB Debug Adapter
1
2
3
5
8
4
6
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7.2. Measuring Power with Varying VDDTo measure power with a varying VDD:
1. Connect a USB Debug Adapter to the 10-pin shrouded debug connector (J23).
2. Remove the three shorting blocks from J7.
3. Remove the JP2 Imeasure shorting block.
4. Connect a multimeter across the JP2 Imeasure jumper (positive side on the left pin, current flow indicated by the silk screen arrow).
5. Move the VDD Select switch (SW2) to the lower MB position.
6. Connect the negative terminal of a bench power supply to board ground.
7. Connect the positive terminal of a bench power supply to the positive side (left pin) of the Imeasure jumper. This will ensure that the /RST pin pull-up is powered.
Note: The pull-up resistor on /RST is powered by the VDD pre-measure (VDD_PM) net, which is separated from the VDD netwith the Imeasure shorting block (JP2) removed. Powering the MCU using VDD without powering the VDD_PM net willprevent the IDE from communicating with the MCU.
8. Download the code to the board.
9. Remove the debug adapter connection.
10. Measure the power of the device.
Figure 13. C8051F850 MCU Card Power Measurement Configuration—Varying VDD
8. Known Board IssuesThere are no known issues with Revision 200 of the C8051F850 MCU card.
+000.500 µADC
2.8 V
USB Debug Adapter
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2
3
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9
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9. Schematics
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R10
60
R89
0
R99
0
R11
20
R11
10
R79
0
R71
0
J24 P
ort 0
11
22
33
44
55
66
77
88
99
1010
TP15
C2C
K
R11
60
JS12
Jum
per S
hunt
R11
50
R11
70
R68
0
R98
0
TP14
C2D
R10
70
J23
5X2
Shr
oude
d H
eade
r
DE
BU
G
11
22
33
44
55
66
77
88
99
1010
JS13
Jum
per S
hunt
R11
30
R11
90
R77
0
R80
0
R10
20
R87
0
R64 1K
C28
0.1u
F
J26 P
ort 2
11
22
33
44
55
66
77
88
99
1010
R84
0
R90
0
R81
0
R96
0
R85
0
R76
0
R36
0
C30
1uF
R88
0
U11
C80
51F8
50
NC
1
P0.
22
P0.
1 / A
GN
D3
P0.
0 / V
RE
F4
GN
D5
VD
D6
/RS
T / C
2CK
7
C2D
/ P
2.0
8
P1.
79
P1.
610
P1.
511
P2.
112
NC
13P
1.4
14P
1.3
15P
1.2
16P
1.1
17P
1.0
18P
0.7
19P
0.6
20P
0.5
21P
0.4
22P
0.3
23N
C24
R72
0
MH
R66
0
R10
30
J25 P
ort 1
11
22
33
44
55
66
77
88
99
1010
R10
10
R10
90
R11
00
MH
R65
0
R70
0
R78
0
R63 1K
J35
EB
ID I2
C
11
33
22
44
R91
0
R37
0
MH
R73
0
R67
0
R10
40
Fig
ure
14.C
8051
F85
0 U
DP
MC
U C
ard
Sch
emat
ic (
Rev
isio
n 2
00)
(1 o
f 5)
C8051F850-DK-UG
Rev. 0.3 21
5 5
4 4
3 3
2 2
1 1
Power Test Points
User Interface
ADC0.9 / P1.1
ADC0.10 / P1.2
ADC0.12 / P1.4
ADC0.13 / P1.5
Silk
arr
ow
indi
cate
s cu
rren
t fl
ow
VREF / P0.0
VDD Pre-Measure
GND
AGND
VD
D_P
M
+3.3
V_V
RE
G
PW
R_5
.0V
_BU
LK
US
B_5
.0V
PW
R_V
DD
_OU
T
VD
D
VD
D
VD
D_P
M
VD
D
DE
BU
G_5
.0V
+3.3
V_V
RE
G
VD
D_P
M
VD
D_P
M
VD
D_P
M
VD
D_P
MV
RE
F
/RS
T
P1.
0P
1.1
P1.
7P
2.1
P1.
2
AD
C0.
9A
DC
0.10
AD
C0.
12A
DC
0.13
P0.
0 P0.
1
AD
C0.
9A
DC
0.10
AD
C0.
12A
DC
0.13
P1.
1P
1.2
P1.
4P
1.5
VR
EF
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
02.
0
C80
51F8
50 M
CU
Boa
rd
B
25
Frid
ay, M
ay 1
7, 2
013
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
02.
0
C80
51F8
50 M
CU
Boa
rd
B
25
Frid
ay, M
ay 1
7, 2
013
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
02.
0
C80
51F8
50 M
CU
Boa
rd
B
25
Frid
ay, M
ay 1
7, 2
013
TP5 V
DD
C37
4.7u
F
R11
1K
S1
P1.
7
D6
15V
DS
9B
LUE
PO
WE
R
S5
RE
SE
T
C36
4.7u
F
R95
1K
J32
VR
EF/
AG
ND
135
246
TP8 G
ND
SW
1
SW
_SLI
DE
_2P
OS
VD
D S
elec
t
123
R15
750
J6Pow
er J
ack
PO
WE
R
321
C6
0.1u
F
S2
P2.
1
R13
10K
1 3
2
R19
1.5K
D7
STP
S14
0Z
TP3
RE
SE
T
C7
4.7u
F
R16
750
TP16 V
DD
_PM
J34
Ana
log
Hea
der
1 3 52 4 6
C38
0.1u
F
R25
100K
TP9 G
ND
TP17 G
ND
JS2
Jum
per S
hunt
R94
1K
DS
5R
ED
P1.
0
JS14
Jum
per S
hunt
R9
1K
D3
STP
S14
0Z
JS1
Jum
per S
hunt
JS3
Jum
per S
hunt
C20
0.01
uF
JS15
Jum
per S
hunt
TP10 G
ND
DS
6R
ED
P1.
1
TP18 G
ND
JS4
Jum
per S
hunt
D4
STP
S14
0Z
J27 Por
t 0
11
22
33
44
55
66
77
88
99
1010
JS5
Jum
per S
hunt
D5
STP
S14
0Z
TP11 G
ND
JP2
JUM
PE
RIm
easu
re
U6 LP
2989
-3.3
V
BY
P1
NC
2
GN
D3
INP
UT
4O
UTP
UT
5S
EN
SE
6E
RR
OR
7S
DN
8
JS6
Jum
per S
hunt
Fig
ure
15.C
8051
F85
0 U
DP
MC
U C
ard
Sch
emat
ic (
Rev
isio
n 2
00)
(2 o
f 5)
C8051F850-DK-UG
22 Rev. 0.3
54
32
1
Enables switch between MCU Card
COM and Motherboard COM.
VIO
_CO
M
VIO
_CO
M
VD
D_C
OM
VD
D_C
OM
VIO
_CO
M
PW
R_3
.3V
_BU
LK
US
B_5
.0V
VD
D_P
MV
DD
_CO
M
MC
U_R
X
MC
U_T
X
UA
RT_
VC
P_E
N
VC
P_R
X
VC
P_T
X
MC
U_R
X
MC
U_T
X
UA
RT_
SY
S_E
N
UA
RT_
RX
_SY
S
UA
RT_
TX_S
YS
VC
P_R
XV
CP
_TX
P0.
4P
0.5
MC
U_T
XM
CU
_RX
R4
1K
JS11
Jum
per S
hunt
C16
4.7u
F
C12
0.1u
F
R11
81M
DS
10R
ED
CO
M
TP12
VC
OM
RTS
C10
0.1u
F
C19
0.1u
FN
I
R22 0
C13
0.1u
F
J5 US
B T
YP
E M
INI B
CO
M P
OR
T
+V D-
D+
ID GN
D
SHSH
C17
1uF
R20
10K
U5
74A
VC
4T24
5
1DIR
2V
CC
A1
2B1
111A
25
2A1
6
2A2
7
GND8
1OE
15
2OE
14
1B1
13
1B2
12
2B2
10
GND9
2DIR
3
1A1
4
VC
CB
16
L10.
68uH
NI
TP13
VC
OM
CTS
C11
0.1u
F
C18
0.1u
F
U2
CP
2103
VDD6
VIO5
REGIN7 GND
2
RE
SE
T9
SU
SP
11S
US
P12
VBUS8
D+
3D
-4
CTS
22R
TS23
DS
R26
RX
D24
DTR
27
TXD
25
DC
D28
RI
1
GP
IO.3
16G
PIO
.217
GP
IO.1
18G
PIO
.019
EPAD29
NC
10N
C13
NC
14
NC
15
NC
20
NC
21
D1
SP
0503
BA
HT
J7 CO
M1 3 5
2 4 6
C3
1uF
JS10
Jum
per S
hunt
C15
0.1u
F
U4
74A
VC
4T24
5
1DIR
2V
CC
A1
2B1
111A
25
2A1
6
2A2
7
GND8
1OE
15
2OE
14
1B1
13
1B2
12
2B2
10
GND9
2DIR
3
1A1
4
VC
CB
16
R21
10K
R12
275
0C
40.
1uF
JS9
Jum
per S
hunt
Fig
ure
16.C
8051
F85
0 U
DP
MC
U C
ard
Sch
emat
ic (
Rev
isio
n 2
00)
(3 o
f 5)
C8051F850-DK-UG
Rev. 0.3 23
5 5
4 4
3 3
2 2
1 1
Electronic Board Identification (EBID)
PW
R_S
YS
_BU
LK
PW
R_S
YS
_BU
LK
C2_
CLK
_BC
2_D
AT_
B
C2_
CLK
_B
C2_
DA
T_B
PC
A_E
CI_
AP
CA
_CH
0_A
SP
I_S
CK
_EZR
SP
I_M
ISO
_EZR
SP
I_M
OS
I_E
ZRS
PI_
NS
S0_
EZR
GP
IO00
GP
IO01
GP
IO02
GP
IO03
GP
IO04
PC
A_C
H1_
A
WA
KE
UP
1W
AK
EU
P0
EX
T_IN
T0E
XT_
INT1
UA
RT_
RX
_SY
S
UD
PB
US
_SD
A_A
UD
PB
US
_SC
L_A
TIM
ER
_CT_
A
TIM
ER
_CT_
B
PC
A_C
H0_
B
I2C
_SC
L_E
ZRI2
C_S
DA
_EZR
UA
RT_
TX_A
UA
RT_
RX
_AU
AR
T_R
TS_A
UA
RT_
CTS
_AU
AR
T_TX
_SY
SU
AR
T_R
TS_S
YS
UA
RT_
CTS
_SY
S
CLK
OU
T0
GP
IO05
GP
IO06
Title
Siz
eD
ocum
ent N
umbe
r
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
0
C80
51F8
50 M
CU
Boa
rd
B
45
Frid
ay, M
ay 1
7, 2
013
Title
Siz
eD
ocum
ent N
umbe
r
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
0
C80
51F8
50 M
CU
Boa
rd
B
45
Frid
ay, M
ay 1
7, 2
013
Title
Siz
eD
ocum
ent N
umbe
r
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
0
C80
51F8
50 M
CU
Boa
rd
B
45
Frid
ay, M
ay 1
7, 2
013
U1
C80
51F9
90
P0.
1_A
GN
D1
GND3
VDD4
RS
T_C
2CK
5P
2.7_
C2D
6
P1.
77
P1.
68
P0.
220
P1.
1_C
PO
-13
P1.
0_C
PO
+14
P1.
310
P1.
59
P1.
211
P0.
319
P0.
7_IR
EF
15P
0.6_
CO
NV
VS
TR16
P0.
0_V
RE
F2
RX
_P0.
517
TX_P
0.4
18
GNDEPADGND
12
C2
0.1u
F
R46
0N
I
J1U
DP
MC
U H
1
UD
P D
C H
EA
DE
R
LPTI
ME
R_O
UT_
A10
0G
ND
1
LPTI
ME
R_I
N_A
99U
SA
RT_
TX_A
2
LIN
_RX
_B98
US
AR
T_R
X_A
3
LIN
_TX
_B97
US
AR
T_R
TS_A
4
CA
N_R
X_A
96U
SA
RT_
CTS
_A5
CA
N_T
X_A
95U
SA
RT_
UC
LK_A
6
EX
T_D
MA
_TR
IG1
94C
AN
_TX
_B7
EX
T_D
MA
_TR
IG0
93C
AN
_RX
_B8
EX
T_D
AC
_TR
IG1
92S
PI_
SC
K_A
9
EX
T_D
AC
_TR
IG0
91S
PI_
MIS
O_A
10
EX
T_A
DC
_TR
IG1
90S
PI_
MO
SI_
A11
EX
T_A
DC
_TR
IG0
89S
PI_
NS
S0_
A12
EX
T_IN
T188
SP
I_N
SS
1_A
13
EX
T_IN
T087
SP
I_N
SS
2_A
14
WA
KE
UP
186
SP
I_N
SS
3_A
15
WA
KE
UP
085
US
AR
T_TX
_B16
PO
RT_
MA
TCH
184
US
AR
T_R
X_B
17
PO
RT_
MA
TCH
083
US
AR
T_R
TS_B
18
GP
IO15
82U
SA
RT_
CTS
_B19
GP
IO14
81U
SA
RT_
UC
LK_B
20
GP
IO13
80E
PC
A_E
CI_
A21
GP
IO12
79E
PC
A_C
H0_
A22
GP
IO11
78E
PC
A_C
H1_
A23
GP
IO10
77E
PC
A_C
H2_
A24
GP
IO09
76E
PC
A_C
H3_
A25
GP
IO08
75E
PC
A_C
H4_
A26
GP
IO07
74E
CP
A_C
H5_
A27
GP
IO06
73LI
N_T
X_A
28
GP
IO05
72LI
N_R
X_A
29
GP
IO04
71P
CA
_EC
I_A
30
GP
IO03
70P
CA
_CH
0_A
31
GP
IO02
69P
CA
_CH
1_A
32
GP
IO01
68P
CA
_EC
I_B
33
GP
IO00
67P
CA
_CH
0_B
34
CLK
OU
T066
PC
A_C
H1_
B35
I2S
IN_D
OU
T_A
65I2
SO
UT_
DFS
_A36
I2S
IN_C
LK_A
64I2
SO
UT_
CLK
_A37
I2S
IN_D
FS_A
63I2
SO
UT_
DO
UT_
A38
I2C
_SC
L_B
62I2
C_S
DA
_EZR
39
I2C
_SD
A_B
61I2
C_S
DA
_EZR
40
SP
I_N
SS
3_E
ZR60
TIM
ER
_CT_
A41
SP
I_N
SS
2_E
ZR59
TIM
ER
_EX
_A42
SP
I_N
SS
1_E
ZR58
TIM
ER
_CT_
B43
SP
I_N
SS
0_E
ZR57
TIM
ER
_EX
_B44
SP
I_M
OS
I_E
ZR56
UA
RT_
TX_A
45
SP
I_M
ISO
_EZR
55U
AR
T_R
X_A
46
SP
I_S
CK
_EZR
54U
AR
T_R
TS_A
47
UA
RT_
CTS
_SY
S53
UA
RT_
CTS
_A48
UA
RT_
RTS
_SY
S52
UA
RT_
TX_S
YS
49
UA
RT_
RX
_SY
S51
GN
D50
R51
0
R47
0N
I
R52
0
C1
1uF
R3
1K
JP1
CO
NN
SO
CK
ET
4X1
NI
Fig
ure
17.C
8051
F85
0 U
DP
MC
U C
ard
Sch
emat
ic (
Rev
isio
n 2
00)
(4 o
f 5)
C8051F850-DK-UG
24 Rev. 0.3
5 5
4 4
3 3
2 2
1 1
D C B A
PW
R_V
DD
_OU
T
PW
R_5
.0V
_BU
LK
PW
R_S
YS
_BU
LK
PW
R_3
.3V
_BU
LK
UD
PB
US
_SD
A_A
UD
PB
US
_SC
L_A
C2C
KC
2D C2_
CLK
_BC
2_D
AT_
B
UA
RT_
VC
P_E
NU
AR
T_S
YS
_EN
AD
C_I
N0
AD
C_I
N1
AD
C_V
RE
F
AD
C_I
N2
AD
C_I
N3
CP
_OU
T_A
AD
C_V
RE
FGN
D
CP
_OU
TA_A
EP
CA
_CH
0_M
OTO
R
EP
CA
_CH
2_M
OTO
R
EP
CA
_CH
4_M
OTO
R
CP
_PO
S_A
CP
_NE
G_A
EP
CA
_CH
1_M
OTO
R
EP
CA
_CH
3_M
OTO
R
EP
CA
_CH
5_M
OTO
R
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
02.
0
C80
51F8
50 M
CU
Boa
rd
B
55
Frid
ay, M
ay 1
7, 2
013
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
02.
0
C80
51F8
50 M
CU
Boa
rd
B
55
Frid
ay, M
ay 1
7, 2
013
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
400
W C
esar
Cha
vez
Aus
tin, T
X 7
8701
UP
MU
-F85
02.
0
C80
51F8
50 M
CU
Boa
rd
B
55
Frid
ay, M
ay 1
7, 2
013
J3U
DP
MC
U H
3
UD
P D
C H
EA
DE
R
$PIN
010
0G
ND
1
$PIN
299
PW
R_V
DD
_IN
2
$PIN
498
PW
R_V
DD
_IN
3
$PIN
697
PW
R_V
DD
_OU
T4
$PIN
896
PW
R_V
DD
_OU
T5
$PIN
1095
PW
R_R
AD
IO_I
N6
$PIN
1294
PW
R_R
AD
IO_I
N7
$PIN
1493
PW
R_R
AD
IO_O
UT
8
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1692
PW
R_R
AD
IO_O
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9
$PIN
1891
PW
R_I
O_I
N10
$PIN
2090
PW
R_I
O_I
N11
$PIN
2289
PW
R_I
O_O
UT
12
$PIN
2488
PW
R_I
O_O
UT
13
$PIN
2687
PW
R_I
O_B
US
14
$PIN
2886
PW
R_I
O_B
US
15
$PIN
3085
PW
R_A
UX
_BU
S16
$PIN
3284
PW
R_A
UX
_BU
S17
$PIN
3483
PW
R_H
V1_
BU
S18
$PIN
3682
PW
R_H
V1_
BU
S19
$PIN
3881
PW
R_H
V2_
BU
S20
$PIN
4080
PW
R_H
V2_
BU
S21
$PIN
4279
PW
R_V
PP
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LK22
$PIN
4478
PW
R_V
PP
_BU
LK23
$PIN
4677
PW
R_5
.0V
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LK24
$PIN
4876
PW
R_5
.0V
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LK25
$PIN
5075
PW
R_5
.0V
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LK26
$PIN
5274
PW
R_5
.0V
_BU
LK27
$PIN
5473
PW
R_3
.3V
_BU
LK28
$PIN
5672
PW
R_3
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LK29
$PIN
5871
PW
R_3
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LK30
$PIN
6070
PW
R_3
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LK31
$PIN
6269
PW
R_S
YS
_BU
LK32
$PIN
6468
PW
R_S
YS
_BU
LK33
$PIN
6667
GN
D34
$PIN
6866
EB
ID_S
CK
35
$PIN
7065
EB
ID_M
OS
I36
$PIN
7264
EB
ID_M
ISO
37
$PIN
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EB
ID_N
SS
38
$PIN
7662
C2_
CLK
_A39
$PIN
7861
C2_
DA
T_A
40
$PIN
8060
C2_
CLK
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$PIN
8259
C2_
DA
T_B
42
$PIN
8458
C2_
CLK
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$PIN
8657
C2_
DA
T_C
44
$PIN
8856
C2_
CLK
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$PIN
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C2_
DA
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46
VC
P_E
N54
C2_
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RT_
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S_E
N53
C2_
DA
T_E
48
JTA
G_T
DI_
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JTA
G_T
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GN
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U H
4
UD
P D
C H
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D10
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ND
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299
C2D
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00_A
2
$PIN
498
C2D
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01_A
3
$PIN
697
C2D
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02_A
4
ITM
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X03
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ITM
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T395
C2D
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04_A
6
ITM
_DA
T294
C2D
_TX
05_A
7
ITM
_DA
T193
C2D
_TX
06_A
8
ITM
_DA
T092
C2D
_TX
07_A
9
$PIN
1891
C2D
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08_A
10
EZR
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IO4
90C
2D_T
X09
_A11
EZR
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IO3
89C
2D_T
X10
_A12
EZR
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IO2
88C
2D_T
X11
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EZR
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IO1
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X12
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IO0
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I85
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14_A
16
EZR
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SS
I84
C2D
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15_A
17
EZR
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SE
T83
C2D
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00_A
18
EZR
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82C
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X01
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T81
C2D
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02_A
20
EZR
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80C
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X03
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EZR
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00X
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79C
2D_R
X04
_A22
EZR
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S78
C2D
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05_A
23
EZR
_NIR
Q77
C2D
_RX
06_A
24
EZR
_SD
N76
C2D
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07_A
25
GN
D75
C2D
_RX
08_A
26
EZR
P_R
X_D
ATA
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T74
C2D
_RX
09_A
27
EZR
P_R
X_C
LK_O
UT
73C
2D_R
X10
_A28
EZR
P_T
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72C
2D_R
X11
_A29
GN
D71
C2D
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12_A
30
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LK_I
N70
C2D
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13_A
31
GN
D69
C2D
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14_A
32
EX
TRE
G_B
D_A
68C
2D_R
X15
_A33
EX
TRE
G_O
UT_
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GN
D34
EX
TRE
G_S
N_A
66A
DC
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EF
35
EX
TRE
G_S
P_A
65A
DC
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EFG
ND
36
I2V
_IN
N_A
64A
DC
_IN
037
I2V
_IN
P_A
63A
DC
_IN
138
GN
D62
AD
C_I
N2
39
HV
DA
_IN
N_B
61A
DC
_IN
340
HV
DA
_IN
P_B
60G
ND
41
HV
DA
_IN
N_A
59D
AC
_RE
F42
HV
DA
_IN
P_A
58D
AC
_RE
FGN
D43
GN
D57
DA
C_O
UT0
44
CP
_NE
G_B
56D
AC
_OU
T145
CP
_PO
S_B
55D
AC
_OU
T246
CP
_NE
G_A
54D
AC
_OU
T347
CP
_PO
S_A
53G
ND
48
CP
_OU
TA_A
52ID
AC
_A49
CP
_OU
T_A
51ID
AC
_B50
J2U
DP
MC
U H
2
UD
P D
C H
EA
DE
R
CM
OS
CLK
_XTA
L2_A
100
GN
D1
CM
OS
CLK
_XTA
L1_A
99U
DP
BU
S_S
DA
_A2
LCD
_CO
M7_
A98
UD
PB
US
_SC
L_A
3
LCD
_CO
M6_
A97
EP
CA
_EC
I_M
OTO
R4
LCD
_CO
M5_
A96
EP
CA
_CH
0_M
OTO
R5
LCD
_CO
M4_
A95
EP
CA
_CH
1_M
OTR
6
LCD
_CO
M3_
A94
EP
CA
_CH
2_M
OTO
R7
LCD
_CO
M2_
A93
EP
CA
_CH
3_M
OTO
R8
LCD
_CO
M1_
A92
EP
CA
_CH
4_M
OTO
R9
LCD
_CO
M0_
191
EP
CA
_CH
5_M
OTO
R10
LCD
_SE
G39
_A90
HV
GP
IO00
11
LCD
_SE
G38
_A89
HV
GP
IO01
12
LCD
_SE
G37
_A88
HV
GP
IO02
13
LCD
_SE
G36
_A87
HV
GP
IO03
14
LCD
_SE
G35
_A86
HV
GP
IO04
15
LCD
_SE
G34
_A85
HV
GP
IO05
16
LCD
_SE
G33
_A84
HV
GP
IO06
17
LCD
_SE
G32
_A83
HV
GP
IO07
18
LCD
_SE
G31
_A82
EM
IF_A
2319
LCD
_SE
G30
_A81
EM
IF_A
2220
LCD
_SE
G29
_A80
EM
IF_A
2121
LCD
_SE
G28
_A79
EM
IF_A
2022
LCD
_SE
G27
_A78
EM
IF_A
1923
LCD
_SE
G26
_A77
EM
IF_A
1824
LCD
_SE
G25
_A76
EM
IF_A
1725
LCD
_SE
G24
_A75
EM
IF_A
1626
LCD
_SE
G23
_A74
EM
IF_A
1527
LCD
_SE
G22
_A73
EM
IF_A
1428
LCD
_SE
G21
_A72
EM
IF_A
1329
LCD
_SE
G20
_A71
EM
IF_A
1230
LCD
_SE
G19
_A70
EM
IF_A
1131
LCD
_SE
G18
_A69
EM
IF_A
1032
LCD
_SE
G17
_A68
EM
IF_A
933
LCD
_SE
G16
_A67
EM
IF_A
834
LCD
_SE
G15
_A66
EM
IF_A
735
LCD
_SE
G14
_A65
EM
IF_A
636
LCD
_SE
G13
_A64
EM
IF_A
537
LCD
_SE
G12
_A63
EM
IF_A
438
LCD
_SE
G11
_A62
EM
IF_A
339
LCD
_SE
G10
_A61
EM
IF_A
240
LCD
_SE
G09
_A60
EM
IF_A
141
LCD
_SE
G08
_A59
EM
IF_A
042
LCD
_SE
G07
_A58
EM
IF_W
RB
43
LCD
_SE
G06
_A57
EM
IF_O
EB
44
LCD
_SE
G05
_A56
EM
IF_A
LE45
LCD
_SE
G04
_A55
EM
IF_C
S0B
46
LCD
_SE
G03
_A54
EM
IF_B
E1B
47
LCD
_SE
G02
_A53
EM
IF_C
S1B
48
LCD
_SE
G01
_A52
EM
IF_B
E0B
49
LCD
_SE
G00
_A51
GN
D50
Fig
ure
18.C
8051
F85
0 U
DP
MC
U C
ard
Sch
emat
ic (
Rev
isio
n 2
00)
(5 o
f 5)
C8051F850-DK-UG
Rev. 0.3 25
10. Bill of Materials
Table 7. C8051F850 UDP MCU Card Bill of Materials
Reference Part Number Source DescriptionC1 C3 C17
C30C0603X7R100-105K Venkel 1 µF 10 V ±10% X7R 0603
C2 C4 C6 C10 C11 C12 C13 C15 C18 C28
C38
C0603X7R100-104K Venkel 0.1 µF 10 V ±10% X7R 0603
C20 C0603X7R100-103M Venkel 0.01 µF 10 V ±20% X7R 0603
C7 C16 C36 C37
C0603X5R6R3-475K Venkel 4.7 µF 6.3 V ±10% X5R 0603
D1 SP0503BAHTG Littlefuse 300 mW 20 V TVS SOT143
D3 D4 D5 D7 STPS140Z ST Semiconductor 1.0 A 40 V Schottky SOD-123
D6 MMSZ5245BT1 On Semiconductor 15 V 500 mW 15 V 5% Zener SOD-123
DS5 DS6 DS10
SML-LX0603IW LUMEX INC RED 30 mA LED 0603
DS9 LTST-C190TBKT LITE-ON Technology Corp
BLUE LED 0603
J1 J2 J3 J4 FX8-100P-SV1 Hirose Electric UDP DC Header
J23 5103309-1 Tyco 0.1 in. 5x2 Shrouded Header
J24 J25 J26 J27
TSW-105-07-T-D Samtec 0.1 in. 5x2 Header
J34 1729160 Phoenix Contact Analog Header Terminal Block 1x6
J35 TSW-102-07-T-D Samtec 0.1 in. 2x2 Header
J5 54819-0519 Molex USB Mini B
J6 RAPC722X Switchcraft Inc. Power Jack 5 A BARREL
J7 J32 TSW-103-01-L-D Samtec 0.1 in. 2x3 Header
JP2 TSW-102-07-T-S Samtec 0.1 in. 1x2 Header
JS1 JS2 JS3 JS4 JS5 JS6
JS9 JS10 JS11
SNT-100-BK-T Samtec Jumper Shunt
R118 CR0603-16W-1004F Venkel 1 MΩ 1/16 W ±1% ThickFilm 0603
R13 RV100F-30-4K1B-B10K-B301
Alpha (Taiwan) 10 kΩ 0.03 W 30% ThumbwheelPotentiometer
R15 R16 R122
CR0603-16W-7500F Venkel 750 Ω 1/10 W ±1% ThickFilm 0603
R19 CR0603-10W-1501F Venkel 1.5 kΩ 1/10 W ±1% ThickFilm 0603
DisclaimerSilicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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