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Sunplus Technology Co., Ltd. 1 Rev.: 1.0 1999.12.21

SPCA506A1USB A/V GRABBER

GENERAL DESCRIPTION

The SPCA506A1 provides a single chip solution to the AV-Capture application. It includes image compression

and data transaction units. The compressed data is transferred to the PC side via the USB bus. The

embedded USB controller is a hard-wired state machine. There is no need to use external microprocessors.

FEATURES

Support Decoded TV/YUV 4:2:2 image inputs

using Philips SAA7111A or SAA7113 or SAA7114,

Rockwell BT835 or BT 827B / BT829B TV decoder

chips

High Speed Compression support real time image

output

YUV 4:2:0 Video mode:

640 x 480 15 - 20 fps

352 x 288 25 - 30 fps

320 x 240 30 fps

240 x 180 30 fps

176 x 144 30 fps

160 x 120 30 fps

Snapshot mode: 640 x 480 YUV 4:2:0 data

EDO DRAM interface: 1M x 16 or 256K x 16

PC Interface: USB with built in tranciever

EP0: Default Endpoint, control type transaction

EP1: Isochronous type transaction for video mode

image data (interface 0)

EP2: Isochronous type transaction for audio

data (interface 1)

USB Suspend mode available.

Serial EEPROM: Vendor ID, Product ID,

Revision#,

Synchronous Serial Control interface

3.3V power supply

128 pins QFP packages (14 x 20 x 2.75mm)

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SPCA506A1

BLOCK DIAGRAM

GENERAL DESCRIPTION

The system receives and processes image data from TV decoder chips. The image data is then further

compressed by the Compression block and stored in the DRAM. The data is then read back from the DRAM

and transmit to the USB bus via the USB controller. The Synchronous Serial Control blocks programs the TV

decoder chips to generate the appropriate input image format. The detailed function of each block is described

in the following subsection.

COMPRESSION CONTROLLER

Input/Output Image Formats

Input image: YUV 4:2:2 input image format.

Output image: It may generate various output image formats as list in the following table:

Mode Image Type

640 x 480 YUV 4:2:0 (compression supported)






640 x 480 YUV 4:2:2

640 x 480 YUV 4:2:0

YUV 4:2:0 type images may be either compressed or non-compressed; while other type images will always

be non-compressed.

Snap Control

A snap picture may be obtained by pulling down the snapnn pin of the chip or by writing to an internal snap

register in the chip. Besides, two alternating snap control schemes are implemented for snapping a

picture: one is software dominated; the other is hardware dominated. The software dominated control

scheme is designed for the application software which can not immediately adjust the display window size

according to the image type in the property byte of the incoming image frame.

Software dominated control scheme (Un-toggle control):

When software dominated control scheme is selected, 8 image types are defined. User may select

any image type to play a motion picture. When the snap button is pressed, either by pulling down the

snapnn pin or writing to the snap register, the IC will keeps playing motion pictures according to the

image type selected . The only difference is the snap bit in the property byte for that image frame is set

to 1. Then, the application software may detect this snap bit turn on and snap the image frame.

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SPCA506A1

Hardware dominated control scheme (Toggle control):

When hardware dominated control scheme is selected, 6 image types are defined as video modes toplay motion pictures and 4 image types are defined as snap modes to capture a single image frame.

User may select one image type for video mode and one for snap mode respectively. Video mode and

snap mode may toggle dynamically during playing. The IC is default in video mode and playing motion

pictures. When one of the snap buttons are pressed, the IC will stop playing motion pictures right after

the current image frame is transferred. Then the system will output a still image frame according to the

image type previously selected for snap mode. The snap bit in the property byte for this still image

frame will be set as 1. After that, the system will immediately resume to play motion pictures according

to the image type previously selected for video mode.

DRAM CONTROLLER

The 1M x 16bit DRAM is used as the temporary buffer for the compression controller and as the ISO packet FIFO

for the USB controller. The DRAM controller must schedule all the requests to satisfy the bandwidth and latency

time requirements for various image operations in order to get better performance. The contents of the DRAM

can also be accessed with the USB vendor commands. The procedure is described below.

1. set the starting row address

2. set the starting column address

3. set the return row address

4. set the return column address

5. set the prefetEn bit in the control port 1 register if the operation is read

6. access the DRAM data port

The row and column addresses for the DRAM are internal generated by the chip.

USB CONTROLLER

There are two USB pipes built-in the chip: the first one is the default pipe which is used to handle the standard

and vendor commands. The other one is the ISO-IN pipe that is used to transmit the image data.

Pipe 0

The maximum packet size is 8 bytes for pipe 0. All standard commands except SET_DESCRIPTOR and

SYNCH_FRAME are supported. All the USB descriptors, except vendor ID, product ID and device release

number, are hardwired. The values of vendor ID, product ID and device release number, could be hard-

wired or loaded from an external serial EEPROM(AT93C66). The selection is done by an IO-trap pin,

refer to IO-pin section for further details. The string descriptors are also stored in the serial EEPROM.

The details about the data in the serial EEPROM are described in Section 4.7.

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SPCA506A1

Video ISO-IN pipe

For the video ISO-IN pipe, the host may issue standard commands to change its maximum packet size.To achieve the optimal system performance, the user must adjust the alternative interface setting based on

the image size and compression rate. The following table shows the maximum packet sizes for the

available alternative interface settings.

Alternative Interface Setting Maximum Packet Size for ISO IN Pipe (bytes)

0 0

1 128

2 3843 512

4 640

5 768

6 896

7 1023

Video ISO Packet Property byte:

Each image frame stream consists of a set of USB ISO packets. In the first USB ISO packet for an imageframe stream, several bytes are defined as property bytes to record the image type, compression scheme,

and snap approach for the image frame stream. Thus, software may identify each incoming image frame

stream.

There are ten property bytes for the start of frame packet. They are sequence byte, property byte 1,

property byte 2,.., property byte 8 and property byte 9. The other packets contains only the sequence byte.

The value of the sequence byte in the first packet of an image stream is 0X00, followed by sequence byte

0X01, 0X02, 0X03, etc. The last value of the property byte is 0XFE. The value will wrap around to

0X00 when it reaches 0XFE. 0XFF is a special value for the property byte which marks a drop packet, i.e.

no image data is in this packet.

Property Byte 1:

Bit Field Att Description

4:0 ImageType r Refer to the compression part in the section Internal register description

5 Reserved

6 SnapBit r Two alternating definitions for this bit may be selected by SnapControl field.

Under software dominated snap control (Un-toggle control):

When the hardware snap button or software snap button is pressed, this bit in

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the property byte of the next coming out image will be set to 1. It will become

0 for the next coming out image.

Under hardware dominated snap control (Toggle control):

When this bit is 1, the image type of the current coming out image will be one

of the 4 snap modes; when this bit is 0, the image type of the current coming

out image will be one of the 6 video modes.

7 SnapControl r Refer to the compression part in the section Internal register description

Property Byte 2:


0 CompEnable r Refer to the compression part in the section Internal register description

3:2 TurnPoint3A r Refer to the compression part in the section Internal register description

6:4 Threshold3D r Refer to the compression part in the section Internal register description

Property Byte 3:




Property Byte 4:


2:0 Quant3A r Refer to the compression part in the section Internal register description

6:4 Quant3D r Refer to the compression part in the section Internal register description

Property Byte 5:




Property Byte 6:


7:0 FramSequence r The input image frame sequence number

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Property Byte 7:


0 EdgeMode r Edge enhancement:

0: disable 1: enable

1 GammaEn r Gamma correction enable


2 AudioEn r The audio function


7:3 Reserved

Property Byte 8:


7:0 GPIO r General purpose IO

Property Byte 9:


7:0 Reserved

USB Power Control

According to the USB specification 1.0, no USB device may require more than 100 mA when first attached,

a configured bus-powered USB device attached to a self-powered hub may use up to 500 mA and all USB

devices must support a suspended mode that requires less than 500A. For the USB power budgeting,

there are three states designed in the chip: unconfigured, full-speed and suspend. The chip behavior in

the three states are described as follows:

Unconfigured: all output pins, except connecting to the USB transceiver and serial EEPROM pins, are

not driven and all bi-directional pins, except the GPIO pins, are pulled-down to 0.

Full-speed : all pins are normally operated.

Suspend : all output pins, except connecting to the USB transceiver pins, are not driven and the serial

EEPROM output pins and all bi-directional pins are pulled-down to 0. The internal clocks

are gated and unchanged and the clock driver pin is disabled.

There is a newly adding bit at the bit 15 in the control port 0 to enable the DRAM control. The default value

of this bit is zero that means the DRAM control is disabled. So the power for the DRAM must be turned offbefore this bit is enabled.

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SERIAL EEPROM CONTENT

There is an interface to access the 256x16 serial EEPROM (93c66) that can beused to store some data aboutthe device.

Address Purpose

0 Vendor ID

1 Product ID

I2C INTERFACE

The i2c interface is used to program TV decoder IC(SAA7111).

The write sequence:

S Slave Address + wb ACKs Sub Address ACKs Data ACKs P

The read sequence:

S Slave Address + wb ACKs Sub Address ACKs

Sr Slave Address + r ACKs Data ACKm P

Or

S Slave Address + wb ACKs Sub Address ACKs P

S Slave Address + r ACKs Data ACKm P

Where S is start condition, ACKs is acknowledge from slave, P is stop, Sr is repeat start condition, and ACKm is

acknowledge from master.

TV INTERFACE

TV interface is used to receive the digital output data from TV decoder. The format is CCIR 601/656 YUV 422.

Both single channel and dual channels are supported.

Single channel (TV-Y) : Cb Y Cr Y Cb Y Cr Y

Dual channels : TV-Y : Y0 Y1 Y2 Y3 .

TV-UV : Cb0 Cr0 Cb1 Cr1 ..

In CCIR 601, the active signals (horizontal active or vertical active or data valid) are needed to inform the active

region. In CCIR 656, the active signals can be extracted from data streams according to SAV/EAV code.

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SPCA506A1

IO TRAP DESCRIPTION

The Output pins ma[0], ma[1], ma[2] and ma[3] are used as IO-trap pins. These signals can be pulled high orlow on the system board to configure the SPCA506A1 operation. The hardware setting is as follows:

Trap Pin Function

ma[0] The vendor/product ID selection:

0: from the serial EEPROM

1: by hardwire

ma[1] The USB transceiver selection:

0: internal1: external

ma[2] The interface 1 (audio)

0: disable

1: enable

ma[3] test mode

0: normal mode

1: test mode

INTERNAL REGISTER DESCRIPTION

Vendor commands are used to access the internal registers that are categorized to ten groups that are selected

by the bRequest byte in the setup packet. The register size in the first three groups are 16 bits and the register

size in the other groups are 8 bits. The detailed description for vendor command is shown as follows:

bmReqType bRequest wValue wIndex WLength

EEPROM 0x41 / 0xc1 (*) 0 data register index 0 / 2 (**)

Memory 0x41 / 0xc1 1 data register index 0 / 2

USB Control 0x41 / 0xc1 2 data register index 0 / 2

Global Control 0x41 / 0xc1 3 data register index 0 / 1

Compress 0x41 / 0xc1 4 data register index 0 / 1

Reserved 0x41 / 0xc1 5 data register index 0 / 1

Reserved 0x41 / 0xc1 6 data register index 0 or 8 / 1 or 8

Synchronous

Serial Control0x41 / 0xc1 7 data register index 0 / 1

TV 0x41 / 0xc1 8 data register index 0 / 1

Audio 0x41 / 0xc1 9 data register index 0 / 1

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* : 0x41 for write , 0xc1 for read.

** : wLength specifies the data size in the DATA phase of an USB setup transfer. When writing to a register,the data is stored in the wValue. So the value of wLength is always zero. When reading a register, there

are one, two or eight bytes data returned in the data phase. If burst writing to a register, the data will be

transferred in the other data phase. So the value of wLength is eight.

EEPROM CONTROLLER REGISTER

Mode Windex-High Windex-Low

read 8h00 access address

write 8h01 access addresswrite disable 8h02 dont care

write enable 8h03 dont care

MEMORY CONTROLLER REGISTER

DRAM Access Data Port (0)


15:0 Data[15:0] r/w The host accesses the data of DRAM.

The Start Row Address of DMA (1)


9:0 RowAdr r/w The starting row address to access DRAM.

15:10 Reserved

The Start Column Address of DMA(2)


9:0 ColAdr r/w The starting column address to access DRAM.

15:10 Reserved

The Return Row Address of DMA (3)


9:0 RowAdr r/w The return row address to access DRAM.

15:10 Reserved

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The Return Column Address of DMA (4)


9:0 ColAdr r/w The return column address to access DRAM.

15:10 Reserved

USB CONTROL REGISTER

Control (0)


0 ISOEn r/w The ISO packet machine

0: disable

1: enable

1 PrefetEn r/w Prefetch DRAM enable for the USB host

0: disable

1: enable

15:2 Reserved

Test (1)


0 BlkISODPkt r/w Block ISO drop packet

0: disable

1: enable

1 DPThrSel r/w Drop packet threshold selection:

0: the data in ISO FIFO is not greater than four

1: the data in ISO FIFO is not greater than one

15:2 Reserved

Vendor ID in Serial EEPROM (2)


15:0 VID[15:0] r The vendor ID in the serial EEPROM

Product ID in Serial EEPROM (3)


15:0 PID[15:0] r The product ID in the serial EEPROM

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GLOBAL CONTROL REGISTER

Addr Bit Field Att Description

0 0 IDSel r The vendor/product ID selection

0: auto load from the serial EEPROM

1: hardwire value

1 ExtTrxEn r USB transceiver selection

0: internal transceiver 1: external transceiver

4:2 Reserved

5 Synchronous

Serial ControlEn

r/w Synchronous Serial Control function


6 AudioEn r/w The audio function


7 Reserved

1 0 BlkUSBReset r/w Block the USB reset to reset the device


1 BlkSuspend r/w Block USB suspend


2-3 Reserved r/w4 DramOutEn r/w The DRAM controller output enable


5 IntRsmCntEn r/w Internal resume counter enable


7:6 Reserved

2 7:0 Reserved r/w

3 6:0 GPIOO r/w The general purpose I/O output data

bit0: Synchronous Serial Control clockbit1: Synchronous Serial Control data

other bit: GPIOO

4 6:0 GPIOOENN r/w The general purpose I/O output enable (low active)

0: output enable 1: output disable

5 6:0 GPIOI r The general purpose I/O input data

bit1: Synchronous Serial Control data

other bits: GPIOI

6 1:0 Reserved r/w

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SPCA506A1

COMPRESS REGISTER


0 4:0 ImageType r/w The image type to be transferred to PC host for display. Two

alternating definitions for this register may be selected by

SnapControl field.

Under software dominated snap control (Un-toggle control)

Bits [3:0]:

0000: mode 0 --- 640x240 YUV 4:2:0 continuous processing.

0001: mode 1 --- 352x288 YUV 4:2:0, continuous processing0010: mode 2 --- 320x240 YUV 4:2:0, continuous processing

0011: mode 3 --- 240x180 YUV 4:2:0, continuous processing



1000: mode 6 --- Reserved

1001: mode 7 --- 640x240 YUV 4:2:2, discrete processing

1010: mode 8 --- Reserved

1011: mode 9 --- 640x240 YUV 4:2:0, discrete processing

else : Reserved

Bits [4]: Reserved

Under hardware dominated snap control (Toggle control)

Bits [2:0]:

000: video mode 0 --- 640x240 YUV 4:2:0

001: video mode 1 --- 352x288 YUV 4:2:0

010: video mode 2 --- 320x240 YUV 4:2:0

011: video mode 3 --- 240x180 YUV 4:2:0

100: video mode 4 --- 176x144 YUV 4:2:0

101: video mode 5 --- 160x120 YUV 4:2:0

else: reserved

Bits [4:3]:

00: snap mode 0 --- Reserved

01: snap mode 1 --- 640x240 YUV 4:2:2

10: snap mode 2 --- Reserved

11: snap mode 3 --- 640x240 YUV 4:2:0

7:5 Reserved

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1 0 SnapControl r/w 0: Software dominated snap control (Un-toggle control)

1: Hardware dominated snap control (Toggle control)

1 HwSnapButnSta r The status for the hardware snap button

Set : when the hardware snap button is pressed

Cleared : when the register is read

2 HwSnapButnVldChk r/w Hardware snap button valid check

0: Disable

1: Hardware snap button valid only when it keeps more than 2.6ms

3 SwSnapButton w When 1 is written to this bit, the hardware will emulate the behaviorjust like the hardware snap button pressed. When 0 is written, no

effect. When read, always return 0.

4 Dram1M r/w 0: means DRAM 256Kx16.

1: means DRAM 1Mx16. (The Compress unit may process the

image in the larger DRAM buffer region to get better image quality)

5 Reserved r/w

6 TVFieldProcess r/w 0: frame mode: process both fields for each frame. This mode

doesnt support 640x240 TV output.1: field mode: process only one field for each frame.

7 Reserved

2 0 Line8Image r/w 0: normal

1: only 8 lines of processed data is output by the compress unit for

each image frame, whatever the image type is set.

1 HFiltDram r/w 0: normal

1: only horizontal processing is activated by the compress unit for

each image frame

7:2 Reserved

7:3 7:0 Reserved

8 0 CompEnable r/w 0: without compression

1: with compression

7:6 Reserved

9 1:0 TurnPoint3A r/w 3A band normalization

00: T=0

01: T=32

10: T=64

11: T=96

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6:4 Threshold3D r/w 000: threshold = 0

001: threshold = 2

010: threshold = 4

011: threshold = 8

100: threshold = 16

101: threshold = 32

else: threshold = 0

a 2:0 Threshold2D r/w Refer to Threshold3D field.

6:4 Threshold1D r/w Refer to Threshold3D field.b 2:0 Quant3A r/w 000: quantization factor = 1

001: quantization factor =2

010: quantization factor = 4



else: quantization factor = 1

6:4 Quant3D r/w Refer to Quant3A field.

c 2:0 Quant2D r/w Refer to Quant3A field.6:4 Quant1D r/w Refer to Quant3A field.

SYNCHRONOUS SERIAL CONTROL REGISTER

Addr Bit Field Att Description Default

0 7:0 DATA[7:0] r/w The data buffer for Synchronous Serial Control

transfer. Writing this buffer will initiate

Synchronous Serial Control write sequence.

8h00

1 7:0 ADDR[7:0] w The register address 8h002 7:0 PREFETCH[0]

RSTA[1]

w Writing this bit will initiate Synchronous Serial

Control read sequence Synchronous Serial

Controls repeat start condition when rsta is high,

otherwise Synchronous Serial Control will stop

then start.(only work in Synchronous Serial Control

read)

1h0

1h0

3 7:0 BUSY[0] r Busy is high when Synchronous Serial Control

read or write.

1h0

4 7:0 SLA[7:0] w The slave address 8h00

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AUDIO CONTROL REGISTER

Control (0)Bit Field Att Description

0 AudioEn r/w When high, the audio function is enabled.

1 AudOutReg r/w When low to high, the value in the output address and data (only in the write

mode) will be transmitted

2 AudInRegClr r/w When high, the valid bit for the audio in register will be cleared.

3 WRstCodec r/w When high, the audio reset pin will be forced to the low state and the audio will

be into warm reset state.

4 CRstCodec r/w When high, the audio sync pin will be forced to the high state and the audio

device will be into cold reset state.

5 ATETest r/w When high, the audio data out pin will be forced to the high state and the audio

device will be into ATE test state. The audio reset pin must be forced to low

state before the audio data out pin is in high state and must be forced to high

state after the audio data out pin is from low to high.

6 AudFIFOTest r/w When high, the CPU can directly read or write audio FIFO.

7 Reserved

Output Address(1)


7:0 AudOutAddr r/w 7: ( 1 = read, 0 = write)

6:0 The output address to read/write audio register

Write Data Low byte(2)


7:0 AudWrData r/w The data to write audio register (low byte)

Write Data High byte(3)


7:0 AudWrData r/w The data to write audio register (high byte)

Input Address(4)


6:0 AudInAddr r The register address in audio input frame

7 Reserved

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SPCA506A1

Input Data Low Byte(5)


7:0 AudInData r The register data in audio input frame (low byte)

Input Data High Byte(6)


7:0 AudInData r The register data in audio input frame (high byte)

Status(7)


0 AudOutBusy r When high, it indicates the process to out audio register is still going.

1 AudInVld r When high, it indicates there is valid data in the audio input address and data

registers and the following input register data will be skipped.

7:2 Reserved

PIN DESCRIPTION

MnemonicPIN

No.

Type PIN Description Initial SuspendRegister

Enable

AP Consider.

uvdd 1 Pusb

dm 2 B

dp 3 B

uvss 4 Pusb

tvuv[0]/

dpo

5 BL TV UV data bus / test

signals /External USB

transceiver dpo

OUT when

ma[1] trap 1

OUT when

ma[1] trap 1

tvuv[1]/dmo

6 BL TV UV data bus / testsignals /External USB

transceiver dmo

OUT whenma[1] trap 1

OUT whenma[1] trap 1

tvuv[2]/

usboenn



transceiver usboenn

OUT when

ma[1] trap 1

OUT when

ma[1] trap 1

tvuv[3]/

suspend



transceiver suspend

OUT when

ma[1] trap 1

OUT when

ma[1] trap 1

tvuv[4]/

dpi

9 IHBH TV UV data bus / test


transceiver dpi

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SPCA506A1

MnemonicPIN

No.


Enable

AP Consider.

tvuv[5]/

dmi

10 IL BL TV UV data bus / test


transceiver dmi

tvuv[6]/

din

11 IL BL TV UV data bus / test


transceiver din

tvuv[7] 12 IL BL TV UV data bus / test

signalsgvdd 13 Pglob

gvss 14 Pglob

tvy[0:7] 15-22 ILBL TV Y data bus/ test

signals

gvdd 23 Pglob

tvhref 24 ILS TV horizontal reference

signal

tvvref 25 ILS TV vertical referencesignal

tvfield 26 ILS TV field odd/even

tvdvalid 27 ILS TV data valid signal

tvck 28 IL

IC2x2

TV clock (x1, 13.5M Hz)

tvckk 29 IL

IC2x2

TV clock (x2, 27M Hz)

tvvd30

ILS TV vertical sync signaltvhd 31 ILS TV horizontal sync

signal

dvdd 32 Pint

dvss 33 Pint

gpio[0]/

scl

34 BS General purpose IO

port / Synchronous

Serial clock

Tri Tri Rgpio,

Ri2c

External pull high

gpio[1]/

sda

35 BS General purpose IO

port / Synchronous

Serial data

Tri Tri Rgpio,

Ri2c

External pull high

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MnemonicPIN

No.


Enable

AP Consider.

ovdd 66 Pio

md[6:15] 67-76 BL5 DRAM data Tri, L Tri, L Rdram Tri-state during

DRAM power off

dvdd 77 Pint

dvss 78 Pint

ecs 79 BL EPROM chip select Tri, L EPROM will be tri-

stated during

power-on resetperiod; while not

tri-stated during

suspend

esk 80 TO EPROM clock Tri

edi 81 TO EPROM data input Tri

edo 82 IL EPROM data output

test[4]

aurstnn

83 TO Audio reset to Codec Tri Tri Tri-state during

audio chip poweroff

test[3]

ausync

84 TO Auiod sync to Codec Tri Tri Tri-state during

audio chip power

off

test[2]

audin

85 IL5 Audio data input from

Codec

test[1]

aubclk

86 IL5 Audio bit clock from

Codec

test[0]

audout

87 TO Audio data output to

Codec

Tri Tri Tri-state during

audio chip power

off

xtalin 88 XI Crystal pad

xtalout 89 XO Crystal pad Oscil. Out 1

dvdd 90 Pint

dvss 91 Pint

rstnn 92 IS Global reset signal to

the chip

External pull high

snapnn 93 IS Snapshot signal External pull high

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MnemonicPIN

No.


Enable

AP Consider.

nc 94 ILS External VD

nc 95 ILS External HD

nc 96-99 TO Reserved Tri Tri Rtg

ovdd 100 Ptg


ovss 103 Ptg


ovdd 111 Ptg


gvdd 117 Pglob

gvss 118 Pglob

nc 119-128 IL Reserved

Note. PAD type symbol definition:

I: input (need external pull high/low) TO: tri-state output

O: output BL: bi-direction, pull low

B: bi-direction (need external pull high/low) BS: bi-direction, smith trigger

P: power pad BL5: bi-direction, pull low, 5V tolerant

XI: crystal input pad Ptg: power pad for output

XO: crystal output pad Pio: power pad for I/O buffer

IL: input, pull low Pint: power pad for internal core logic

IH: input, pull high Pglob: power pad for both I/O buffer & internal core logic

IS: input, smith trigger Pusb: power pad for USB

ILS: input, pull low, smith trigger

AC/DC CHARACTERIZATION

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VT -0.4 to 4.0 V

Supply Voltage relative to VSS VDD -0.4 to 4.0 V

Short Circuit Output Current IOUT 50 mA

Power Dissipation PD

0.2 W

Operating Temperature TOPT 0 to +70 C

Storage Temperature TSTG -55 to 125 C

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RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min. Typ. Max. Unit

Supply Voltage VDD 3.1 3.3 3.45 V

Input low voltage VIL -0.3 - 0.3VDD V

Input high voltage VIH 0.7VDD - VDD+10% V

DC CHARACTERISTICS

TA = 0C - 70C, VDD = 3.3V 5%, VSS = 0V

Symbol Parameter Min. Typ. Max. Units Test Condition

VOL Output low voltage - - 0.4 V 4mA buffer

IOL = 4mA

8mA buffer

IOL = 8mA

12mA buffer

IOL = 12mA

VOH Output high voltage 2.4 - - V 4mA buffer

IOH = -4mA

8mA buffer

IOH = -8mA

12mA buffer

IOH

= -12mA

IDD

(unconfigured)

Power supply current - 80 - mA fop = 48MHz

IDD

(normal)

Power supply current - 100 - mA fop = 48MHz

IDD

(suspend)

Power supply current - 10 - uA

IIL Input leakage current - 10 - A VIN = 0V

Notes: (1) All DC electrical characteristics are measured at 25C

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SPCA506A1

AC CHARACTERISTICS

1. DRAM Single Read Timing :

RASNN

MA

tRP

OENN

MD

tRCD

CASNNtCAS

row

address

column

address

column

address

tASR tRAH tASC tCAH

tROD tROD

tCAC

valid

data

Symbol Parameter Min. Typ. Max. Units Notes

tRCD RAS to CAS delay - 60 - ns

tRP RAS recovery time - 40 - ns

tCAS CAS pulse width 10 20 - ns

tASR Address to RAS setup time - 40 - ns

tRAH RAS to address hold time - 40 - nstASC Address to CAS setup time - 20 - ns

tCAH RAS to address hold time - 20 - ns

tROD RAS to OE delay - 40 - ns

tCAC CAS to valid data delay - - 30 ns

2. DRAM Page Mode Read Timing :

RASNN

MA

OENN

MD

CASNN

row

address

column

address 1

column

address 2

valid

data 1

tCP

valid

data 2


tCP CAS recovery time - 20 - ns

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SPCA506A1

3. DRAM Single Write Timing :

RASNN

MA

tRP

WRNN

MD

tRCD

CASNNtCAS

row

address

column

address

column

address

tASR tRAH tASC tCAH

valid

data

tDS tDH


tRCD RAS to CAS delay - 60 - ns

tRP RAS recovery time - 40 - ns

tCAS CAS pulse width - 20 - ns

tASR Address to RAS setup time - 40 - ns

tRAH RAS to address hold time - 40 - ns

tASC Address to CAS setup time - 20 - ns

tCAH RAS to address hold time - 20 - ns

tDS data to CAS setup time - 20 - ns

tDH data to CAS hold time - 20 - ns

4. DRAM Page Mode Write Timing :

RASNN

MA

WRNN

MD

CASNN

row

address

column

address 1

column

address 2

valid

data 1

tCP

valid

data 2

tDS tDH tDS tDH


tCP CAS recovery time - 20 - ns

tDS data to CAS setup time - 20 - ns

tDH data to CAS hold time - 20 - ns

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SPCA506A1

5. Refresh Cycle Timing :

CASNN

RASNN

tCSR tCHR

tCAS


tCAS CAS low pulse width - 80 - ns

tCSR CAS to RAS setup time - 40 - ns

tCHR RAS to CAS hold time - 40 - ns

6. Serial EEPROM Timing :

ECS

EDI

EDO (Read)

EDO (Program)

ESK

tCSS tSKH tSKL tCSH

tDIS tDIH

tPD0 tPD1 tDF

tDF

tCS

tSV


tSKH ESK High Time - 2.5 - us

tSKL ESK Low Time - 2.5 - us

tCS Minimum ECS Low Time - 5 - us

tCSS ECS Setup Time - 2.5 - us

tDIS EDI Setup Time - 2.5 - us

tCSH ECS Hold Time - 2.5 - us

tPD1 Output Delay to 1 0 - 2.5 us

tPD0 Output Delay to 0 0 - 2.5 us

tSV ECS to Status Valid 0 - 5.0 us

tDF ECS to EDO in Z 0 - 5.0 us

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SPCA506A1

PACKAGE ASSIGNMENT AND DIMENSION

PACKAGE Assignment

112

128 pin package

2 3 4 5 6 710

9811

12

13

14

15

16

17

18

23

22

21

24

20

19

25

111

113114

110109108

105106107

104103

414243

3940

44454647484950

1

75

74

73

72

71

70

69

68

67

94

65

gvss

gvdd

md0md1

rasnn

casnnmoennmwenn

ovddovss

ncncncnc

ncnc

ncnc

nc

gvdd

dvdd

dvss

ncncnc

nc

nc

ncnc

nc

nc

ovdd

gvdd

ovss

gvss

uvdd

dm

dp

uvss

93

92

89

91

90

88

87

86

85

84

83

82

81

66

120119118117116115

IO buffer power/ground

internal cell power/ground

nc

nc

26

27

28

29

30

76

77

78

79

80

dvssdvdd

USB cell power/ground

33

32

31

34

35

36

37

38

5152535455565758596061626364

95

102

101

96

97

98

99

100

122122121

123

124124

128127126125

tvuv0/dpo

tvuv1/dmo

tvuv2/usboenn

tvuv3/suspend

tvuv4/dpi

tvuv5/dmi

tvuv6/din

tvuv7

tvy0

tvy1

tvy2

tvy3

tvy4

tvy5

tvy6

tvy7

dvdd

dvss

tvhref

tvvref

ncncncncncncncncncnc

tvfield

tvck

tvhd

tvckk

ma0ma1ma2ma3ma4ma5ma6ma7ma8ma9

gpio1/sda

gpio0/scl

gpio2

gpio3

gpio4

md2md3md4md5

md6

md7

md8

md9

md10

md11

md12

md13

md14

md15

rstnn

snapnn

xtalin

xtalout

edi

edo

ecs

esk

tvvd

dvss

dvdd

ovdd

ovss

gpio5

ovdd

ausync

aubclk

audin

audout

aurstnn

gpio6

tvdvalid

Global power/ground

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SPCA506A1

PACKAGE Dimension

AA2

D

D1

D2

E2E1E

e

b

SUNPLUS

SPCA506A1

YYWW

Symbol Min. Nom. Max.

A - - 3.4

A2 2.5 2.72 2.9

E 17.20 17.20 17.20

E1 14.00 14.00 14.00

E2 12.50 12.50 12.50

D 23.20 23.20 23.20

D1 20.00 20.00 20.00

D2 18.50 18.50 18.50

e 0.50 0.50 0.50

b 0.17 0.20 0.27

Unit: millimeter

NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in

order to improve the design and performance and to supply the best possible product.

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SPCA506A1

DISCLAIMER

The information appearing in this publication is believed to be accurate.Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions

stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description

regarding the information in this publication or regarding the freedom of the described chip(s) from patent

infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR

ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any

time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in

this publication are current before placing orders. Products described herein are intended for use in normal

commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military

equipment or medical life support equipment, are specifically not recommended without additional processing by

SUNPLUS for such applications. Please note that application circuits illustrated in this document are for

reference purposes only.

Date post:	02-Apr-2018
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