SSV SummitNovember 2013
Cadence Tempus™ Timing Signoff Solution
2 © 2013 Cadence Design Systems, Inc. All rights reserved
• Signoff closure up to 40% of the design flow
• Need faster runtimes
• Capacity for +100M cell designs with 100s of timing views
• Better accuracy to reduce pessimism, power, area
Industry needs for next generation signoff
65nm 40nm 28nm 20nm
Design Flow ComponentsSignoff P&R Front End
Technology NodeD
esig
n C
ycle
Dis
trib
utio
n %
3 © 2013 Cadence Design Systems, Inc. All rights reserved
The Tempus™ Timing Signoff Solution
Tempus – It’s about TIME
• Up to 10X reduction in closure time• Placement and routing aware• Unlimited MMMC capacity
CLOSURE• Massively parallelized computation• Scalable to 100s of CPUs• Optimized data structures
PERFORMANCE
• Up to 10X faster path-based analysis (PBA)• Advanced process modeling• TSMC-certified accuracy
ACCURACY
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• Optimized multi-threading
• Distributed processing
• Incremental & hierarchical analysis
• Concurrent multi-mode multi-corner analysis
• Parallelized path based analysis
Performance backgroundStacked performance enablement
MMMCConcurrency
Incremental Analysis
Distributed Processing
Flat Single View (Multi-Threading)
Technology
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• Combines multi-threading with distribution
• Simple setup– User specifies desired resources
• Parallelization transparent to user
• Up to 50M cells analyzed in one hour
• Low memory footprint
Performance metrics Parallelized processing
MMMCConcurrency
Incremental Analysis
Distributed Processing
Flat Single View (Multi-Threading)
6 © 2013 Cadence Design Systems, Inc. All rights reserved
• Analyzes all modes and corners in one timing session
• Runs on one compute server
• More than 2X faster with same hardware– Less than 20% memory overhead
per additional timing view
• Reduces hardware resource requirement
Concurrent MMMC view analysis
MMMCConcurrency
Incremental Analysis
Distributed Processing
Flat Single View (Multi-Threading)
7 © 2013 Cadence Design Systems, Inc. All rights reserved
• Graph based analysis is fast but inherently pessimistic
• Path based analysis is slow but reduces pessimism– Accurate transitions and
derates
• Tempus solves PBA reporting runtimes– Parallelized computation
Path-based analysis (PBA)Reduced pessimism and runtime
0 100 200 300 400 500 600
-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
PBA reduces pessimism
AOCV PBA Slack
AOCV Graph Based
Path Number
Path
Sla
ck
Pessimismreduction
8 © 2013 Cadence Design Systems, Inc. All rights reserved
• Full timing/optimization solution
• Delay and SI
• Distributed MMMC
• Physically aware
• Setup/hold/DRV/leakage optimization– Path or graph based
Tempus timing closure
TempusDistributed
MMMC delay
calculationand STA
Physically-aware
optimization
Hold, DRV, setup,
leakage
Place and route
Timing closed
2-3Iteration
Physicalview(LEF/ DEF)
Physicallyaware ECO
9 © 2013 Cadence Design Systems, Inc. All rights reserved.
Tempus resonates with users
What we said…
Community feedback (courtesy of DeepChip)…
10 © 2013 Cadence Design Systems, Inc. All rights reserved
• Presented at ARM® TechCon 2013
• Cortex®-A12 testchip– 28nm SLP Technology
• Close collaboration– ARM, Global Foundries,
Cadence• Full Cadence flow
– Final signoff with Tempus!• Key Tempus technologies
– MMMC analysis– Physically aware optimization
Global Foundries tapeout success
11 © 2013 Cadence Design Systems, Inc. All rights reserved.
• Cadence is solving the design complexity challenge– Eliminating the signoff bottleneck – Enables power, performance and time-to-market goals
• Tempus™ accelerates timing analysis and closure by weeks– As much as 10x faster – Handles 100’s of millions of cells– Optimizes timing across hundreds of views
• Strong customer demand– Multiple evaluations and customers
• Early tapeout success
In summary
More to come!
12 © 2013 Cadence Design Systems, Inc. All rights reserved
"Cadence, Encounter, Tempus, Virtuoso and the Cadence logo are trademarks of Cadence Design Systems, Inc. All other trademarks and logos are the property of their respective holders."