Ursula Bassler 1integration meeting 22 Aug 2001

Calorimeter TimingDetector +

PreAmp-Boxes

Platform:

BLS cards

MCH:Trigger boards

MCH:

ADC cards

MCH:Trigger framework

MCH:Timing & Control Boards

timing w.r.t accelerator

done during 18 strores

cable length –fixed

scl-cable: length adjustable: ~10ns

delays/trigger tower

jumpers/ BLS crate: ~5ns

samplingtime byRF-bucket in FPGA

Reiner Hauser 2integration meeting 22 Aug 2001

Cal Timing: L1 timingVerification of cable between from Detector to Trigger Summers (BLS-boards): CC uniform

ECN, ECS: different regions cable from trigger summers to trigger receiver boards (MCH):

3 different lengths (ECN, CC, ECS) – same as in Run Ifiner adjustment for different EC regionsadjustment possible for each trigger tower with delay line

em

Dan Edmunds 3integration meeting 22 Aug 2001

Trigger/Read Out timing

flash ADC Read Out adjusted to peak of the Trigger Pickoff

measurements done for a sample of em/had channels in CC

same value used everywhere

systematic adjustment comparing L1Cal-Read Out by varying the Trigger by +/- 1 RF-bucket

final L1Cal trigger Read Out needed

Ursula Bassler 4integration meeting 22 Aug 2001

Timing Studies: triple sampling

signal

time

0 +1-1

Triple sampling runs: comparison of energy measured at the nominal position, 132ns earlier/later

ratios allow to determine time offset more precise timing from comparison with

Spice model

Ursula Bassler/Melissa Ridel 5integration meeting 22 Aug 2001

Timing: Model Validation

type A preamp.

type B preamp.

type D preamp.

type E preamp.

Model validation:comparing pulser calibration signal with Spice Model

Model optimisation:pulse reflexion measurements on the detector

SimulationMeasurement

em

had

verification underway

Ursula Bassler 6integration meeting 22 Aug 2001

Timing: cryostat comparison

early/ nominal

late/ nominal

CC ECN

ECSafter 1st adjustmentfrom scope measurements:3 cryostats and all crates show essential the samebehavior !

Mingcheng Gao, Columbia NY 7integration meeting - 22 Aug. 2001

Timing Studies: delay scan

late/nominal

early/nominal

+ 81 ns + 97 ns + 113 ns

=0.77

=0.69

=0.78=0.82=1.04

=0.64=0.61=0.39

at first look an offset of 113 ns seems correct

Ursula Bassler 8integration meeting 22 Aug 2001

Status & Outlook

yesterday: new FPGA code, with 6 RF-buckets shift (113 ns)

analysis of triple sampling data underway

Spice Model validation

extraction of time-offset from comparison with Spice Model

separation of measurement with different PreAmp Types

Fine Adjustment for each Quadrant October shutdown(?):

fine adjustment for each BLS crate? Trigger/Precision Read-Out comparisons a.s.a.p