Capacitorless LDO voltage regulators

1880 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 9, SEPTEMBER 2012

Robust Miller Compensation With Current AmplifiersApplied to LDO Voltage Regulators

Gianluca Giustolisi, Member, IEEE, Gaetano Palumbo, Fellow, IEEE, and Ester Spitale

Abstract—This paper presents a general methodology for com-pensating LDO regulators which exploits a current amplifier to ef-fectively multiply the Miller capacitor. After a general theoreticalanalysis that takes into account both the external and internal loopstability, it is examined the feasibility of applying this kind of com-pensation in different LDO applications, showing the role of thedesign parameters and proposing a specific design procedure foreach practical cases which differ in terms of load capacitance andthe adoption of a decoupling voltage buffer. Simulations and exper-imental results which validate the methodology are also included.

Index Terms—CMOS analog integrated circuits, frequency com-pensation, low drop-out voltage regulators.

I. INTRODUCTION

I N THE LAST ten years, power management in integratedcircuits (ICs) has been gaining more and more attention

thanks to the growing demand for portable battery-poweredelectronic devices such as cellular phones, pagers, camerarecorders, laptops, and PDAs. In such a scenario, where thepower consumption reduction is a mandatory target, the lowdrop-out linear voltage regulator (LDO) has become one of themost important building blocks as it can provide regulated andaccurate supply voltages [1], [2].Linear regulators, and in particular LDOs, are based on a

feedback topology which is made up of a voltage reference,an error amplifier a power device and a feedback resistive net-work. The feedback topology requires frequency compensationto achieve closed-loop stability and, although its small signalequivalent circuit is conceptually similar to a two-stage am-plifier, it is harder to be compensated. This is due to the largevalues of the capacitances involved and to the wide output cur-rent range which causes the poles to span over several decades[3]–[8].The literature has proposed several compensation techniques

which concern and apply to two main classes of LDOs: the highcapacitive load (HL) and the low capacitive load (LL) class.The HL class includes those LDOs designed to provide cur-

rent to external (off-chip) circuitry [1], [2], [9]–[12]. In this case,a large capacitive load (in the micro-farad range) is put at theoutput node in order to both compensate the circuit and to re-

Manuscript received July 29, 2011; revised November 09, 2011; acceptedDecember 19, 2011. Date of publication May 25, 2012; date of current versionAugust 24, 2012. This paper was recommended by Associate Editor Jipeng Li.The authors are with the Dipartimento di Ingegneria Elettrica Elettronica e

Informatica, Facoltà di Ingegneria, Università degli Studi di Catania, Catania,Italy.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2012.2185306

duce the LDO overshoots during transient load or supply vari-ations. However, the compensation remains a delicate task be-cause of the large gate capacitance of power transistor which,setting an internal low-frequency second pole, degrades boththe loop-gain bandwidth and the slew rate performance of thecircuit. It is general practice to make use of the output capac-itor equivalent series resistance (ESR) to compensate the secondpole but the approach has several drawbacks (i.e., the ESR of acapacitor is not properly specified in many cases and varies withtemperature; the use of area-efficient ceramic capacitors withvery low ESR is not allowed and large ESR can significantlyincrease transient voltage spikes) [10], [13]. Hence, alternativecompensation techniques with low or zero ESR are advisable.The LL class includes those LDOs designed to provide cur-

rent to internal (on-chip) circuitry [9], [14]–[19]. These LDOshave a relatively small output capacitive load (in the range ofhundreds pico-farad up to few nano-farad) and compensation isdemanded to Miller-based compensation approaches. However,such approaches present the drawback of requiring very largeon-chip capacitors which may lead to a prohibitive area occu-pation and degrade the slew-rate performance of the circuit.Recently, the scientific community has been interested in

Miller-based compensation techniques which exploit capacitivemultiplication through current amplifiers (CAs). The approachseems to be promising in both the two LDO classes. In theLL class, the capacitive multiplication allows to integrate thesame equivalent capacitor reducing the area occupation. Inthe HL class, the approach improves the transient responsesince the miller effect allows to boost up the second-pole and,consequently, to increase the open-loop unity-gain frequency.However, despite its advantages, Miller compensation throughcurrent amplifiers gives rise to complex-conjugate poles in theopen-loop transfer function which may cause instability, as inthe simpler case of a two-stage amplifier [20]–[23]. Hence,compensation must be accomplished prudently.Some recent works have reported low drop-out voltage

regulators compensated with current amplifiers (CA-LDOs)which are very different from each other in terms of topologyand applications [24]–[31]. Despite their dissimilarities, theseCA-LDOs can be classified in terms of HL and LL circuits.Besides, a second useful classification can be made dependingon the presence or the absence of a voltage buffer betweenthe error amplifier and the power transistor.1 This classifica-tion differentiates between voltage-buffered LDOs (VB) and

1The role of the voltage buffer is to decouple the high capacitive node atthe power transistor gate from the high impedance node at the output of theerror amplifier. This increases speed (in terms of slew-rate and bandwidth) andhelps stability. However, this solution has the drawback of decreasing the powertransistor overdrive.

1549-8328/$31.00 © 2012 IEEE

GIUSTOLISI et al.: ROBUST MILLER COMPENSATION WITH CURRENT AMPLIFIERS APPLIED TO LDO VOLTAGE REGULATORS 1881

TABLE ICA-LDO CLASSIFICATION

Fig. 1. LDO basic structure. The compensation is achieved by amplifyingwith the Current Amplifier (CA). A standard Miller capacitor, , may be re-quired to properly compensate the circuit. (a) LDO basic structure; (b) compen-sation network.

no-buffered LDOs (NB). Therefore, as reported in Table I, wemay distinguish four types of CA-LDOs which, as we shalldiscuss in Section II, have different small-signal equivalentmodel and, hence, require different compensation procedure.In this paper we develop a general and systematic model of

the frequency response of CA-LDOs which takes into accountthe changes in the transfer function due to load current varia-tions. Then, applying this general model to all the cases sum-marized in Table I, we carry out the necessary conditions forguaranteeing a minimum acceptable degree of stability overthe whole load current range. Finally, we propose three LDOvoltage regulator topologies and, unless for the LLVB case, pro-vide a robust compensation strategy and design criteria whichdemonstrate the advantage of the proposed approach in LDOdesign for the three analyzed cases (HLVB, HLNB and LLNB).In Section II, we introduce the general model of a CA-LDO

and conduct the theoretical stability analysis. Sections III, IV,V and VI investigate in detail the four different cases pro-viding transistor level implementations and simulation results.A design example with measurement results is reported inSection VII. Finally, conclusions are given in Section VIII.

II. CA-LDO MODELING

The schematic of a generic CA-LDO is shown in Fig. 1. Apartition of the output voltage, , is fed back throughand to the non-inverting input of the error amplifier (EA) andcompared to the reference voltage, . The current generator,, represents the load whose current is supplied by the power

transistor, .Quite often a voltage buffer, VB, is inserted before the power

transistor to decouple the high capacitive load seen at the gate of[1], [2], [24], [26]. The VB (whose gain is ) allows to

Fig. 2. CA-LDO small-signal schematic.

relax the EA specifications and facilitates the compensation. Onthe contrary, the VB limits the overdrive voltage of the powerdevice which requires more silicon area to provide the same loadcurrent. Hence, especially in low-voltage design, the VB is notused and the compensation is more complicated.The load capacitance, , may model either an external ca-

pacitor or the load offered by the interconnectionlines in SoC applications ( 0.1–1 nF).Finally, in our modeling, the compensation network is shown

in Fig. 1(b), and is made up of a compensation capacitor, ,amplified by through the current amplifier, CA [23]–[26].Moreover, in some configurations, a standard Miller capacitor,

, may be required to obtain proper compensation.

A. Open-Loop Gain Modeling

The generic regulator of Fig. 1 has two loops. The externalloop is due to the feedback of the output voltage throughand . The internal loop is due to the compensation network.The worst-case for stability occurs when the regulator is used inunity-gain configuration, that is with and . Inthis case, the open-loop small-signal circuit for evaluating theloop-gain is shown in Fig. 2.In the same figure, elements , , and model

the error amplifier and its equivalent output load. Elements, and model the second stage (i.e., the power stage

and the possible voltage buffer) and the overall output load.The current amplifier is represented by its input resistance

and the current-controlled current source .Finally, models the overall capacitor connected betweenthe output node of the EA and the drain of the power device.It is worth noting that the value assumed by some model pa-

rameters depends on the presence or the absence of the voltagebuffer. Specifically, in the case we use a VB to decouple the EAfrom the power device, the power MOS parasitic capacitances(i.e., , and ) may be neglected2 and models thesmall VB input capacitance. In addition, models only thepossible standard Miller compensation capacitor (i.e.,

) and comprises both the VB gain and the power de-vice transconductance (i.e., ).In the case we do not use a VB and the error amplifier is di-

rectly connected to the power device, is mainly due to thegate-source and the gate-bulk capacitances of the power MOS(i.e., ) while comprises the power MOS

2We assume that the resistance offered by the VB output node is sufficientlysmall to nullify the frequency contribution of the power MOS parasitic capaci-tances. If this is not the case, their contribution must be included.


gate-drain capacitance and the possible standard Miller com-pensation capacitor (i.e., ).As the load current, , extends over its operating range bothand change within several orders of magnitude. Some

other design parameters (i.e., the power MOS capacitances, theEA output resistance, etc.) do not change significantly (no morethan a factor of 2) and some others remain constant (i.e., ,the current mirrors’ gain, etc.).The complete open-loop transfer function of the regulator

modeled in Fig. 2, is

(1)

where

(2a)

(2b)

(2c)

(2d)

(2e)

(2f)

In order to guarantee stability, both the external and internalloops must be properly compensated. In particular, the internalloop may be responsible for two complex-conjugate poles [21],[23]. Assuming with a dominant pole, after few manipu-lation, we can approximate (1) as [21]

(3)

where

(4a)

(4b)

(4c)

B. Stability Analysis

The stability of systems that include more than one feedbackloop, can be ensured by properly checking the stability of eachsingle loop [23], [32]. This principle is very often applied in thedesign of multistage feedback amplifiers because it is simplefrom an engineering viewpoint and leads to robust implementa-tions [21], [23]. Following these considerations, the approachwe adopt requires first ensuring the adequate stability of theinner loop so that we can proceed to the external one [21]. More-over, as shown in the Appendix A, we can neglect the two zeros.The second-order polynomial in the denominator of (3) rep-

resents the closed-loop transfer function of the internal loopwhose open-loop transfer function, evaluated in terms of returnratio [23], [33], takes the form

(5)

being the dc gain, the dominant pole of the internalloop and the second pole of the internal loop. These latterquantities are related to and through

(6a)

(6b)

It is worth noting that the details of and are notnecessary as we are interested in their product, , whichrepresents the gain-bandwidth product of the internal loop. Asfar as is concerned, it is defined as the ratio between thesecond pole and the gain-bandwidth product and is related tothe stability of the internal loop [21], [23]. Specifically, underthe assumption that the internal loop has an acceptable degreeof stability with small factor, the gain-bandwidth product,

, approximates the transition frequency of the internalloop and therefore

(7)

being the phase-margin of the internal loop.3

If , the internal loop is sufficiently stable and exhibitsa phase margin with a small peak in the frequencydomain (i.e., small factor). If the phase margin is

and the frequency response is maximally flat. Fi-nally, for the poles of the closed-loop transfer functionrelated to the internal loop are real [21].Once the stability of the internal loop is guaranteed (i.e., set-

ting ), the overall stability depends on the external loopand, specifically, on the ratio between the equivalent secondpole of the external loop, , and the overall gain-bandwidthproduct, . If , the equivalent secondpole depends on the closed loop transfer function of the internalloop and is approximately equal to . Consequently, wemay define

(8)

which has a meaning similar to but refers to the external (oroverall) loop. In particular, as for (7), the overall phase margin,

is approximately given by

(9)

The stability of the overall amplifier is certainly guaranteedif and .In three-stage amplifiers a convenient choice is setting

which guarantees a maximally flat response inthe closed-loop gain of the internal loop and an overall phasemargin of about 65 [21], [23], [35], [36]. The compensation ofvoltage regulators is more complex than three-stage amplifierssince we must take into account the large variation of the loadcurrent which may span within several orders of magnitude(e.g., from to ). This large variation causes also

3A more accurate expression that bounds and together may be foundin [34] where, for a pure two-pole system, we have


to change severely and so do both and thus making thecompensation a delicate task.Note that also changes with the load current by several

orders of magnitude. However, observing that and coeffi-cients in (2) are proportional to , it is easy to demonstratethat the output resistance of the power stage does not affect thestability since and are independent of .Of course, keeping both and higher than minimum

targets, and , we can ensure the stability in the wholeoutput current range or in the desired range of interest. Hence,the behavior of both and with has to be analyzed.In general, voltage regulators are designed to work in oper-

ating mode and in stand-by mode. In the first region the load cur-rent lies in the operating range while in the secondregion a very small stand-by current, , is forced through thepower device. The stand-by current can be equal or even muchlower than the minimum load current, that is . If

the two regions are well separated, otherwise, ifthe operating region includes also the stand-by re-

gion.Obviously, a high stability degree would be desirable in the

whole interval ; however, if , it maybe sufficient to guarantee stability just in the operating range

and in stand-by mode where .Let us study as a function of . Substituting (2) into

(8) and equating we find that presents aminimum

(10)for

(11)Substituting (2) into (4c), and solving we

find the minimum of

(12)at the corresponding value of

(13)

Fig. 3 shows the trend of and as a function of fora generic CA-LDO that can be modeled as in Fig. 2. reachesits minimum at low load currents (low ) and remains con-stant at high load currents (high ). On the contrary, isconstant for low load currents and reaches its minimum at highload currents.4

It is worth noting that and are both linearly re-lated to the load capacitance , that is, the curves in Fig. 3 are

4The plot of in Fig. 3 is not valid for . In this case, (12) and(13) reveal that for , that is, the minimum is reachedat infinite load current.

Fig. 3. Stability parameters, and , versus transconductance .

shifted to the left or to the right depending on the value of theload capacitor.Note also that if the minimum of a generic parameter oc-

curs below (above) the operating range of , that is,, then the minimum of can be assumed

at the edge of the operating range, that is,.

Stability of internal and external loops will now be analyzedin the four topologies identified in Section I. For each case, weshall provide the proper compensation network capable of guar-antee and .All the implemented LDOs have been designed in a standard

0.35- CMOS technology ( , ,, ) and are capable to work

with a maximum load current of 100 mA and with a minimumdrop-out voltage of 200 mV.

III. HIGH-LOAD VOLTAGE-BUFFERED (HLVB) CA-LDO

The HLVB CA-LDO is a voltage regulator with an off-chipoutput capacitor in the micro-farad range and a decouplingvoltage buffer placed between the the error amplifier and thepower device. The big capacitive load is used for stabilityreason and for reducing the undesired transient under/over-shoots. The voltage buffer helps stability and improves speedperformance.

A. External and Internal Loop Stability

In the HLVB CA-LDO we neglect the power device parasiticcapacitors (i.e., , and ) as their contributions arestrongly reduced by the low output resistance offered by thevoltage buffer. Capacitor stands for the input impedanceof the voltage buffer and, since no standard Miller capacitor isrequired , relationships (10) and (11) turninto

(14)

(15)

The plot of versus is sketched in Fig. 4 (solid line)where a parabolic behavior is apparent in the range of interest.Hence, setting makes the external loop stable forevery value of or, which is the same, for every value of theload current, [26]. Therefore, solving (14) for yields

(16)

where the approximation holds for high .


Fig. 4. Position of (solid line) and (dotted line) curves with respectto , for the HLVB CA-LDO. In the patterned region the circuit does notsatisfy the stability requirements.

As far as is concerned, evaluating (13) for leadsto . Hence, as sketched in Fig. 4 (dotted line),decreases with and its minimum value is obtained when theload current is maximum (i.e., ). Substituting(2) in (4c) yields for

(17)

Therefore, imposing , we find for the CA inputconductance

(18)

where we assumed , which is true forsatisfying (16), and , which is true forhigh .Once the circuit is compensated, the dominant pole, , and

the equivalent second pole, , may be found from(4a) and (4b), thus yielding

(19a)

(19b)

For low load currents (so that )the two poles are approximated byand while, for high load currents,they turn into and

. Hence, at low load cur-rents, we observe that the two poles are well separated and thatthe dominant pole is placed at the external node. On the otherhand, at high load currents, the dominant pole (which dependson the equivalent compensation capacitor, , amplified bythe Miller effect, ) moves to the internal node whilethe second pole experiences the pole-splitting effect.From (16) and (18) some considerations can now be drawn.

First, it is clear that the higher the current gain, , the lowerthe capacitor that has to be integrated. Second, we observethat is linearly related to and that it does not dependon the load capacitance, . Specifically, keeping low the inputimpedance of the voltage buffer helps in obtaining a reasonablevalue of . Third, substituting (16) in (18), we notice thatboth a high current gain, , or a low VB input impedance, ,strongly help to relax constraint (18). Fourth, if the regulator

Fig. 5. HLVB CA-LDO: circuit implementation.

has been designed for a given , using a lower external loadcapacitance may cause instability as (18) may no longer hold.If (16) and (18) are satisfied, stability is guaranteed in the

whole range of load currents. Hence, the stand-by region coin-cides with the lower bound of the operating region (i.e.,

) and can be set as low as possible to reduce the power con-sumption.

B. LDO Design

The proposed circuit implementation of a HLVB CA-LDO isshown in Fig. 5. The regulator has been designed to work with amaximum load current of 100 mA and with a minimum externaloutput capacitor of 1 .The EA is a single-stage class-A folded-mirror operational

transconductance amplifier (OTA) made up of transistors. Transistors with the constant current sourceconstitute the VBwith adaptive biasing so to increase speed

during fast load transients without affecting the current con-sumption at low loads.5 Obviously, the presence of the VB limitsthe power supply to no less than 2.5 V.The CA is made up of current mirrors , of gain, and , of gain . The latter is shared with the EA

and set also , being the transconductanceof the differential-pair transistors. The overall CA gain is

while its input conductance, , is given bythe transconductance of .Transistor aspect ratios are reported in Table II. The CA cur-

rent gain, , has been set to 20 ( ; ). Bias cur-rent has been set to 2 leading toand . The VB input capacitance, is approx-imatively 500 fF. Imposing , relationship (16) pro-vides for the compensation capacitance, . Imposing

, and substituting in(18), we obtain for the CA input conductance,which is satisfied setting . Observe that, if neces-sary, the bias current of the CAmay be further reduced using thestructure discussed in Section IV for the HLNB case or usingmore efficient structures, such as the one in [37], provided thatrelationship (18) is guaranteed. Finally, the minimum VB bias

5The adaptive biasing of the VB lowers its voltage gain down to athigh output currents.


TABLE IIHLVB CA-LDO TRANSISTORS ASPECT RATIOS

Fig. 6. Open-loop gain and phase of the HLVB CA-LDO for different loadcurrent, . Drop-out condition: ; ; ;

.

Fig. 7. Phase margin of the HLVB CA-LDO versus the load current. The min-imum value of 57 is achieved in correspondence with and occurs at 1.5mA of load current.

current, , has been set to 4 and the stand-by current,has been chosen equal to 10 .

C. Circuit Simulations

Simulations are performed on the circuit in Fig. 5 where thebias current sources have replaced by their transistor-level im-plementation. The loop gain of the HLVB CA-LDO is shownin Fig. 6 for different load currents, . The curves refer to thecircuit connected in unity-gain feedback while experiencing adrop-out voltage of 200 mV.The nominal phase margin versus the load current is shown

in Fig. 7. As expected, the minimum phase margin occurs atmedium load current (about 1.5 mA) and in correspondence ofthe minimum value of . In this point, Monte Carlo simula-tions show a minimum phase margin of .Fig. 8 displays the transient response of the output voltage for

load current going from 1 mA to 100 mA (at time )and back to 1 mA (at time ). The rise/fall time ofthe current step is 1 . Considering both load regulation andunder/overshoots, the maximum difference with respect to thedesired is less than 0.5%. Monte Carlo simulations report

Fig. 8. HLVB CA-LDO: transient response for going from 1 mAto 100 mA and vice versa. (a) Buffer configuration: ;

; (b) drop-out condition: ; ;.

a settling time of and for the low-to-highand the high-to-low cases, respectively.Finally. the offset of the circuit was carried out throughMonte

Carlo simulations6 and a standard deviation of 21 mV over theentire load current range is apparent.

IV. HIGH-LOAD NO-BUFFERED (HLNB) CA-LDO

The HLNB CA-LDO is a voltage regulator with an off-chipoutput capacitor in the micro-farad range and with no voltagebuffer between the error amplifier and the power transistor. Theabsence of the voltage buffer allows reducing the supply voltagebut makes the compensation more critical due to the high capac-itive value seen at the EA output node.


Referring to the small-signal model in Fig. 2, capacitorsand are due to the power MOS parasitic capacitances

( , ). Hence, considering thatis several orders of magnitude higher than the other involvedcapacitances, we may approximate (10) and (11) into

(20)

(21)

Relationship (20) shows that, setting , wouldlead to an unreasonable value of whichposes a serious drawback for the integration. Hence we shallalways be in the situation where , as sketched inFig. 9 (solid line). However, due to the parabolic behavior of, our LDO can operate correctly outside the interval where

holds, that is, for (stand-by region)and for (operating region).Substituting (2) in (8) yields for

(22)

6All Monte Carlo simulation results have been carried out using 100 runs andconsidering both inter-die and intra-die variations.


Fig. 9. Position of (solid line) and (dotted line) curves with respectto , for the HLNB CA-LDO. In the patterned region the circuit does notsatisfy the stability requirements.

where the approximation holds for .Therefore, imposing we get for

(23)which represents the constraint for the compensation capacitor.From (23), it is clear that a high current gain is essential toreduce the required .With reference to the stand-by current, , from Fig. 9 we

observe that it should be set as low as possible so to assure thatthe corresponding lies in the stand-by region defined by

.As far as is concerned, (13) reduces to

(24)

which, due to the large value of , set well above anyreasonable value of , as shown in Fig. 9 (dotted line).Substituting (2) in (4c) yields for

(25)

Therefore, imposing , we guarantee the internalloop stability and find for the CA input conductance

(26)

where we assumed , which istrue for high load currents, and used the approximation

.Once the circuit is compensated, the dominant pole, , and

the equivalent second pole, , are given by (19) where the in-ternal capacitor is . At low or high loadcurrents the two poles approximate as in the HLVB case, hence,they behave in a similar fashion.Relationship (23) and (26) shall be used for designing the

compensation network. However, further simplifying them into

(27)

(28)

allows us to draw some considerations. First, from (27), (28), itis apparent that a high current gain, , helps in reducing boththe the compensation capacitor, , and the input conductanceof the current amplifier, (that is, area and power consump-tion). Second, in this CA-LDO, the compensation capacitor isrelated to the square root of and using a higher externalload capacitance may cause instability as (27) may no longerhold. Third, the operating region (bounded by and )cannot be set too wide as the ratio would lead toan unreasonable value of . If (23) and (26) are satisfied,stability is guaranteed in the operating region range of load cur-rents.As far as the stand-by region is concerned, it may be found in

terms of . Specifically, substituting (22) into

(29)

and solving for yields

(30)

which enables to choose the proper stand-by current of thepower transistor.

B. LDO Design

The proposed circuit implementation of a HLNB CA-LDO isshown in Fig. 10 where elements inside the dotted boxes are in-cluded and the standard Miller capacitor (drawn in dashedline) is not present. The regulator has been designed to workwith an operating load current ranging from to

. The load capacitor has been set to 1 . Wehave assumed a regulated output voltage equal to the referencevoltage of 1 V. The minimum power supply is 1.2 V.Due to the large capacitive load seen at the power MOS gate,

using the same class-A OTA of Fig. 5 would pose serious speedlimitations in terms of slew-rate. Hence, to allow the OTA tooperate in class-AB and overcome its inherent slew-rate limita-tions, we used the adaptive bias stage reported in [38], [39]. Re-ferring to Fig. 10, transistors constitute the same OTAcore of Fig. 5 while transistors perform the adaptivebias stage for class-AB operation. Moreover, current mirrors

and make use of transistors and ,respectively, to permit low-voltage operation .The CA is made up of current mirrors , of gain, and , of gain . The latter is shared with the EA

and set also , being the transconductanceof the differential-pair transistors. Transistorstogether with the bias current are used to set properly therequired input CA admittance, .Transistor aspect ratios are reported in Table III. In order to

make an effective comparison, we set the same CA gain of theHLVB CA-LDO, that is and thus causing anoverall current gain . Bias currents and havebeen set to 1 leading to and

. The corresponding transconductance atresults while at it increasesup to . The power MOS parasitic capaci-tances are and .


Fig. 10. Circuit implementation of HLNB and LLNB CA-LDOs. In the HLNB CA-LDO elements inside the dotted boxes are present while capacitor isremoved. In the LLNB CA-LDO elements inside the dotted boxes are removed and capacitor is present.

TABLE IIIHLNB CA-LDO TRANSISTORS ASPECT RATIOS

Setting and using (23), we got . Set-ting in (26), we obtained to whichwas implemented using the common gate stage with theextra current . Finally, from (30), the stand-by cur-rent, , has been chosen equal to 10 .


Simulations are performed on the circuit in Fig. 10 wherethe bias current sources have replaced by their transistor-levelimplementation. The loop gain of the HLNB CA-LDO is shownin Fig. 11 for different load currents, . The curves refer to thecircuit connected in unity-gain feedback while experiencing adrop-out voltage of 200 mV.The nominal phase margin versus the load current is shown

in Fig. 12. As designed, at the minimum operating load current,, the average phase margin is about 65 with a

standard deviation of 11 . As expected, the minimum value forthe phase margin occurs in the forbidden range (i.e.

), where it drops down to at .Fig. 13 displays the transient response of the output voltage

for load current going from 1 mA to 100 mA (at time )and back to 1 mA (at time ) at (drop-outcondition) and (power MOS in saturation region).The rise/fall time of the current step is 1 . The undershootsand overshoots are less than 2.5% and 3%, respectively. Monte

Fig. 11. Open-loop gain and phase of the HLNB CA-LDO in buffer configura-tion for different load current, . Drop-out condition: ;

.

Fig. 12. Phase margin of the HLNB CA-LDO versus the load current. Theminimum value is 33 and occurs at 100 of load current. Above 500the phase margin is greater than 45 , thus guaranteeing an acceptable degree ofstability.

Carlo simulations report a settling time of andfor the low-to-high and the high-to-low cases, respectively.

Because of inter/intra-die variations, Monte Carlo simula-tions report a standard deviation dc offset of 60 mV over theentire load current range. This large value is mainly due to the


Fig. 13. HLNB CA-LDO: transient response for going from 1 mAto 100 mA and vice versa. Buffer configuration: .

Fig. 14. Position of (solid line) and (dotted line) curves with respectto , for the LLNB CA-LDO. In the patterned regions the circuit does notsatisfy the stability requirements.

different statistical behavior of the NMOS and the PMOS tran-sistors which realize the two current sources. Fig. 10.

V. LOW-LOAD NO-BUFFERED (LLNB) CA-LDO

The LLNB CA-LDO is a voltage regulator with a low ca-pacitive load in the order of thousands of picofarad and withno voltage buffer between the error amplifier and the powertransistor. The low capacitive load models the interconnectionpower supply lines that extend over the chip or a part of it.The absence of the voltage buffer allows reducing the supplyvoltage but makes the compensation critical due to the high ca-pacitive value seen at the EA output node. This voltage regu-lator is functional for powering low-voltage on-chip circuitry inmixed signal applications or in SoC environments.


Referring to the small-signal model in Fig. 2, capacitoraccounts for the gate-to-ground power MOS parasitic capaci-tances (i.e., ) while capacitor representsthe overall gate-to-drain capacitive contribution, (i.e.,

). Consequently, under the reasonable assumptionthat , (12) and (13) reduce to

(31)

(32)

Examining (31), we find that typically locates at mediumload currents, as sketched in Fig. 14 (dotted line). Hence, theinternal loop is compensated by setting in (32).This leads to a precise relationship between capacitors and

, that is

(33)

More specifically, (33) obliges adding a standard Miller capac-itor to properly compensate the internal loop as on its ownis barely sufficient.As far as is concerned, its minimum point is given by

(11), which simplifies into

(34)

It is apparent that, due to the small value of (on-chip load),the minimum point, , is even smaller than any minimumvalue of , as shown in Fig. 14 (solid line). Hence, the min-imum value of occurs for .Substituting (2) in (8) yields for

(35)

where we assumed . Therefore, to obtainproper compensation in terms of , it is sufficient to set

. Following the details in Appendix B, weobtain the design equations

(36)

(37)

(38)

being a scaling factor satisfying

(39)

Once the circuit is compensated, the dominant pole and theequivalent second pole result

(40a)

(40b)

where and . In the LLNBCA-LDO, the dominant pole is always placed at the internalnode of the circuit while the second pole experiences the pole-splitting effect. For low load currents the two poles simplifiesinto

(41a)

(41b)

For high load currents the dominant pole remains unchangedwhile the second pole turns into

(42)


From (36)–(39) some considerations can be drawn. First, asfor the other CA-LDOs, also in this case, a high current gainhelps in reducing the required . Second, a high scaling

factor is advisable as it plays a significant role in reducing boththe compensation capacitors and . However, since itmay also take the input conductance to infinity, it mustbe chosen judiciously and a trade-off between area (in termsof compensation capacitors) and power dissipation (in termsof current required for generating ) is apparent. Third, thescaling factor may be increased by increasing the right-handside of (39). However, this would mean either increasingor decreasing and once again a new trade-off betweenarea (in terms of compensation capacitors), power dissipation(in terms of the stand-by current required for generating )and speed (in terms of ) is apparent. Fourth, if the regulatorhas been designed for a given , a higher capacitive load maycause instability.

B. LDO Design

The proposed circuit implementation of a LLNB CA-LDOis shown in Fig. 10 where elements inside the dotted boxes areto be removed and the standard Miller capacitor (drawnin dashed line) is present. The regulator has been designed toprovide a maximum load current of 100 mA with an equivalentcapacitive load of 100 pF. We have assumed a regulated outputvoltage equal to the reference voltage of 1 V. The minimumpower supply is 1.2 V.Also in this case, the EA makes use of the adaptive bias stage

reported in [38], [39] to drive the power MOS gate properly.The CA is made up of current mirrors , of gain, and , shared with the EA, of gain . The input

CA admittance, is set by the transconductance of , that is.

Transistors and the power transistor, , have thesame aspect ratios of the corresponding transistors in the HLNBvoltage regulator and are reported in Table III. Aspect ratios of

and are 6/1 and 24/1, respectively.In order to make an effective comparison, we set the same CA

gain of the other CA-LDOs, that is and thuscausing an overall current gain . Bias currents and

have been set to 1 and 10 , respectively, leading toand . The power

MOS parasitic capacitances areand .Setting and , from (39), we find that

hence we choose . Applying (36)–(38) we get, and .


Simulations are performed on the circuit in Fig. 10 wherethe bias current sources have replaced by their transistor-levelimplementation. The loop gain of the LLNB CA-LDO is shownin Fig. 15 for different load currents, . The curves refer to thecircuit connected in unity-gain feedback while experiencing adrop-out voltage of 200 mV.The nominal phase margin versus the load current is shown in

Fig. 16(a). As expected, from the analysis of , the minimum

Fig. 15. Open-loop gain and phase of the LLNB CA-LDO in buffer configura-tion ( , ) for different load current, .

Fig. 16. Phase and Gain margin of the LLNB CA-LDO versus the load current.(a) The minimum phase margin occurs at minimum load current. The phasemargin has no direct relation with ; (b) The maximum Gain margin occursat medium load current, that is, when is at its minimum value.

phasemargin occurs at theminimum load current, .The average phase margin is about 90 with a standard deviationof 6.6 . Note that the minimum phase margin is higher than thatforecasted by the theory because of the LHP zero in (2c), whichwas not considered in our analysis. Fig. 16(b) shows the nominalgain margin of the voltage regulator just to show that the max-imum value occurs at medium load current , thatis, when is at its minimum value. In this point, Monte Carlosimulations reveal a gain margin of 27 4.5 dB. These simu-lated values of phase and gain margin reveal that the circuit hasa high degree of stability and that our equations overestimatethe necessary compensation capacitors. Hence, if required, fineadjustment can be accomplished by trial-and-error in order tofurther reduce the compensation capacitors and the area occu-pation.Fig. 17 displays the transient response of the output voltage

for load current going from 1 mA to 100 mA (at time )and back to 1 mA (at time ) at (drop-outcondition) and (power MOS in saturation region).The rise/fall time of the current step is 1 . The circuit is stableand fast but, due to the low capacitive load, the undershoots andovershoots are about 12% and 16%, respectively. These values


Fig. 17. LLNB CA-LDO: transient response for going from 1 mAto 100 mA and vice versa. Buffer configuration: .

are in line with similar works [15], [28] and can be further re-duced by adopting one of the techniques proposed in [16], [18].Monte Carlo simulations report a settling time ofand for the low-to-high and the high-to-low cases,respectively.Finally, because of inter/intra-die variations, Monte Carlo

simulations report a standard deviation dc offset of 11 mV overthe entire load current range.

VI. LOW-LOAD VOLTAGE-BUFFERED (LLVB) CA-LDO

The LLVB CA-LDO is a voltage regulator with a low capaci-tive load in the order of thousands of picofarad which makes useof a voltage buffer between the error amplifier and the powerdevice, provided that there are no requirements for low voltagepower supply.


In this case, the small signal model in Fig. 2 is inaccurate todescribe the circuit behavior andmust be completed consideringthe pole associated to the output resistance of the voltage buffer,

. Including the above-mentioned term, we findthat the minimum of results

(43)

where we introduced

(44)

and where accounts for the gate-to-ground powerMOS par-asitic capacitances, (i.e., ).From (43), equating we obtain the value of the

required standard Miller capacitor

(45)

Relationship (45) poses a serious limitation to the LLVBtopology. In fact, for a given value of (set by the con-straint , not shown in this discussion), makingsmall through a high value of , leads to a small(approximatively ) which, in turn,leads to a prohibitive value of . In few words, (45) revealsthat the benefit of reducing through a high current gainis completely lost by a severe augment in .

Fig. 18. Chip photo of the LLNB CA-LDO voltage regulator.

As an example, assuming a capacitive load of 100 pF andthe reasonable value of 20 pF for , we obtain the valueof 45 pF for which nullifies the potential benefits of thecurrent-amplifier approach.7

As a consequence, in the LLVB CA-LDO, the advantage ofthe current amplification is absent and the circuit is better stabi-lized with a standard Miller compensation only. From anotherpoint of view, in case of low capacitive load, a voltage buffer isnot recommended.

VII. CASE STUDY

As a further validation of the proposed methodology, we in-tegrated the LLNB CA-LDO in Fig. 10 following the designcriteria in Section V and using the standard 0.35- CMOStechnology used for simulations. The circuit is suitable for SoCoperation and has been designed to provide up to 50 mA of loadcurrent with a supply voltage of 1.2 V and a drop-out of200 mV. The maximum expected on-chip load capacitor is 1 nF[31].The power MOS transistor has been designed with an aspect

ratio of 50000/0.6. Bias currents and have been set to1.5 , while the stand-by current, , has been setto 15 . The stability has been imposed setting and

. The overall current gain has been set towith and . Compensation capacitors have beenset to and . Just to have an ideaof the benefits of the capacitive multiplication through currentamplifiers, we note that a pure standard Miller compensationapproach would require more than 300 pF.The chip photo of the LLNB CA-LDO is shown in Fig. 18.

The chip area is about 0.4 . As expected, the main contri-bution to area occupation is due to the power MOS and the twocompensation capacitors.Fig. 19 shows the measured load regulation at

for three different values of power supply. Fig. 20displays the measured transient response of the output voltagefor the load current going from 1 mA to 50 mA and backagain to 1 mA with a rise/fall-time of about 1 . Positive andnegative overshoots stay below 70 mV while the settling time,, takes about 4 .

7In the example we assumed , , ,, .


Fig. 19. Load regulation of LLNB CA-LDO at different supply voltages.

Fig. 20. Measurement results of for going from 1 mA to 50 mA andback to 1 mA ( ; ).

TABLE IVPERFORMANCE COMPARISON BETWEEN RECENT WORKS ON SOC LDOS

Internal capacitive load (SoC)

Estimated load capacitor 10 pF

Table IV provides comparison between performance of theproposed LDO regulator and other published designs that aretargeted for SoC power management. The figure of merit

(46)

which is an extension of the usedin [14], [40], is adopted here to evaluate the speed in terms ofsettling time in different designs with respect to the dis-sipation efficiency , the maximum capacitive capa-bility and the area occupation in terms of compensationcapacitor . A lower implies a better slewing per-formance. From Table IV, it is apparent that the proposed LDOhas the best which is from 4 to 9 times lower than that ofother designs.

Fig. 21. Phase margin versus the load current for different ESR values. (a)HLVB; (b) HLNB.

VIII. FINAL REMARKS AND CONCLUSIONS

In this paper, we have presented a robust compensation tech-nique for LDO regulators which make use of Miller compensa-tion with current amplifiers in order to reduce the compensationcapacitor. The approach has been developed for all the possiblecases reported in Table I and, for three of them, LDO voltageregulator topologies have been proposed.In regulators with high (external) capacitive load where a

voltage buffer between the error amplifier and the power deviceis used, the compensation technique is particular advantageousover the whole load current range and does not relies on theESR to compensate the regulator (see Appendix C). Similarly, iflow-voltage operation is required and, hence, the voltage bufferremoved, the compensation benefits can be still achieved but ina restricted load current operating range.In on-chip regulators, which present a definitely lower ca-

pacitive load, internal loop stability requires a further standardMiller compensation capacitor. The advantage of current ampli-fication still holds when the power device is driven directly bythe error amplifier. On the contrary, a voltage buffer has beendemonstrated to worsen stability since it imposes the use of alarge standardMiller compensation capacitor which nullifies thepotential benefits of the current-amplifier approach.

APPENDIX AEFFECT OF THE ZEROS

In deriving our theory, we neglected the two zeros in (2b),(2c). To prove the validity of the approximation, in Table V wereported the worst placement of the two zeros with respect tothe for the three LDO VRs designed in the paper. Thelast row of the table refers to the LLNB CA-LDO discussed inSection VII. It is apparent that the RHP zero does not affectthe stability being always well beyond the of the circuit.Note however, that since the RHP zero depends on , in theLLNB CA-LDO a minimum bias current is required to flow inthe power MOS to prevent possible instability. As far as theLHP zero is concerned, it affect the phase margin in the LLNBcase only (as shown in Fig. 16 and discussed in Section V-C).However, its contribution is not critical to stability and may beneglected in the design phase.


TABLE VWORST PLACEMENT OF THE ZEROS

APPENDIX BCOMPENSATION OF THE LLNB CA-LDO

Equating in (35) and collecting the termsin we get

(47)

where

(48)

Relationship (47) is a quadratic equation whose solution is

(49)

Setting

(50)

we find for

(51)

and, considering that , we easily obtain thefirst design equation in (36).Substituting (51) in (33) and solving for we get the

second design equation in (37).Finally, substituting (48) in (50) and solving for we get

the third design equation in (38).Obviously, since must be positive, the denominator in

(38) must be positive as well, that is

(52)

which, solved for leads to the constraint in (39).APPENDIX C

EFFECT OF THE ESR ON HL VOLTAGE REGULATORS

The two HL voltage regulators have been designed withoutconsidering any LHP zero caused by the ESR of the load capac-itor. However, since the load capacitor is an external compo-nent, few words should be spent on the effect of the ESR on thestability. To this aim, for the two HL voltage references, we sim-ulated the phase margin behavior with respect to the load cur-rent for the ESR ranging from 0 to 1 and reported the resultsin Fig. 21. For the HLVB case, we observe that the presence of

the ESR increases the phase margin. On the contrary, the sameESR, does not alter the phase margin of the HLNB VR signifi-cantly. In both cases, it is apparent that the presence of the ESRis not critical to the circuit stability.

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Gianluca Giustolisi was born in Catania, Italy, in1971. He received the Laurea degree (cum laude)in electronic engineering and the Ph.D. degree inelectrical engineering from University of Catania,Catania, Italy, in 1995 and 1999, respectively.Currently, he is Associate Professor at Di-

partimento di Ingegneria Elettrica Elettronica eInformatica(DIEEI), University of Catania. Hisresearch interests include analysis, modeling anddesign of analog integrated circuits and systems withparticular emphasis on non-linear and low-voltage

applications.

Gaetano Palumbo was born in Catania, Italy, in1964. He received the Laurea degree in ElectricalEngineering in 1988 and the Ph.D. degree from theUniversity of Catania in 1993.Since 1993 he conducts courses on electronic de-

vices, electronics for digital systems and basic elec-tronics. In 1994 he joined the DEES (DipartimentoElettrico Elettronico e Sistemistico), now DIEEI (Di-partimento di Ingegneria Elettrica Elettronica e In-formatica), at University of Catania as a researcher,subsequently becoming Associate Professor in 1998.

Since 2000 he is a full Professor in the same department. His primary researchinterest has been analog circuits with particular emphasis on feedback circuits,compensation techniques, current-mode approach, low-voltage circuits. Then,his research has also embraced digital circuits with emphasis on bipolar andMOS current-mode digital circuits, adiabatic circuits, and high-performancebuilding blocks focused on achieving optimum speed within the constraint oflow power operation. In all these fields he is developing some the research ac-tivities in collaboration with STMicroelectronics of Catania.Prof. Palumbo was the co-author of three books: CMOS Current Amplifiers,

Feedback Amplifiers: Theory and Design, and Model and Design of Bipolarand MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), all byKluwer Academic Publishers, in 1999, 2001 and 2005, respectively, and a text-book on electronic device in 2005. He is the author of over 350 scientific paperson referred international journals (150) and in conferences, and is co-author ofseveral patents.From June 1999 to the end of 2001 and from 2004 to 2005 he served as an

Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PARTI for the topic Analog Circuits and Filters and Digital Circuits and Systems, re-spectively. From 2006 to 2007, he served as an Associate Editor of the IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS PART II. Since 2008 he has beenserving as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS ANDSYSTEMS PART I. In 2005 he was one of the 12 panelists in the scientific-dis-ciplinare area 09—industrial and information engineering of the CIVR (Com-mittee for Evaluation of Italian Research), which has the aim to evaluate theItalian research in the above area for the period 2001–2003. In 2003 he receivedthe Darlington Award. Since 2011 he has been a member of the Board of Gov-ernors of the IEEE CAS Society.

Ester Spitale was born in Catania, Italy, in 1980.She received the Laurea degree (cum laude) in elec-tronic engineering and the Ph.D. degree in electricalengineering from the University of Catania, Catania,Italy, in 2004 and 2009, respectively.She is currently working at STMicroelectronics as

an analog IC designer, dealing with power conver-sion devices and industrial products. The research ofher Ph.D., developed at the Dipartimento di Ingeg-neria Elettrica Elettronica e Informatica(DIEEI) ofthe University of Catania, has concerned linear regu-

lators, with particular emphasis on compensation techniques in SoC low-voltageapplications.

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Capacitorless LDO voltage regulators

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