Chapter 5: The Multi-Stage Amplifiers

Section 5.1 The DC Voltage in the Output

Let us consider a typical amplifier shown in Fig. 5.1-1(a). Its I-V curve and its load line are shown in Fig. 5.1-1(b).

Fig. 5.1-1 An amplifier with its operating point

As shown in Fig. 5.1-1, the small signal output will be on top of a DC voltage which is usually larger than . Now, consider the two-stage amplifier shown in Fig. 5.1-2. will now become the in the next stage. Since is usually high, it is not appropriate for it to act as .

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Fig. 5.1-2 A two-stage amplifier

One possible solution is to introduce a coupling capacitor between these two amplifiers. The coupling capacitor will filter out . That is, whatever is, it will not appear at the gate of the M2. But, we need an appropriate bias voltage for the second stage transistor. This is done by having a voltage divider consisting of R2 and

R3. As shown in Fig. 5.1-3, the gate bias voltage of M2 is now .

Fig. 5.1-3 A two-stage amplifier with a coupling capacitor in between

Experiment 5.1-1: A Two-stage Amplifier Coupled by a Capacitor

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In this experiment, we tested the circuit in Fig. 5.1-3. The program is in Table 5.1-1 and the results are in Fig. 5.1-4. The gain was found to be 40.

Table 5.1-1 Program for Experiment 5.1-1Ex5.1-1.protect.lib "d:\model\tsmc\MIXED035\mm0355v.l" TT.unprotect.op.options nomod post

VDD vdd! 0 3.3vR1 vdd! 1 10kR2 vdd! 3 160kR3 3 0 40kR4 vdd! 4 70k

.param W1=5uM1 1 2 0 0+nch L=0.35u W='W1' m=1+AD='0.95u*W1' PD='2*(0.95u+W1)' +AS='0.95u*W1' PS='2*(0.95u+W1)'

.param W1=5uM2 4 3 0 0+nch L=0.35u W='W1' m=1+AD='0.95u*W1' PD='2*(0.95u+W1)' +AS='0.95u*W1' PS='2*(0.95u+W1)'

C2 1 3 0.01nF

VGS1 vi+ 0 0.65vVin vi+ 2 SIN(0 0.001v 1Meg).tran 0.001us 10us.end

5-3

Fig. 5.1-4 The gain for Experiment 5.1-1

But a capacitor is by no means easy to fabricate in integrated circuits. Therefore, some other solution is needed. One possible solution is to introduce a PMOS transistor in the second stage, as shown in Fig. 5.1-5.

Fig. 5.1-5 A two-stage amplifier with a PMOS in the second stage

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vin

vout

t

t

Suppose that is high. Since , a high will mean a low which is appropriate for Q2. But, it is very hard to have an ideal case. That is, is seldom appropriate to be a proper . A further trick is to have an active load to replace RL2, as shown in Fig.. 5.1-6.

Fig. 5.1-6 A two-stage amplifier with a CMOS circuit in the second stage

Since an NMOS M3 is the load of M2, although may not be ideal for M2, we can still adjust the widths and lengths of the gates of M2 and M3 in such a way that there is an appropriate operating point for M2. This is demonstrated in the following experiment.

Experiment 5.1-2 A Two-Stage Amplifier without Capacitive Coupling

The program to find is in Table 5.1-2. As can be seen in Fig. 5.1-7, is almost 2.4V which means is around 3.3V-2.4V=0.9V. The program to show the operating point of M2 is in Table 5.1-3 and the result is shown in Fig. 5.1-8. The gain is shown in Table 5.1-4. We can see that the operating point of M2 is quite good from Fig. 5.1-8 and the gain is about 156 from Table 5.1-4.

Table 5.1-2 Program for operating points of M1070708TwoStageCMOSaa.protect.lib 'c:\mm0355v.l' TT.unprotect.op.options nomod post

5-5

VDD 11 0 3.3vR1 11 2 40kR2 11 1 0kV2 2 0 0

M1 2 5 0 0 nch L=0.35u W=5uM2 3 2 1 1 pch L=0.35u W=5uM3 3 4 0 0 nch L=0.35u W=5u

VGS3 5 6 0.65vVGS1 4 0 0.65vVin 6 0 sin(0 0.001v 500k)

.DC V2 0 3.3v 0.1v

.PROBE I(M1) I(R1)

.end

Fig. 5.1-7 The operating points of M1

VDS1

IM1

5-6

Table 5.1-3 Program for operating points of M2070708TwoStageCMOSb.protect.lib 'c:\mm0355v.l' TT.unprotect.op.options nomod post

VDD 11 0 3.3v

R1 11 2 40kR2 11 1 0kV3 3 0 0

M1 2 5 0 0 nch L=0.35u W=5uM2 3 2 1 1 pch L=0.35u W=5uM3 3 4 0 0 nch L=0.35u W=5u

VGS3 5 6 0.65vVGS1 4 0 0.65vVin 6 0 sin(0 0.001v 500k)

.DC V3 0v 3.3v 0.1v

.PROBE I(M2) I(M3) I(R2)

.end

5-7

Fig. 5.1-8 Operating points of M2

Table 5.1-4 The gain for Experiment 5.1-2**** small-signal transfer characteristics v(3)/vin = 155.8296 input resistance at vin = 1.000e+20 output resistance at v(3) = 101.1364k

Section 5.2 The DC Analysis of a Two-Stage Differential Amplifier

A two-stage differential amplifier is shown in Fig. 5.2-1. It can be seen that transistors M1 to M5 form the first stage and transistors M6 to M7 form the second stage.

V3=Vout=VDS3

IM2 I-V curve of M2(load curve of M3)

I-V curve of M3(load curve of M2)

5-8

Fig. 5.2-1 A two-stage differential amplifier

This first stage differential amplifier was analyzed rather thoroughly in Chapter 4. So far as DC analysis is concerned, if increases, the voltage at the drain of M4, namely V2 will also increase, as shown in Fig. 5.2-2.

Fig. 5.2-2 The input/out relationship of the first stage

Let us consider M6 and M7. Note that as increases, decreases. As shown in Fig. 5.2-3.

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Fig. 5.2-3 The I-V curves of M6 and its load curve

From Fig. 5.2-3, we can see that the increasing of will induce an increasing of as shown in Fig. 5.2-4.

Fig. 5.2-4 vs

But . Thus we have the relationship between and as shown in Fig. 5.2-5.

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Fig. 5.2-5 vs

Finally, we have the versus as shown in Fig. 5.2-6.

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Fig. 5.2-6 vs

It should be noted that the gate of M1 was labeled as positive in Chapter 4. Why is it labeled as negative in this two-stage circuit? It is labeled as negative because as shown in Fig. 5.2-6, if increases, decreases. For the same reason, the gate of M2 must be labeled as positive now.

Section 5.3 Experiments

Experiment 5.3-1 The Gain

The circuit we used is that shown in Fig. 5.2-6. The program is in Table 5.3-1 and the result is shown in Fig. 5.3-1. As can be seen, the gain is 1202.

Table 5.3-1 Program for Experiment 5.3-10423

.PROTECT

.OPTION POST

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.LIB 'c:\mm0355v.l' TT

.UNPROTECT

VDD VDD! 0 1.5V

VSS VSS! 0 -1.5V

M3 1 1 VDD!VDD! PCHW=7U L=2U

M4 2 1 VDD!VDD! PCHW=7U L=2U

M1 1 V- 3 VSS! NCH W=10U L=2U

M2 2 V+ 3 VSS! NCH W=10U L=2U

M5 3 VB VSS! VSS! NCH W=100U L=2U

M6 VO 2 VDD! VDD! PCHW=4U L=3U

M7 VO VB VSS! VSS! NCH W=14U L=2U

VBIAS VB 0 -0.95v

.OP

VIN+V+ 0 SIN(0V 0.000001V 10K)

VIN- V- 0 DC 0

.TF V(VO) VIN+

.TRAN 1U 1M

.END

5-13

Fig. 5.3-1 The gain for the two-stage amplifier in Fig. 5.2-6

**** small-signal transfer characteristics v(vo)/vin+ = 1.2028k input resistance at vin+ = 1.000e+20 output resistance at v(vo) = 452.7281k

Experiment 5.3-2 The Relationship between Vi- and Vo

We set to be 0 and changed from -1V to 1V. The program is shown in Table 5.3-2 and the result is in Fig. 5.3-2. It can be seen that drops quite sharply which indicates a high gain.

Table 5.3-2 Program for Experiment 5.3-20423

.PROTECT

.OPTION POST

.LIB 'c:\mm0355v.l' TT

5-14

vo

vin

.UNPROTECT

VDD VDD! 0 1.5V

VSS VSS! 0 -1.5V

M3 1 1 VDD!VDD! PCHW=7U L=2U

M4 2 1 VDD!VDD! PCHW=7U L=2U

M1 1 V- 3 VSS! NCH W=10U L=2U

M2 2 V+ 3 VSS! NCH W=10U L=2U

M5 3 VB VSS! VSS! NCH W=100U L=2U

M6 VO 2 VDD! VDD! PCHW=4U L=3U

M7 VO VB VSS! VSS! NCH W=14U L=2U

VBIAS VB 0 -0.95v

.OP

*** Transient Simulation ***

VIN+V+ 0 0

Vin- V- 0 0

.DC Vin- -1 1v 0.01v

.PROBE V(2, 1)

.END

5-15

Fig. 5.3-2 and vs

Experiment 5.3-3 The Operating Point of M6

The operating point is always important. In this experiment, we tried to find the operating of M6 to see whether it can be still improved. The program is in Table 5.3-3 and the result is in Fig. 5.3-3. As can be seen, the operating point can still be improved, which will be done in the next experiment.

Table 5.3-3 Program for Experiment 5.3-30423-2

.PROTECT

.OPTION POST

.LIB 'c:\mm0355v.l' TT

.UNPROTECT

VDD VDD! 0 1.5V

VSS VSS! 0 -1.5V

M3 1 1 VDD!VDD! PCHW=7U L=2U

M4 2 1 VDD!VDD! PCHW=7U L=2U

5-16

V2

Vout

V-

M1 1 V- 3 VSS! NCH W=10U L=2U

M2 2 V+ 3 VSS! NCH W=10U L=2U

M5 3 VB VSS! VSS! NCH W=100U L=2U

M6 VO 2 6 VDD! PCHW=4U L=3U

M7 VO VB VSS! VSS! NCH W=14U L=2U

Rm6 VDD! 6 0

VSD6 VDD! VO 0V

VBIAS VB 0 -0.95v

.OP

VIN+V+ 0 SIN(0V 0.000001V 10K)

VIN- V- 0 DC 0

.DC VSD6 0 3v 0.1v

.PROBE I(Rm6) I(M7)

.END

Fig. 5.3-3 The operating point of M6 in Fig. 5.2-6

5-17

I(M6)

I(M7)

I(M6)

VSD6

Experiment 5.3-4 The Changing of Operating Point of M6

In this experiment, we increased the width of M7 to be 17u to increase the current of M7. This gives a better operating point and a gain of 13968. The program for the operating point is shown in Table 5.3-4 and the result is Fig. 5.3-4. The program for finding the gain is in Table 5.3-5 and the result is in Fig.5.3-5.

Table 5.3-4 Program for Experiment 5.3-40423-2

.PROTECT

.OPTION POST

.LIB 'c:\mm0355v.l' TT

.UNPROTECT

VDD VDD! 0 1.5V

VSS VSS! 0 -1.5V

M3 1 1 VDD!VDD! PCHW=7U L=2U

M4 2 1 VDD!VDD! PCHW=7U L=2U

M1 1 V- 3 VSS! NCH W=10U L=2U

M2 2 V+ 3 VSS! NCH W=10U L=2U

M5 3 VB VSS! VSS! NCH W=100U L=2U

M6 VO 2 6 VDD! PCHW=4U L=3U

M7 VO VB VSS! VSS! NCH W=17U L=2U

Rm6 VDD! 6 0

VSD6 VDD! VO 0V

VBIAS VB 0 -0.95v

.OP

VIN+V+ 0 SIN(0V 0.000001V 10K)

VIN- V- 0 DC 0

.DC VSD6 0 3v 0.1v

.PROBE I(Rm6) I(M7)

.END

5-18

Fig. 5.3-4 A better operating for M6

Table 5.3-5 Program for finding the new gain0423-3

.PROTECT

.OPTION POST

.LIB 'c:\mm0355v.l' TT

.UNPROTECT

VDD VDD! 0 1.5V

VSS VSS! 0 -1.5V

M3 1 1 VDD!VDD! PCHW=7U L=2U

M4 2 1 VDD!VDD! PCHW=7U L=2U

M1 1 V- 3 VSS! NCH W=10U L=2U

M2 2 V+ 3 VSS! NCH W=10U L=2U

M5 3 VB VSS! VSS! NCH W=100U L=2U

M6 VO 2 VDD! VDD! PCHW=4U L=3U

M7 VO VB VSS! VSS! NCH W=17U L=2U

VBIAS VB 0 -0.95v

5-19

I(M7)

I(M6)

VSD6

.OP

VIN+V+ 0 SIN(0V 0.000001V 10K)

VIN- V- 0 DC 0

.TF V(VO) VIN+

.TRAN 1U 1M

.END

Fig. 5.3-5 The new gain

**** small-signal transfer characteristics v(vo)/vin+ = 13.9685k input resistance at vin+ = 1.000e+20 output resistance at v(vo) = 4.5357x

Experiment 5.3-5 The Input/Output Curve of the Second Stage

In Fig. 5.3-2, we can see that as increases, keeps a constant for a while and suddenly drops sharply. Thus it is worthwhile to investigate the input/output

5-20

vo

vin

relationship between the input and output of the second stage. Fig. 5.3-6 shows the second stage circuit. The program is in Table 5.3-6 and the result is in Fig. 5.3-7. As can now be seen, the input/output is indeed very sharp.

Fig. 5.3-6 The second stage circuit

Table 5.3-6 The program for Experiment 5.3-5HW4_CWLu.PROTECT.OPTION POST.LIB ‘c:\mm0355v.l’ TT.UNPROTECT.OP

VDD VDD! 0 1.5VVSS VSS! 0 -1.5VM1 2 g1 VSS! VSS! NCH W=14U L=2UM2 2 g2 VDD! VDD! PCH W=4U L=3UVG1 g1 0 -0.95VVG2 g2 0 0

.DC VG2 -1.5v 1.5v 0.1v

.END

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Fig. 5.3-7 The input/output curve of the second stage

Experiment 5.3-7 The Investigation of the Reason Behind the Behavior of the Input/Output of the Second Stage

In this experiment, we try to explain why the input/output curve of the amplifier in Fig. 5.3-6 is so sharp. We plot the I-V curve of M1 and load curves corresponding to different gate voltages of M2. The program is in Table 5.3-7 and the result is in Fig. 5.3-8. From Fig. 5.3-8, we can see that the I-V curves are very crowded when is small. Thus when is small, does not change much. We may even say that it remains a constant. But, as reaches a certain value, sharply decreases.

Table 5.3-7 The program for Experiment 5.3-7.PROTECT.OPTION POST.LIB ‘c:\mm0355v.l’ TT.UNPROTECT.OP

VDD VDD! 0 1.5VVSS VSS! 0 -1.5V

VG2

VD2

5-22

Rdm VDD! 3 0

M1 2 g1 VSS! VSS! NCH W=14U L=2UM2 2 g2 3 3 PCH W=4U L=3UVG1 g1 0 -0.95VVG2 g2 0 XVDS1 2 VSS! 0

.DC VDS1 0v 3v 0.01v SWEEP X 0 1v 0.1dv

.PROBE I(M1) I(Rdm)

.END

Fig. 5.3-8 The I-V curve of M1 and its load curves

VDS1

I(M1)

I(M2)VG2=0

VG2=0.1

VG2=0.2

VG2=0.3

VG2=0.4

VG2=0.5

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