.,.
\NABCC ~
An American-Standard Company
SERVICE MANUAL 6054
CAR SPACE MICROPROCESSOR
nay, 1980 A-80-50-2121-3
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INSTALLATION & MAII\JTENANCE
UNION SWITCH & SIGNAL DIVISION WESTINGHOUSE AIR BRAKE CON\PANY
Swissvale, PA 15218
TABLE OF CONTENTS -------...
SECTION TITLE
I CAR SPACE MICROPROCESSOR. . . . . . 1.1 PURPOSE. . . . . . . . . . . . 1.2 GENERAL DESCRIPTION. .
' 1.3 SYSTEM COMPONENTS. . . . . 1. 3.1 Central Processing Unit. . 1.3.2 Memory and I/0 Control . . 1.3.3 Data Buss/Multiplexer. . . 1.3.4 PROM Card. . . . . . . . . 1.3.5 PROM . . . . . . . 1.3.6 RAM. . . . . . . . . . . . 1.3.7 Console Card . . . . . . . 1.3.8 Priority Interrupt 1.3.9 Buss Port. . . . . . . 1.3.10 Latched Output Buffer . . 1.3.11 Device Address Decoder . 1.3.12 Device Interrupt/Control 1.3.13 Real-time Clock. . 1.3.14 Enclosure. . . . . . . . .
1. 4 CONTROLS AND INDICATORS. . . . . ,-'
II INSTALLATION. . . . . . . . . . 2.1 GENERAL. . . . . . . 2.2 PRINTED CIRCUIT BOARD PART NUMBERS
AND LOCATIONS. . . . . 2.3 INTERFACE WIRING . . . . . . .
III PRINCIPLES OF OPERATION . . . . 3.1 GENERAL. . . . . . . . . . . . . . 3.2 SYSTEM BUSS ORGANIZATION . . . . 3.3 FUNCTIONAL DESCRIPTION . . . . .
r 3.3.l Car Space and Distance Displays Operation .
3.3.2 Scan Completion. . . . . . 3.3.3 Initialization Routine . .
3.4 MICROPROCESSOR ORGANIZATION. . . . 3.5 BASIC MICROPROCESSOR SIGNALS . 3.6 CPU STATUS INFORMATION . . . . 3.7 TIMING . . . . . . . . . . . . . 3.8 MEMORY AND I/0 SYNCHRONIZATION . 3.9 AUTOMATIC POWER-UP RESTART . .
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PAGE
1-1
1-1 1-1 1-2
1-2 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-4 1-4 1-5 1-5 1-5
1-5
2-1
2-1
2-1 2-1
3-1
3-1 3-1 3-3
3-5 3-7 3-8
3-8 3-10 3-12 3-13 3-18 3-18
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SECTION
IV
v
TABLE OF CONTENTS (Cont.)
TITLE
FIELD MAINTENANCE •• . . . . . 4.1 4.2 4.3 4.4 4.5
(;E!~E!RAL • • • • • • • • • • • • TEST EQUIPMENT •••••• GENERAL FAULT ANALYSIS ••••• TROUBLESHOOTING PROCEDURES ••••• ADJUSTMENTS • • • • • • • • • • • •
4.5.1 Test Equipment •••• 4.5.2 Adjustmen~ Procedure
. . . DIAGRAMS ••
5.1 5.2
GENERAL • • • • • • • DIAGRAM LIST •••• . . .
APPENDIX A - SERVICE DATA •• . . . . . . . . .
FIGURE
1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 3-6 4-1
LIST OF ILLUSTRATIONS
TITLE
Car Space Microprocessor .•.•. Console Card and Status Indicators Card File and Processor Data ••..• System Buss Organization. . . •. Microprocess·or Organization . . . Basic CPU Machine Cycle ....••• CPU State Transition Diagram. CPU Block Diagram .•.••. Functional Description •.••.•.• Microprocessor Power Supply Adjustment
Location . . . . . . . . . . . . . .
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PAGE
4-1
4-1 4-1 4-1 4-1 4-7
4-7 4-8
5-1
5-1 5-1
A-1
PAGE
1-2 1-6 2-3/2-4 3-2 3-9 3-14 3-15 3-17 3-19/3-20
4-8
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SECTION I
CAR SPACE MICROPROCESSOR
1.1 PURPOSE
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The Car Space Microprocessor performs the housekeeping functions required to handle data between the A/D converter and either the Central processor at the yard, or the car space and distance data displays.
The Car Space Microprocessor uses an integrated circuit microprocessor as the controlling element instead of hand-wired integrated circuit logic, since the software program of the microprocessor provides more capability and flexibility with much less complexity. The flexibility of the program permits operations such as data linearization, binary-to-BCD conversion, multiplication, and division without additional hardware. The processor also provides addressed data storage and interrupt control of the program sequence.
1.2 GENERAL DESCRIPTION
The Car Space Microprocessor (Figure 1-1) comprises a solidstate processor unit and power supplies, housed in a card file designed for mounting in a standard 19 inch rack. The power switch and fuse are conveniently located on the rear panel and the unit is designed for operation from a standard 115 volt, 60 Hz power source. The unit is pre-wired for memory expansion and is designed for cable card interfacing •
. The Car Space Microprocessor can be subdivided. into four basic functional areas: 1) microprocessor including program memory and data memory, 2) input ports, 3) output ports, and 4) interrupt control circuitry.
The Microprocessor card file also contains: interfacing circuits for external equipment, including differential line drivers and receivers to interface to the main yard CPU; optical isolators and relay boards to interface the external displays and thumbwheel switches; a real time one second clock, and power supplies for the data processor.
The main circuit configuration is organized around a set of three printed circuit logic cards that form an 8-bit central processing unit with supporting control logic. These cards form the basic processor and comprise the following:
1. Central Processing Unit - CPU (Intel 8080) and Address Buss drive and control logic.
6054, p. 1-1
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Figure 1-1. Car Space Microprocessor
2. Memory and I/0 Control - Crystal-controlled system clock and logic for controlling input/output and memory synchronization.
3. Data Buss/Multiplexer - CPU input multiplexer and Data Output Buss drive logic.
1.3 SYSTEM COMPONENTS
The following is a brief description of the microprocessor system modules and peripheral devices.
1.3.1 Central Processing Unit
This module includes the CPU, a single chip LSI microprocessor (Intel 8080) fabricated using N-channel MOS technology. The CPU is an 8-bit parallel processor.with six 8-bit working registers, an 8-bit accumulator and a 16-bit stack pointer. The CPU instruction set includes 78 basic instructions.
6054, p. 1-2
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The CPU operates from a 2 MHz, two-phase, asymmetric clock. The execution of instructions is divided into a number of "time states" - each time state takes 500 nanoseconds and the number of time states required depends'upon the instruction being executed and consideration of the speeds.of_ the memories and peripheral device interfaces being used. The execution time of the "typical average" instruction is in the range of 5.5 to 7 microseconds. Refer to section III for a detailed discussion of basic processor timing.
This card also includes tri-state drivers for the A Buss and drivers for CPU status, control, and timing signals.
1.3.2 Memory and I/0 Control
Th~s module includes the 2 MHz, two~phase, asymmetric, crystal-controlled system clock. CPU status information is latched and used to control data traffic entering the CPU via the CPU Input Multiplexer and to control memory ~ead/write and input/output data transfers. It also contains logic to match CPU speed to the data transfer speed of memories and peripheral device interfaces. This logic is programmed by a jumper and indu9es WAIT states into CPU instruction execution cycles. These WAIT states (500 nanoseconds each) cause the CPU to delay, giving the memories and peripheral device interfaces enough time to perform their data transfers.
1.3.3 Data Buss/Multiplexer
This card includes the CPU Input Multiplexer, a two-port . multiplexer that gates data from the MD Buss or the DI Buss onto the bi-directional D' Buss and into the CPU. It also includes drivers for the D Buss.
1.3.4 PROM Card
Each PROM card contains sockets for two erasable/reprogrammable ROMs and logic for decoding 14-bit addresses. Memory address range selection on the module is done by user-installed jumpers. The memory capacity of the module is 512 bytes (two 256 Bit PROMS). .
1.3.5 PROM
The PROM is a 256-byte ultra-violet, erasable/reprogrammable read only memory with a 1.0 usec. maximum ac9ess time. This device is mounted in sockets on the PROM card_s. PROMs are supplied programmed according to WABCO Specifications.
6054, p. 1-3
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1.3.6 RAM
This card contains a 1024-byte random access memory {read/ write memory) with on-board logic for decoding 14-bit addresses. Memory address range selection on the module is done by jumpers. The memory has a maximum access time of 1.0 usec.
1.3.7 Console Card
This card provides operator controls for starting, stopping, and single stepping the CPU.
1.3.8 Priority Interrupt
This module provides logic for eight vectored priority interrupts. All interrupts can be enabled and disabled as a group under program control and individual interrupts can be masked under program control. Only 2 of the 8 interrupt lines are used in the Car Space Processor.
1.3.9 Buss Port
The Buss Port provides 24 bits of TTL level input interface to the microcomputer system. Logically, the card contains 24 tri-state gates with outputs organized for wiring "directly onto the DI Buss. The gates are arranged in six groups of four gates each. Three groups output to DI7-DI4 and three groups output to DI3-DI0. Groups are paired for 8-bit data transfers. Data transfers onto the DI Buss are enabled by direct select line outputs from Device Address Decoders.
1.3.10 Latched Output Buffer
The Buffer provides storage latches for 24 bits of information TTL output. Inputs to the latches are directly from the D Buss. The latches are organized in six groups of four latches each. Inputs to three groups are from D7-D4 and inputs to the remaining three groups are from D3-Do, Groups are paired for 8-bit data outputs. The latches are enabled by direct select line outputs from Device Address Decoders.
1.3.11 Device Address Decoder
The Device Address Decoder provides decoding of the address lines into one of sixteen separate active low outputs for the control of peripheral devices and external logic. The 4 bits of device select code are wired to the input of this card. The code is a 4-bit subset of the 8 device code bits generated by the processor input/output instructions. The card also includes four dual input NOR gates that are employed in decoder enable control, decoder output gating, etc.
6054, p. 1-4
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1.3.12 Device Interrupt/Control
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The Interrupt/Control circuits generate interrupt requests to the Priority Interrupt card. The interrupting device generates an interrupt request with a rising-edge clock signal.
1.3.13 Real~tlme Clock
The Clock is a programmable, crystal-controlled inter:val timer. -The clock rate can be rates of 1 Hz, 10 Hz/ 100 Hz or 1,000 Hz. Expiration of an interval is directly sensed by the processor as an interrupt. In the Car Space Processor the l Hz (1 second) time interval starts the SCAN.
1.3.14 Enclosure
The enclosure is-wired for the processor, including'the power supplies which provide +12V (@ 0.5 amps}, +5V (@ 6 amps}, -5V (@ 0.1 amps), and -9V {@ .2 amps).
1. 4 · .· CONTROLS AND. INDICATORS
Figure 1-2 illustrates the controls and indicators, mounted on the console card and the memory control card-. The control switches, pushbuttons, and indicators are described below.
1. Run Indicator - This LED _indicator is illuminated when the CPU is not in the.stopped (Halt) condition. It is turned off only by execution of an HLT instruction. When on, it indicates that the CPU is executing instructions.
2. Data Switches - Three octally coded numeric thumbwheel switches. The most significant digit is the uppermost thumbwheel. These switches are used to set up CPU instructions for various console control functions. The number set in these switches may also be read by a program as input data.
3. :Reset .Pushbutton - The Res.et pushbutton generates a logic signal that triggers the Automatic Power-up Restart logic in the Basic Processor, causing the CPU to d~sable interrupts and begin program execution at memory location· O.
4. Wait Switch -- The Wait switch causes the READY line to go false. The READY line is not switched·until machine cycle Ml, time state T2. As a result, when the switch is first turned on, the CPU pa·uses in a Tw state during Ml - at the start of. the next instruction- -fetch.
6054 I P• 1-5
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CONSOLE CARD
CONSOLE MEMORY SWITCH --P....,.-.-_..;::::_.....;... ,....,.--:;._.11 .....ii---- MEMORY CONTROL
RUN INDICATOR --.:---=~--!-i~~~
MOST SIGNIFICANT --.---+---MDIGIT
CONSOLE DATA SWITCHES
·o 0 0
LEAST SIGNIFICANT --..--"""T"---i-~ DIGIT
O STATUS INDICATORS
WAIT SWITCH --;---;,,---;,--+
-----INTA
o-'---HLTA
0-+--l -INP
0 OFF
ON_..-/
(SWITCH POSITIONS)
Figure 1-2. Console Card and Status Indicators
5. Step Pushbutton - The Step pushbutton causes the READY line to go true only long enough for the CPU to leave the current Tw state. It is used to single step the CPU through successive machine cycles. The button operates only when the CPU is in the Tw state.
6. Console Memory Switch - The Console Memory switch causes the CPU Input Multiplexer to switch to the DI Buss unconditionally and for as long as the switch is on. It also enables tri-state gates on the Console
6054, p. 1-6
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Card and places the Console Data switch data on the DI Buss.· As a result, all inputs to the CPU come from the Data switches. The switches can then be thought of as a single memory location, the·contents of which are set by the operator.
7. Status Indicators - Four Status indicators are provided on the Memory Control card.· These are LED indicators and show through the test point holes in the card handle, as listed below:
Test Point
5 6 7 8
INTA HLTA INP OUT
Status
(interrupt acknowledge) (halt condition) (input instruction) (output instruction)
6054, p. 1-7/1-8
2.1 GENERAL
SECTION II
INSTALLATION
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This section provides general information for the installation and interfacing of the Microprocessor. Included are printed circuit board part numbers and card file locations, an~ interface wiring information.
2.2 PRINTED CIRCUIT BOARD PART NUMBERS AND LOCATIONS
Table 2-1 lists the part numbers for the printed circuit boards used in the Car Space Microprocessor, a description of each board, and the card file slot where each board is located.
Additional information, and slot locations, are shown in Figure 2-1.
TABLE 2-1. PRINTED CIRCUIT BOARD LOCATIONS
CARDFILE PART NUMBER DESCRIPTION SLOT
N451493-1002 Programmable Read Only Memory (PROM) 6 N451493-1001 Programmable Read Only Memory (PROM) 7 N451493-1102 Random Access Memory (RAM) 8 J776616-192 Microprocessor 9 J776616-194 Buss Multiplexer 10 N451493-ll01 Memory Control 11 J776616-196 Console Card 12 J776616-195 Interrupt Priority Control 14 J776616-199 Address Decoder 17,18 J776616-202 Interrupt Select 19 J776616-203 Real-time Clock 20 J776616-201 Eight-Bit Buffers 21,22,23 J776616-200 Eight-Bit Buss Port 24,25 N451054-9902 Line Termination 26 N451054-0301 Cable Cards 27,28,
/ 29,30
J776616-187 Differential Line Receiver 31,32 J776616-l86 Differential Line Driver 33,34 N451054-0301 Cable Cards 35,36 N451054-1601 Optical Isolator 37 J776616-175 Relay Interface 38 N451054-0301 Cable Card 39
2.3 INTERFACE WIRING
Convenient interfacing is facilitated through the use of cable card printed circui~ boards in the card file1 refer to the WABCO system manual (SM6053) for interfacing information.
6054, p. 2-1/2-2
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SECTION III
PRINCIPLES OF OPERATION
3.1 GENERAL
This section provides a basic description of the principles of operation, the timing, and the synchronization of the Car Space Microprocessor.
3.2 SYSTEM BUSS ORGANIZATION
Five system busses for control and communication originate and terminate on the Basic Processor card set as shown in Figure 3-1.
1. Input Data Buss (DI Buss) - This 8-bit tri-state buss carries data and status information to the CPU from peripheral devices and logic.
2. Memory Data Buss (MD Buss) - This 8-bit buss carries instructions and data to the CPU from memories.
3. Data Output Buss (D Buss) - This 8-bit buss carries data and control information to memories and peripheral devices.
4. Address Buss (A Buss) - This 16-bit tri-state buss carries ·the addresses of memory locations and peripheral devices.
5. CPU Data Buss (D' Buss) - This 8-bit bi-directional tri-state buss provides communication between the CPU and the Data Buss/Multiplexer card.
The 16-bit A Buss (A15-AQ) originates on the Central Processing Unit card. Normal traffic on this buss consists of memory address (during instruction and data fetch cycles and memory write cycles) and input/output device addresses (during I/0 instruction execution). The device address appears on A7-Ao and on A15-A9 simultaneously and serves as a code for up to 256 input devices and 256 output devices. Ao is the least significant bit of the A buss for memory addresses. Ao and Ag are the least significant bits for device addresses.
The D' Buss (D'7-D'o) is an 8-bit bi-directional buss between the Central Processing Unit card and the Data Buss/Multiplexer card. Normal traffic on this buss consists of all data exchanges between the CPU and the remainder of the system (memories and peripheral devices}. Processor status is also an output on this buss and is latched on the Memory and I/0 Control card. Data to the CPU from memories and peripheral
6054, p. 3-1
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BUSS PORTS
PRIORITY INTERRUPT CONTROL
MEMORY DATA
I BUSS I L:or~~..J
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I INPUT DATA BUSS I L 017, 010 TR I-ST A TE _J ---r----
I fA•~~--c LATCHED OUTPUTS
A I \
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BUSS MUX
I I
I
I DATA OUTPUT BUSS I 07-00 j
·L--,------
' ' rC;U ;ATA BUSS
If' ~ .~ -f 0'7·0'0, TRI-STATE
] - - - - - I BIDIRECTIONAL
--- L---........
CPU
MEMORY CONTROL
MEMORIES
I I
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r-
I
DEVICE ADDRESS
DECODERS
~ ADDRESS BUSS ~....... L~AO, TRI-STATE
Figure 3-1. System Buss Organization
6054, p. 3-2
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logic is gated onto the D1 Buss by the CPU Input Multiplexer. Output data from the CPU on the D' Buss is gated onto the Output Data Buss (D Buss) by buss drive logic. D'o is the least significant of the D' Buss.
Both the A Buss and the D' Buss are tri-state busses. A single control line is provided for commanding these busses to be switched to the high impedance state so that Direct Memory Access (OMA) devices can control them for writing to and reading from memory. An acknowledge line is provided that indicates when the A and D' Busses are in the high impedance state.
The D Buss (D7-Do) is an 8-bit buss originating on the Data Buss/Multiplexer card. Do is the least significant bit of the D Buss. This buss carries CPU status data to the Status Latch and carries all other CPU output data to the system memories and peripheral devices.· Memories and peripheral devices must recognize when they are being addressed and must take data from the D Buss.
The MD Buss (MD7-MD0) is an 8-bit buss terminating on the Data Buss/Multiplexer card. MDo is the least significant bit of the MD Buss. This buss carries instructions and data from the memories to the CPU (via the CPU Input Multiplexer). Data outputs from the MOS memories are OR-tied onto this buss. Decoding logic on each memory card recognizes that the card is being addressed by the contents of the A Buss. Logic then enables the selected memory elements and switches their outputs onto the MD Buss. Switching of the MD Buss onto the D' Buss is via the CPU Input Multiplexer.
The DI Buss (DI7-DI0) is an 8-bit buss terminating on the Data Buss/Multiplexer card. Dio is the least significant bit of the DI Buss. Input from any peripheral device to the CPU is carried on this buss. Any device providing data to the DI Buss must do.so through tri-state gates. Input peripheral devices must recognize when they are being addressed and use this recognition to enable the data transfer onto the DI Buss. Device address decoding services for input devices are also provided.
3.3 FUNCTIONAL DESCRIPTION (Refer to Figure 3-6)
The clock board (location 20) generates a logic interrupt request (IRl) to the interrupt priority register (location 14). This interrupt request is generated once every second and initiates a microprocessor program which scans the yard to determine the available car space in each track.
When the microprocessor acknowledges the clock interrupt, an interrupt acknowledge pulse is generated and routed to the interrupt priority control card which, in turn, clears the requested interrupt with the acknowledge signal (ACKl). At
6054, p. 3-3
WABCC ~
this time, the microprocessor begins running the program stored in the PROM cards (locations 6 and 7) and sends an indication to the main yard computer that it is busy doing a yard scan. An 8-bit word is sen~ to output buffer no. 3 (location 21) over the data buss. This 8-bit word has all bits at a logic 0. This scan complete bit (bit 3 of output port 3) is, therefore, reset. This signal is sent over a differential line to the computer. The logic O state of the scan complete signal also prevents the computer from interrupting the scan until it is completed.
The yard scan now begins with the microprocessor sending the first multiplexer address associated with the first track in the yard to the A/D subsystem via output port 4. The A/D subsystem is configured to check nine groups of eight tracks each. The 8-bit address word has the track address 0-7 as the four least significant bits and the group address 0-8 as the four most significant bits. Twenty microseconds after the address is sent to the A/D converter through output port 4 {location 21), a logic O convert command is sent to the A/D converter through bit O of output port 5 (location 23).
Upon reception of the logic O convert command, the A/D converter performs an analog-to-digital conversion on the analog signal from the phase detectors and presents a 10-bit binary word and a logic O conversion complete signal to the microprocesso~ through input ports 4 and 5. During the conversion time,· the microprocessor is in a loop which examines the conversion complete signal (most significant bit line of input port 5) for a logic O level. As long as the conversion signal is a logic l, data is not read in as the A/D converter is still converting.
When the conversion complete line goes to logic 0, the data is accepted from input port 5 and then port 4. If the conversion complete line does not go to logic O within three passes of the loop program approximately 75 microseconds after the convert command was sent out, the microprocessor assumes an error in data from that address and goes on to check the next track.
After the two words of data are shifted into the microprocessor, the data undergoes an operation which corrects for any nonlinearity in the data. Then, the scan complete bit {logic 1) is OR'ed into bit position 3 of the most significant byte and the data ready bit in bit position 4 is set. The data is stored in the Random Access Memory (RAM) (location 8). Data is stored in the lower half of the RAM in two parts, the least significant byte in location'OCXX (hex) and the most significant byte in location ODXX {hex). The XX portion of the address is the decimal track number of the track associated with the data; e.g., data track 25 is stored in 0025 (hex) and OC25 (hex).
6054, p. 3-4
\
j
After data is stored in memory, the track and group addresses are incremented and the scan process is repeated for the second track and continues on until the processor scans all 72 tracks in the yard. If all 72 tracks are not used in a yard, data will not be sent back by the A/D for the missing tracks. The processor assumes-the track data to be in error, and instead of linearizing the data, the processor OR's a logic 1 error (fail bit) into bit 2 of the most significant word at the same time the scan complete bit is OR'ed into the data. The processor then stores the data in the associated location in the Random Access Memory.
WAEICCI ~
After all 72 channels of the phase detectors have been scanned and converted, the microprocessor goes back and checks two reference voltages (full and half scale) from each phase detector board. These reference voltages are converted by the A/D converter and the digital result is compared to stored values. If a discrepancy occurs, the data for every track associated with that phase detector is recalled from memory, and the fail bit is set in bit 2 of the most significant word of that data.
The test data is also stored in memory. Address 80 through 88 holds the full scale test data from groups 0-8 and address 90 through 98 holds the half scale data. The fail bit is set in ~he most significant word of this data before storage, to indicate non-valid track data if those addresses are inadvertently requested by the main computer.
3.3.l Car Space and Distance Displays Operation
When the scan procedure is completed, the microprocessor services the car space and the distance (feet) display.
The microprocessor inputs the yard operator's panel through is in complementary BCD form. and checked to insure that it 1 and 72.
two-digit track number from the input port 8. This track address
The input is inverted into BCD is a valid decimal number between
If the track number is valid, it is used as a memory address to retrieve the data from the Random Access Memory. The two words of data (in binary form) are multiplied by three and divided by 54 (actually just divided by 18), then converted into a two-digit decimal number by a binary to BCD conversion routine.
NOTE
In the binary data, the least significant bit represents 3 feet. Average standard car length is 54 feet per car and •••
DATA [ 3 ft J Data (Cars) 54 ft/car = 18
6054, p. 3-5
WABCCI ~
The BCD result of the conversion routine is shifted to output port 8 {location 22) as a two-digit number representing car spaces remaining at that track. The buffer is interfaced to the display through reed relays.
If the track number was not valid or if the stored data has the fail bit set to logic 1, an 8-bit word (all logic l's) is outputted to the display causing the display to be blanked.
After the car space display service routine is completed, the microprocessor updates the local distance (feet) display on the car space rack. This routine is very similar to the program for the car space display.
The microprocessor inputs the two-digit track number request from the test panel thumbwheel switch through input port 6. This track address is also in complementary BCD form. The input is inverted in the microprocessor into BCD and checked to insure that it is a valid number between 1 and 72. This address is used to retrieve the data from the memory. Then binary data is multiplied by 3 to convert it into feet and then processed into a four-digit BCD number by the binary to BCD conversion routine.
The four-digit BCD number is outputted as two separate 8-bit words. The two least significant digits are transferred to"'
'\ J
..,
output port 7 as one 8-bit word, while the two most signifi- 1
cant digits are sent to output port 8. These output ports tie 'U directly to the local distance (feet) display. In addition, the distance (feet} display and thumbwheel switches will accept address 80 through 88 and 90 through 98 as a check on the A/D subsystem. As long as the test reference voltage data is within specification, the display will indicate 5000 for a full scale reading (5 volts) and 2500 for a half scale reading (2.5 volts). Since 80 through 88 is the address that repre-sents full scale test data, dialing 81 and getting 5000 is a check that the phase detector for the second group is working. Similarly, 98 dialed into the thumbwheel switches, should in-dicate 2500 on the display insuring that the 9th group phase detector is working.
NOTE
In address format 9X or ax, Xis group number O through 8.
If the reference voltage is not within specification, or a phase detector is not used for a given series of tracks, or an invalid address or an address of an unused track is dialed on the thumbwheel switches, the display will be blanked.
6054, p. 3-6
3.3.2 Scan Completion
WABCD ~
After the distance (feet) display has been updated, the microprocessor outputs a scan complete signal to the main computer over output port 3 to indicate that the scan is finished. The microprocessor then goes into a halt state until an interrupt occurs.
Once the main yard computer receives an indication that the scan complete bit is set, it sends a two-digit BCD track address and a request data bit to the microprocessor over a differential pair set of data lines to input ports 2 and 3.
The request data signal is interpreted by the interrupt select logic (location 19) as an interrupt and the interrupt request is transferred to the interrupt priority control logic (IRO signal). The interrupt priority logic decodes the interrupt and transfers the request to the microprocessor via the data input buss. The 8-bit message instructs the processor to start another program to handle the request for data from the main computer. When the microprocessor acknowledges this request by the interrupt acknowledge signal, the interrupt request is cleared, and the microprocessor responds to the request for data.
The microprocessor inputs the BCD track address from input port 2 and, without checking address validity, transfers the 10 bits of binary data, plus the flag bits (scan complete bit, data ready bit, and fail bit) when used, to output ports 2 and 3. The 8 least significant bits of binary data are transferred from memory location CCXX to output port 2. The processor then retrieves the two most significant bits of binary data and the three flag bits from memory location ODXX, perform an exlusive OR'ing operation on the data ready bit (bit 4), and transfers the data to output port 3. The exclusive OR'ing operation causes data ready to alternate between logic 1 and logic O for each successive data request. The processor saves the state of data ready and then halts again.
The alternating of the data ready bit for each data request is an indication to the computer that the input request has been answered and the new word of data is available at output ports 2 and 3. Once the microprocessor is again in the halt mode, it can accept another interrupt from the computer or the realtime clock.
When the real-time1 clock (location 20) marks a second, another interrupt is sent to the processor to start the scan sequence again. The clock interrupt has priority over the main computer data request, so that once the scan begins the main computer cannot request data until the scan is complete.
6054, p. 3-7
WABCCI ~
3.3.3 Initialization Routine
When power is first applied to the microprocessor, a single shot on the buss multiplexer card {location 10) resets the microprocessor. An initialization routine, starting at _memory address zero, resets the scan complete bit and the convert command to the A/D multiplexer and blanks both displays, by sending an appropriate data word to the corresponding output ports. This program loads the Random ~ccess Memory location ODOl through ODFF {255 addresses) with a special word that has the data ready, scan complete, and fail bits all set to a logic 1. This is done to guarantee that any memory location not loaded with valid data by the scan program will contain an error bit to indicate either invalid data or a non-decimal address selection. The fail bit will be sent to the computer if a track other than 1 to 72 is selected. Likewise, the displays will also be blanked for non-valid addresses.
Memory locations OCOO and ODOO contain a 10 bit binary data word {all zeroes), along with the scan complete and data ready bits. The fail bit is not set.· These data words correspond to track address zero and are used to test the displays and computer communications channel.
The startup program also resets the real-time clock and starts it timing a 1 second scan time interval. After this, the microprocessor halts and waits for an interrupt from the clock. The yard computer is prevented from requesting or receiving data until the scan complete bit is set after completion of the first scan of the yard.
3.4 MICROPROCESSOR ORGANIZATION
The organization of the basic processor is illustrated in Figure 3-2. The basic processor consists of the following major components:
1. Central Processor (CPU) - the Intel 8080, an LSI Nchannel MOS microprocessor.
2. CPU Input Multiplexer - logic for multiplexing the DI Buss (Input Data Buss) and the MD Buss (Memory Data Buss) onto the D' Buss (CPU Data Buss).
3. Status Latch~ a latch for 8 bits of processor status information.
4. Memory and I/0 Synchronization Logic - logic for synchronizing the CPU to memory and peripheral device interfaces during data transfers.
5. System Clock - a crystal-controlled, 2-phase, 2 MHz clock.
6054 I P• 3-8
°' 0 U1 ,s:,. ... tO • w I
\0
./
HOLDU
HLDA ()4 •
A15-AG ( A BUSS
D7·DG ( D BUSS
..,I
I
D R I
I v E R s
STATUS I LATCH
(MEMR, llif, Ml, HLTA, STACK, WO, INTAI
INTE INT WAIT
CENTRAL PROCESSOR
D· I B u s I s
r-D
~ ~ R
I I v E R s
L
CL'.'. .. "OMHZI~ I SYSTEM G1 (2MHZl CLOCK
(i2 (2MHZl
MEMOAY&l.10 SYNCHRONIZATION
LOGIC
ioim
OUTS MW
I
I
: I I
I I
-READY
I
WA
CA
I Ill() SYNC
AUTO POWER UP RESTART
. RESET
I OBIN
( MD BUSS I MD7·MDG CPU
INPUT MPXA
K DI BUSS I D17-DIQ
I ) DMACI
I O CM
(INTERNAL CONNECTIONS NOT ALL SHOWN}
READY
Figure 3-2. Microprocessor Organization ~I
WABCCI ~
6. Address Buss Drivers - drivers for the 16-bit tri-state I'\ A Buss.
7. Data Output Buss Drivers - drivers for the 8-bit D Buss.
8. Automatic Power-up Restart - logic for automatic and manual restart of the processor.
3.5
SYNC
OBIN
READY
WAIT
HOLD
HLDA
INTE
6054, p. 3-10
BASIC MICROPROCESSOR SIGNALS ,.,
Active high output signal indicating the. ·beginning of each machine cycle~' Processor status is sent to the Status Latch at SYNC time.
Active high output signal indicating the D' Buss is in the input mode. It is used by the CPU_Input Multiplexer to enable multiplexed data from the DI or MD Busses·onto the D' Buss. ·
. \·
Input signal indicating to the CPU that valid memory or input data is available on the D' Buss. Absence of a true (logic 1) READY state will cause the CPU to enter a WAIT status condition. The READY signal is controlled by the Memory and I/0 Synchronization logic."
~- ' ·f: '
Active high output signal indicating that the CPU is in the WAIT state.
Active low output signal used during memory write and output operations. It indicates that data on the D' Buss and D Buss is stable when active (WR= 0) •
Active high input signal requesting the CPU to enter the HOLD state; used by direct memory access devices. During the HOLD state, the A Buss and D' Buss are placed in their high impedance condition so that they may be used by OMA devices. Not used in the car space system.
Active high output signal acknowledging the HOLD -request and indicating that.the A Buss and.D'Buss wi_ll go to their high impedance condition. .: .
Active high output signal indicating the state of the CPU internal interrupt enable flip-flop. The flip-flop is controlled by the Enable and Disable program instructions and inhi_bi ts all interrupts if it is reset. It is automatically reset by the RESET signal and at the start of the instruction fetch during an interrupt cycle. It is used by the Priority Interrupt card to control interrupt requests.
.,
INT
RESET
RES ETC
CLK
MW
OUTS
CM
WRBCCI ~
Active high signal requesting a CPU interrupt. It is generated by the Priority Interrupt card in response to interrupt requests from peripheral devices. If the interrupt enable flip-flop is reset or if the CPU is in the HOLD state, the INT request is not honored. Acknowledgement of an interrupt is indicated by the INTA status signal. During an interrupt cycle instruction fetch, the next instruction is fetched from the DI Buss instead of the MD Buss.
This active high signal clears the program counter and instruction register in the CPU and resets the INTE and HLDA flip-flops •. After removal of the RESET signal, the CPU starts running from location O in memory.
A high-to-low transition input here engages the Power-up Restart logic directly. This input is provided from the Console card. It results in the generation of a RESET input to the CPU.
10 MHz crystal-controlled clock oscillator output.
2 MHz phase 1 system clock signal (derived fromCLK).
2 MHz phase 2 system clock signal (derived fromCLK).
This active-low input controls the READY input to the CPU. When inactive (CR= 1), it forces a notready condition. CR is generated from the Console card and is used in single-stepping the CPU.
This is an active high write signal to the memories. It is generated by the Memory and I/0 Synchronization Logic. -
This active low signal indicates an input operation (INP = 1 and OBIN= 1) or an output operation (OUT= land WR= O). It is used to directly enable Device Address Decoders in selecting I/0 devices and is synchronized with WR for output data transfers and OBIN for input data transfers.
This active high signal is the output status condition synchronized with the data stable condition (OUT= 1 and WR= 0). It may be used directly to enable Device Address Decoders for output device selection.
This active high input forces the CPU Input Multiplexer to select the DI Buss. It is generated by the Console card and is used when jamming console control instructions into the CPU.
6054, p. 3-11
WABCC ~
INTA
SELOl ••• 16
SELI ••• 16
Logic O interrupt request signals to the interrupt . priority control. IRI has higher prio:r::i ty and overrides IRO.
Logic O acknowledge signal which .clears the interrupt request in.conjunction with the INTA signal.
Active high output from the status latch on the memory control card at the beginning of an interrupt cycle (at SYNC time) which acknowledges the reception of an interrupt in the microprocessor.
These active low strobes from the Output Device Select Decoders enable the 8-bit latches on the output buffers to store data from the D Buss (under program control) • ·
These active low strobes from the.Input Device Select Decoders enable the-8-bit buss~ports to input data onto the DI Buss (under program control).
The individual input lines into a buss port; e.g., _I2 Bo is the least significant bit line connected to input port no. 2. I16 B7 would be the most sig-nificant bit line of input port no. 16. · ·
The individual output lines from the 8-bit buffered output latch. 01 Bo is the least significant bit position in output buffer no. 1.
CPU STATUS INFORMATION
The following eight items are CPU status information that is output by the CPU on the D' and D Busses at the beginning of each machine cycle. They appear on the busses at SYNC time and are captured in the Status Latch I/0 Memory Control card.
INTA (Do)
WO (D1)
. HLTA (D3)
6054, p. 3-12
Acknowledges an interrupt request.
Indicates that the current machine cycle operation will be a write to memory or to an output device (WO= 0). WO= 1 indicates a read from memory or input operation.
Indicates that the A.Buss holds the pushdown stack address from the CPU Stack Pointer.
Indicates that the CPU i~ in the HALT state (HLT instruc.tion executed).
.,
WABCCI
Indicates that the A Buss contains an output device address. The D Buss will contain output data when WR becomes active.
~
Indicates that the CPU is in the fetch cycle for the first byte of an instruction.
INP (06)
Indicates that the A Buss contains an input device address. Input data is placed on the D' Buss when OBIN is active.
Indicates that a memory read will take place in the current machine cycle.
TIMING
Instructions vary in length from one to three bytes. Each instruction requires from one to five machine cycles for complete execution and each machine cycle requires from three to five time states. Machine cycles are denoted M1,M2,···,M5. Time states are denoted T1,T2, ••• ,T5. Each time state has a duration of 500 nanoseconds (one system clock period). The CPU has three other states which last an indefinite number of clock periods. These are the WAIT, HOLD and HALT states. Their duration is controlled by external events and signals {READY, HOLD, RESET, and INT).
Machine cycle Ml is always used to fetch the operation code, or first byte, of the instructions. It lasts four or five clock periods (minimum), depending upon the type of instruction, plus one WAIT state required for memory synchronization. All other machine cycles normally last for three clock periods each, plus one WAIT state required for memory and input/output device ~ynchronization.
Refer to Figure 3-3, a timing diagram for a typical machine cycle, and Figure 3-4, a simplified processor state diagram, for the following explanation of timing.
During time state T1, address information is sent to the A Buss. Time state T1 is indicated by the SYNC signal and processor status information is placed on the D' Buss. This status describes the current machine cycle and is clocked into the Status Latch at i1 time at the start of state T2. Address information consists of the contents of the program counter during instruction fetch cycles, memory addresses during memory reference cycles, stack pointer contents during stack reference cycles, and input/output device addresses during input/output cycles.
During time state T2, which always follows Tl, the processor tests the condition of the READY, HOLD and HLTA signals. If READY is true, state time T3 is entered. If READY is not
6054, p. 3-13
°' 0 U1 ~ ...
tel • w I ..... ~
T1
IJ 1 . r"\
IJ2 I
A15.0
07.0
SYNC
READ .
WAI
DBI I
WR
A15.0 MEMORY ADDA, 1/0 ADDA
07.0 STATUS INTA OUT HLTA WO MEMR Ml INP STACK
T2 TW T3 T4 T5
I
rr\ f\ " r--"\ r\ ~I VIII, rri I VII 'lh I \ \_
- ----.....-.- - - - -
A -------~-------r---~ \ I
- WRITEMODE
_/ VJ ?Ill/I/A I DATA -
READ MODE . STABLE
~
I/ \
'• DATA •
!~ \ I STATUS • INFORMATION
DATA
SAMPLE READY OPTIONAL FETCH DATA, OPTIONAL HOLD AND HALT INSTRUCTION,
HALT WRITE DATA INSTRUCTION MEMORY& 1/0 EXECUTION ACCESS TIME
ADJUST
Figure 3-3. Basic CPU Machine Cycle
)
lolll....----RESET
(1)
READY+ HLTA
(2)
READY·HLTA
READY
YES SET HOLD F/F
11
HOLD MODE
I I I
'-----1-..C.~----.. - - - _J
YES
RESET HOLD F•F
NO
RESET HOLD F ;F
NO
SET INT F.'F
1-tOLD
INT· INTE
HOLD
SET HOLD F/F
HOLD
RESET HOLD F F
RESET HLTA
(11 INTE F!F IS RESET IF INT IS SET
WAEICCI ~
121 INT F,'F IS RESET IF INTE IS RESET
Figure 3-4. CPU State Transition Diagram
6054, p. 3-15
WABCD ~
true, the processor enters the WAIT state (denoted Tw} and remains there until READY becomes true. The READY signal is controlled by the Memory and I/0 Synchronization Logic and by the CR signal from the Console card.
If the HLTA (Halt Acknowledge} status is true, the processor enters the HALT state (denoted Twh> and remains there until an interrupt or RESET is received. INTE must be true (interrupts must be enabled} for an interrupt to be accepted.
If the machine cycle required input to the CPU, the input transfer signal DBIN will become true during ,2 of T2 and remain true through ,1 of T3 (including any intervening WAIT states}. If the machine cycle requires output from the CPU, the output transfer signal WR will become true during the first ,1 following T2 and will remain true through T3 (including any intervening WAIT states}.
During T3, data is transferred into the CPU from the.D' Buss if the machine cycle is a memory read or input cycle. Data is placed on the D' Buss by the CPU Input Multiplexer. If the machine cycle is a memory write or output cycle, data is placed on the D' Buss by the CPU. This data is transferred onto the D Buss by the Data Output Buss Drivers. The D Buss always contains the same data as the D' Buss.
During state time T3 of machine cycle M1, data from the D' Buss is transferred into the CPU instruction register (see CPU Block Diagram in Figure 3-5}. This data is the first (and, depending upon the instruction, the only) byte of the instruction. The CPU instruction decoder and control section then generates signals to control the internal data transfers and timing for the new instruction.
At the end of T4 (or T5, depending upon the instruction) of machine cycle M1, the processor returns to T1 for machine cycle M2 if the instruction requires more than one cycle. This continues through as many machine cycles as are required by the instruction. If the instruction requires only one machine cycle, then a new M1 machine cycle is started.
Only during the last state of the last machine cycle is the interrupt request signal (INT} tested. If INT is true and interrupts are enabled, a special M1 cycle is started. The program counter is not incremented and the INTA (Interrupt Acknowledge} status is sent out with ~he processor status information. The CPU Input Multiplexer switches to the DI Buss, presenting its contents to the CPU via the D' Buss. The Priority Interrupt card recognizes the INTA status and places a single byte RST instruction on the DI Buss. The CPU executes this instruction, resulting in a subroutine call, a jump to one of two locations in memory.
6054, p. 3-16
WREICCI .~
01 112 READY INT RESET HOLD
: I . OBIN ' ' . , ., ,, READ/WRITE
AND INTE HLDA SYNC WR WAIT MULTIPLEXER
,I I •l 1l I~ 11'
TEMPORARY REGISTER ••
Z(81 W(8)
TIMING AND CONTROL REGISTER - L (81 H (8)
DECIMAL E (81 D (81
ARITHMETIC C(81 B (81
STACK POINTER (161 ~-~ ACCUMULATOR (81 PROGRAM COUNTER (161
1 ' READ/WRITE -I •
INSTRUCTION DECODE
AND CONTROL 1• I
' ACCUMULATOR I NCR EM ENTER LATCH (81 ii DECREMENTER (16)
If a ' I
, -
ALU(8} ~ •INSTRUCTION 14-REGISTER (8) ~ ADDRESS LATCH (161
~
• • 1/0 BUSS (81 - -- -
I ,. I '
FLAGS TEMPORARY 1/0 BUFFER -(51 REGISTER (81 ' AND LATCH 18) . ADDRESS DRIVER (161
,I
t ,I .. I
07-0 A15-0
Figure 3-5. CPU Block Diagram
6054, p. 3-17
WABCCI ~
3.8 MEMORY AND I/0 SYNCHRONIZATION
The access times of presently available standard memories and the buss drive capability of certain peripheral devices dictate that memory read, memory write and input/output transfer machine cycles contain a certain number of Tw states. ·This is to give memories enough time for address decoding and reading or writing of data and to give peripheral devices time to switch the DI Buss or read data from the D Buss. The Memory and I/0 Synchronization Logic provides this function by controlling the READY signal to the CPU.
When enabled, this synchronization logic causes the READY signal to go false at SYNC time, then returns the READY signal to the true condition after a certain number of clock periods. This logic is enabled, and the number of clock periods during which READY is false is selected by a jumper. Since this logic serves as the synchronization control for all memories and peripheral devices in the system, it must be set up to provide enough Tw states to accommodate the slowest device or memory element in the system. In most systems, the slowest component is the PROM. To cover the maximum access time of this device, one Tw state is required.
3.9 AUTOMATIC POWER-UP RESTART
The Buss Multiplexer includes a circuit that generates a RESET signal to the CPU when power is first applied to the Basic Processor. The RESET signal causes the CPU to begin program execution from memory location o. The INTE and HLDA signals are also reset.
An input pin (RESETC) to the Buss Multiplexer is provided. This may be used to cause a RESET signal to be generated as a result of an external logic condition or manually actuated switch. A high-to-low transition on RESETC will actuate the RESET logic. A momentary pushbutton and debouncing flip-flop are provided for this purpose on the Console card.·
. 6054, p. 3-18
~ .... ~ .. ,,/
REMO OISP
Jll
THUMB IIHEE SWIT
TEST PANE
THUMS WHEE SWIT
OUTP FROM
A/o CONV
J14
CPU TRAC llltQIIE
-<:> ....
C"BLE OPTO
CARD COUPLER
N451404 -0301 N451404
~ -160 I ~ =R
iffi IT. 39 m 5 rfi
CABLE CARO
N45 I 404 -0301
16 --BCD
TRJ\CK NUMBER
ITT"! fJ; 27
CABLE C ... RD 15 -FROM -... ;o MSB
JO BIT
BIN,-RY
I DATA
N-451404 -0301
1• --LSB
rn1 2 ~
CABLE DIFFEll!NT IAL CARO L !NE FROM RECEIVER CPU
~ CCS-077K ~ .. J776616 -187
~ 3 ft ,if I
N-451404 -0301 DIFFERENTIAL
LINE RECEIVER
~ CCS-0 77K ~
J776616 TRACK -187 NUMIIER
~ I 3 ~ ~ 3 ~
:S: INDICATES A TRI -STATE _OGIC BUSS• I ,o, OR OFF
INDICATES A U-OIRECTIONAL TRI-STATF _OGIC BUSS
~INDICATES DIRECTION OF !ilGNAL FLOW rn INDICATES CARO FILE LOCATION 0,. CIRCUIT
8 BIT BUSS PORT -
LIH-511
J776616 -200
-- S~Li -mi I [Ts
8 BIT BUSS PORT --
LBl-511
J776616 -200
- SE"Ll 6
ITTl ' ~
3 19 IT -BUSS PORT
~I-SI If}: L -- SELi 5
Ii 25
" " ::, .. 8 BIT BUSS ;; PORT --J776616
-200
LBI-511 - ... ' -~ I ~
I BIT BUSS PORT
LBl-511
J776616 -200 - SEL T 3
mi I fT.
8 BIT suss PORT
LBl-511
.)776616 -200 - SELi 2 -~ I fJ=:
1380 ---
LOC 18
--0383 (scAN CMPl
~ INOIC.ATES SHEET NUMBER OF LOGIC PRINT 0451333 SH. 02XX
SELI
~
.....
: < .,
.__
~
;;
0
......_
~
CPU IN
-{ o;~:s~~~ Tg~:~) Ml -MCC-814 cif
J776616-I 96
i ~ frf - HLTI' -
J na1N -
Ii - MEMORY CONTROL
::! MIM-894 0 SYNC - -- N451493-1101 -
~ I - ~
I Ll - r.ir'mlf j I I BUSS MULTIPLEXER - --
MOM-895 ~
J776616-194
~ I.~ - o-euss
(a a,,, DATA OUTPUT BUSS
I JI JI
Mn a, SS
8 BIT MEMORY OBIN
' DATA' BUSS
' " " ... : ::, SYNC .. ...
" l '' '' Cl ... a: READY
• PROM RAM J 1 I
LPM-596 IKX8 LRM-598
8080 N451-493 N451493 MICRO PROCESSOR -1oxx -JI 02
;.;; MCP-193
J776t 16-1 92 " f ~ rr Rl ~ Rl rr ... .. 5 ~
,I ~
osc . ------rFl ~
16 8 IT ,-QORESS BUSS TRI-STATE
····A
I
INPUT SELE CT REALTJME OUTPUT SELECT 14 DECODER
... ... CLOCK ~~ DECODER I-
LRC-531 - -~ ~ L00-503 J776616-203 - LD0-503
rflJ776616-IIIT ~ ~ ~J776616-l99~ L
18 7 17
I
INP
It I~ I~ INTERRUPT
l I SELECT LDI-530
J776616-202 r.r - JNTA
rFl L INTERRUPT PRIORITY CONTROL
19 - MPl-810 • - J776616-195 iNiA - o-euss -
fiio -
~ ~ -Dl-BUSS la BIT DATA INPUT BUSS -TRI-STATE\
-
Figure 3-6. Functional Description
8 BIT BUFFER -- LL0-515
J776616 ~ -201
filos--~ n:;
8 8 IT
BUFFER -- Ll0-515
07
J776616 MSO BCD SELO 7 -- -201 -
~ ~
8 BIT BUFFER
- LL0-515
Inc J776616
~LO-;;; -201 LSD BCD
. ~ ~
8 BIT BUFFER - LL0-515 -
J77Hl6 ~ -201
5ELC>4 -; ~ ~ i,
' ~!BIT BUFFER 05 -
SELO ., I L • IO 23
8 BIT BUFFER
. LL0-515
J776616 -· -201 SELO 3 .
Rl ["Ti '
8 BIT BUFFER
. LL0-515 ~
,<~,--,,, - J771616 -201 -
Rl ~
REL Y INTER ACE
CRB- 57
J776 16 ~ -175
rffl I \ r:: 5 38
--
--
PULL UP RESISTOR g.2K"'
N451054
~ -9902
i
-SH I 12 I 2\
OIFFEf!ENTIAL LINE
OR l~ERS
CSS(l76 J77C616 =.... -• a•
~ • [T.
O I FFEJlENTIAL
LINE
ORI VE RS
CSS-076 ...... J776&16 -186
~ • r::;
CABLE CARO
TO 2 DIGIT DISPLAY # CAR SPACES
N45 I 404 -0301
~ 5 f;;
CABLE CARO TO
4 DIGIT BCD DISPLAY FEE't
N451 404 -0301
~ 12 rx-
CMLE CARO
TO A/o
MUL Tl !'LEXER
J:~~~IH
N451404 -0301
CONVERT
SH I 12 r:r
CABLE CARO TO CPU
N-451 404 -0301
~ • ~
.
..
"
.
E AY
PACES
TEST PANEL OISP'LAY
TO A/O CONVERTCII
IIT
BINARY OATA
fO CPU
WABCO ~
6054, p. 3-19/3-20
SECTION IV
FIELD MAINTENANCE
4.1 GENERAL
·wRBCC1 ~
This section is provided to assist the field maintenance technician in rapidly analyzing and correcting problems associated with the Car Space Microprocessor system using a minimum of test equipment. The troubleshooting procedures are based on the concept of replacing faulty equipment subassemblies (printed circuit boards, power supplies, etc.) with operable spares. A majority of problems associated with the Car Space Microprocessor system will be repairable by this procedure.
4.2 TEST EQUIPMENT
The following test equipment (or equivalent) is required for fault analysis and troubleshooting of the Car Space Microprocessor system.
Volt Ohm Milliammeter - Simpson 260
TTL Logic Probe - Compatible with +5 volt logic, Hewlett Packard
Extender Card, Keyed - WABCO N451054-7201
Oscilloscope - Tektronix 454
4.3 GENERAL FAULT ANALYSIS
Since the Car Space Microprocessor and the interfacing equipment (yard computer, etc.) are closely related, su~pected problems should be thoroughly analyzed to determine the exact nature of the malfunction(s).
4.4 TROUBLESHOOTING PROCEDURES This paragraph provides a list of typical problems and appropriate remedies. Problems associated with the Car Space Microprocessor can generally be narrowed into one or more of these areas. Refer to Section V for interconnection diagrams and printed circuit board locations, and to Appendix A -Service Data for printed circuit board schematics and descriptions.
CAUTION De-energize the power supply using the rear panel toggle switch before removing or inserting any printed circuit boards. Re-energize the ac power after boards are installed.
6054, p. 4-1
WABCD ~
1. Trouble:
Data is not being sent back to main yard computer: however, at least one display is working properly.
Remedy:
Since a display is working properly, the problem appears to be in the communications channel between the car space rack and the main yard computer, and in the other display.
Computer Interface Check
Replace boards in locations 31, 32. Replace boards in locations 33, 34. Replace board in locations 21, 24. Replace board in locations 18, 19. Replace board in location 17.
If simple board replacement does not solve the problem, perform the following test.
Place the card in location 32 on an extender card. Check for a logic 1 going pulses on pin C of this card when a request for data is made from the central computer. If the pulses are not present or if the line. is a steady logic 1 or steady logic O, check the communications interface input lines from the main computer to the car space rack.
If logic 1 going pulses occur on pin C of location 32, perform the following additional check.
Remove the card in location 32 from the extender card and replace it in the rack. Place the card in location 21 on the extender card. Check for logic O going pulse on pins K, E, 16, arid 15 of location 21 when a request for data is made from the central computer.
If these pulses occur, check the computer interface output cable lines from the car space equipment to the main computer. If the logic O pulses do not occur,.· replace the cards in locations 20 and 14.
Remove the car space processor and check for broken wires.
2. Trouble:
Data is being sent back to the main yard computer but fail bit is present (or data is incorrect} and both display systems are working properly.
6054, p. 4-2
Remedy:
Replace boards in locations 24, 31. Replace boards in locations 34, 33. Replace board in location 21.
WABCCI ~
If board replacement does not solve the problem, check the communication interface cable to the main computer.
Do a bit by bit comparison of the address sent from the main computer and received by the processor. Using an extender card, make a check at location 31, pins c, D, N, 9, 15, 13, W, and 20 (pin c is the least significant bit). If data differs, check the particular line of input cables from the main computer to the processor for a fault.
In a similar fashion, check the data sent from the processor to the computer. Place the card in location 21 on an extender card. Check data on pins 8, H, 7, J, 20, 17, 18, and 19 and D, B, A, c, w, 14, 13, and X (pin 8 is the least significant bit).
3. Trouble:
Data is being sent back to the main computer and the fail bit is present, but both displays are blanked.
Remedy:
Set address on the thumbwheel switch associated with each display to zero.
1) If the space display shows 00 and the car space rack display shows 0000, check the cable connections to the A/D converter subsystem and check the A/D subsystem by replacing cards as follows:
Replace the cards in locations 24 and 25. Replace the cards in locations 21 and 23. Replace the cards in locations 17 and 18.
2) If the displays do not indicate 00 with a track O request:
Replace the cards in locations 22, 25. Replace the cards in locations 17, 18.
(For the yardmasters car space display also check the cards in locations 35, 37.)
· 6054, p. 4-3
WRBt;D ~
Check the cabling between the thumbwheel switches, displays, and the processor. Replace displays and thumbwheels.
4. Trouble:
Data is being transmitted back to the main yard computer and the yardmasters car space display is working, but the car space rack display is blanked, or not ·working correctly.
Remedy:
Set feet display address thumbwheel switch to track number 00, check if display reads 0000.
1) If the display reads 0000, check the wiring of the thumbwheel switch.
2) If the display does not indicate 0000, replace the cards in locations 22, 25, replace the cards in locations 17, 18, and check the wiring of the display, particularly power. Check the cable to the display. Check the thumbwheel switch connections.
5. Trouble:
Data is being sent back to the main yard computer, the car space rack display is working, but the yardmasters display is not working.
Remedy:
Set the car space display thumbwheel switch to track 00 and check if the car space display reads 00.
1) If the car space display reads 00, check the wiring of the thumbwheel switch.
2) If the display does not read 00:
Replace the cards in locations 37, 38. Replace the cards in locations 22, 25. Replace the card in locations 17, 18.
Check the wiring of the display, particularly power. Check the cable to the display. Check the thumbwheel switch connections.
6054, p. 4-4
6. Trouble:
Data is sent back to the main yard computer, with a fail bit, only 1 display is working.
Remedy:
Refer to trouble no. 2 to check the computer interface and then refer to no's. 4 or 5 depending upon which display has failed.
7. Trouble:
Data is not being sent back to the main yard computer and both car space displays are not working.
Remedy:
Check the light emitting diode (LED) on the card in location 11 behind test point 6.
1) If this LED is on and blinks off once a second, check if the LED on the card in location 12 is blinking on once a second. If both LEDS are blinking:
Replace cards in locations 21, 23, 24. Replace cards in locations 18, 17.
2) If the LED at test point 6 of card 11 and the LED on card 12 do not blink, check the position of all toggle switches on the card in location 12. They should be off with their handles pointing to the right.
Press the Reset pushbutton (2nd pushbutton from bottom on location 12). If the system now operates, refer to step 3; if not, go to step 4.
WABCD ~
3) De-energize the ac power with the rear panel toggle switch then re-energize. If it does not work again when power is reapplied, replace the card in location 12, and de-energize and re-energize power. If the system still doesn't work, replace card in location 10, and de-energize and re-energize power. If still not working, go to step 4.
4) Check to see if any LED is on. If none of the LED indications are on, check the ac power input fuse at the rear of the card file.
If the fuse is good, perform a voltage measurement test as !ollows:
6054, p. 4-5
6054, p. 4-6
a. Remove any or all printed circuit boards from the card file.
b. Connect the power cord on the ·card file to a 115 vac, 60 Hz source.
c. Using a fully keyed extender card (N451054-7201), measure the following voltages in the listed card locations.
Location 1 measure:
+5 volts +0.5 volt de on pins 21 and Y -9 volts +0.5 volt de on pins 20 and X
with respect to O volts at pins 22 and Z.
Location 8 measure:
Same as location 1.
Location 9 measure:
+5 volts +0.25 volt de at pins ··21 and Y +12 volts-+0.5 volt de at pin X -5 volts +0.25 volt de at pin 20 with
respect-to O volts de at pins 22 and z.
Location 10 measure:
+5 volts +0.25 volt de at pins 21 and Y with respect to O volts de at pins 22 and z.
Location 16 measure:
+5 volts +0.25 volt de at pins 20 and Y -9 volts +0.5 volt de at pins 20 and X
with respect to O volts de at pins 22 and z.
All other locations:
Same as location 10.
If voltage readings are out of tolerance, refer to the adjustment procedures of paragraph 4.5.
If any one voltage is incorrect or missing, replace the complete card file.
5) If the de voltages are present and correct, replace printed circuit boards.
Location 6, 7. Location 9, 10, 11. Location 12. Location 14, 19, 20. Location 8. Location 21, 17, 18.
Remove all cable cards and check if the LEDS on cards 12 and 11 are blinking.
If the system still is not functional to some extent as described in problems 1-6, replace the complete card file and check the failed unit for defective wiring.
8. Trouble:
WABCCI ~
Data is being sent to the CPU upon request and fail bit only occurs on certain addresses. Displays blanked on these same track addresses, but work normally otherwise.
Remedy:
1) Determine which addresses are producing a failure.
2) Check if these track addresses are used in the yard.
If these addresses are not used in the yard, the operation is correct, that is, unused addresses should produce fail bits and blanked displays.
If these track addresses are used in the yard, check the A/D converter and phase detectors associated with the failed track.
4.5 ADJUSTMENTS
Adjustments are limited to the power supplies. Proceed as follows:
4.5.1 Test Equipment
The following test equipment is required for power supply adjustments:
Digital Multimeter - Fluke 8000A or equivalent
Resistor - 1 ohm, 25 watt (minimum)
6054, p. 4-7
WABCCI ·~
4.5.2 Adjustment Procedure
It is necessary to disassemble the card file to gain access to the power supply adjustment controls. See Figure 4-1 for adjustment locations.
l. Remove one of the side panels of the card file by removing the four Phillips head screws on the side, and one screw on the bottom of the card file.
2. Slide out the plexiglas top panel towards the open end of the card file to expose the adjustment controls.
3. · Adjust the appropriate controls to obtain the correct voltage readings. Note that the +12 volt de supply and the -5 volt de supplies are not adjustable. The -9 volt and +12 volt supplies have an overvoltage crowbar connected to their respective output to prevent excessive output voltage. The +5 volt supply has a variable current limit to protect against excessive current flow caused by a short circuit.
a. If either the +12 or -9 volt supplies are a low value (about 1 volt), check to make sure the crowbar protection is adjusted properly before adjusting or checking the power supply.
TOP VIEW
+5 VOLT CROWBAR CROWBAR +12 VOLT SUPPLY ·9 VOLT +12 VOLT SUPPLY
·9VOLT NON·ADJ. SUPPLY
CURRENT VOLT 0 0 VOLT
0 LIMIT
6054, p. 4-8
0 0 ADJ. ADJ.
RES. TO., I • • gv 68
CARDFILE FRONT
Figure 4-1. Microprocessor Power Supply Adjustment Location
SUPPLY ·5 VOLT
I I re COM.
ZENER 1N4733
5.1 VOLT
..._, ,:'/
WAEICCI ~
If the crowbar(s) have activated, turn off the ac power, remove any loads connected, and move the proper crowbar potentiometer control in the counterclockwise direction slightly (l/8 turn). Restore ac power.
b. The -9 volt crowbar should be set to trip at about 0.25 volts above the 9 volt level. Set the output voltage to -9.25 volts (no load) and adjust the crowbar potentiometer until the output voltage just collapses. Reduce the voltage control on the 9 volt supply slightly. De-energize, then re-energize, the ac power. Now set the supply to -9 volts de.
c. The 12 volt crowbar can be set to trip slightly higher than the voltage present at the output by finding the point at which the crowbar fires and adjusting the potentiometer about 1/16 of a turn counterclockwise.
d. The +5 volt supply voltage can be set directly. Connect a 1 ohm, 25 watt (minimum) resistor across the output terminal of the supply and adjust the current limit potentiometer so that the voltage just begins to decrease, then adjust so the current limit is slightly higher (1/16 turn) than the limit point.
Remove the l ohm load and check that the voltage remains in tolerance.
Reassemble by repeating steps 1 and 2 in reverse order.
Power Supply Ratings
+5 volts +0.25 volt at 6.0 amperes max • • • • • • • • • • Voltage and current limit adjustable
-9 volt +0.5 volt at 2.0 amperes .-•• Voltage adjustable, overvoltage limit adjustable
+12 volt +0.5 volt at 0.5 amperes • 7 ... Non-adjustable, overvoltage limit adjustable
-5 volt +0.25 volt at 0.1 amperes . . . . . . . . . . . . . . . . . . . • Non-adjustable
6054, p. 4-9/4-10
( \
WABCC
SECTION V
DIAGRAMS
5.1 GENERAL
This section includes interconnection cardfile layout, and functional diagrams of the Car Space Equipment. The diagrams are provided as an aid in installation, operation, troubleshooting and repair of the Car Space Microprocessor.
5.2 DIAGRAM LIST
The following tabulation provides a complete listing of all the diagrams herein which are identified by WABCO drawing/ sheet numbers.
WABCO Drawing/ Sheet Number Description Page
0451333/201 Data Buss Multiplexer 5-3/5-4 0451333/202 I/0 Memory Control 5-5/5-6 0451333/203 1024 Word 8-Bit RAM 5-7/5-8 0451333/204 512 Word PROM and Interrupt 5-9/5-10
Control 0451333/205 Console Card 5-11/5-12 0451333/206 Priority Interrupt 5-13/5-14 0451333/207 LDD503 5-15/5-16 0451333/208 Real-time Clock 5-17/5-18 0451333/209 Latched Output Interface 5-19/5-20 0451333/210 Latched Output Interface 5-21/5-22 0451333/211 Buss Port Interface 5-23/5-24 0451333/212 Cable Connectors 5-25/5-26 0451333/213 Differential Line Receivers 5-27/5-28 0451333/214 Differential Line Driver 5-29/5-30 0451333/215 Cable Connector Interface 5-31/5-32
~
6054, p. 5-1/5-2
'
SH. OIOI.
of':i
.... lier
... .... 111.
1111
+uv
+12v
0
• a
L
..OWEl'I CONNECTIONS \.OC. 9
GNO(ov) - !"INS 21'.Z +5 VOLTS - PINI II Y
+12 VOLTS - PIN X ' -5 VOLTS - PIN IO
INTltL IOIO Cl'U
> • ' )~.~~· 2
' & "" INH r----.._ SH· > ~~····
!~
;:f144 ;~ ~ SH.
0203 0204 0207
_:~ ~~ ~
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.,
> I _ ==, 14 ).~ ~
> I ==, ~ A(4 )
0204
SH. OIOI
~·"· ~0105 10
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+1v
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<-E-.. SH.~
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i:g!~ -« l I 1r~: SEL
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g:g:~ 0211 17 +sv 0203~ 0204 Ac
( l I IIoA
--« & I Ir,. R +•
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0103~ 0104 Ao
• +s ma (;>--!!!! 0111 AL 11 +sv
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p
---« ~ I Ir•• --« . .! I Ir,; INPUT
QUAO
--<( ll hoc""" 2~ IIIT I
--<< ~ I I TRI-STATE Iro
0105~ •1•• "" O II 14
--<< .. ~ I lroo
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0111
0103~
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0115~
ii +1v .... 0 Oii i
~ 0113 .. +sv 0104
····~ ,,. +1v .... "" 0111
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mT
--<< , I Ir°"
~~ 'I 11•• ~~ I. I 11:.•NPUT --<< I. I lr,c""x
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i I II•c ----(( TRI-ITAT£
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CENTRAL PROCESSOR ICP-893
Jn6616-1!12
3
., ~· • • T,-, +sv
ux:. 9 SH.~ 0105~
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~
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:~
> • )." lll r:--,,..._ o~
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SH OIOI OIOS 0101 OIOt t210
>•>.~ ;~
v
DATA llJSNJ.1.cPLEXOR J776616-i94 LOC 10
TP-7
SH. tj • )) !SUI G>gu~
I >~~; I
MJCl'IO PROCESSOR Cll'ICUI
IU:QIG O tiv74±.!~ CAR SPACE EWI PMENT
SfANlARO Cl RCUI TS
WRBCCJ ~
1tP
6054, p. 5-3/5-4
NOTE I: REMO VI TERMII ADD JI TERMI
SH. 0201
SH. 0201
.... 0201
SH. 0205
SH. 0201
SH· 0201
TP-1 +sv- IOMHZ y UW'ER BETWEEN
C &. TERMINAL 4 XTl,L
ER BETWEEN _r- osc C &. TERMINAL I
°T
-
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CR ACK MD
> 00 « Do Qo p
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> 03 8
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> 05 u « 05 LATCH Qs
<< > Pl o, Qa
> 07 • (<.., 07 Q7 x
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QA QB QC QD QE
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~~ DMAC2
.rl ov·
rl > iii! (<.., 10
-I l.
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T I T I
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PA QA
PB QB
DECADE
PC COUNTER
~ QC
PD QD
(
MR O<
y
~ 1' ~t£03 ( t· ( ~~EDI ( ~ LED.( LED4 OUT lNP HLTA lNTA
'I'" '!F ~, -'-.,,
LD-
_,
~
~
j ~ -
'
' p 10 MHZ CLOCK~ o~i
' ' • ~SH.
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TP-2
y ... E
TP-3
y ii"j '
4
• { ... ~ ii G>, 0:~i ~ i INIA(9 J~i • 0207
, STACK ~·
-MR
=
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y
TP-4
y
TP-1
y
( w >Ht.TA~ SH. '
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•
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OUTS ~o~f ~>-----
-.-..... TO ~>-----J-O_RO_t.__.;'p~~~ i ~ K
USED
D > r~ : ,,.... 1 1 ... M ,_,,_ "~.,, 1 1 1 ~
3
N451493-1101 LOC. II Z ,22
,m11•.o. Dv1_4412.
CAR !:PACE E~I PMENT ST ANJARO CI RCUI TS
~....... ace wtS1111HGUSE • -E COMPAIIY
~ UNION S.WITCH I SIINAL···DIVlSfflll . _.., __ _ =::::: .. 1101 4 51333 I ••••I••••
_) s1n -•wt-.-~ .....,
1lP
r
WABCO ~
6054, p. 5-5/5-6
SH-0201
[v DO (j I
[v DI (~
E> Pi (~
Iv 03 (~
• (v 04 (~ - . [v 05 (i
NOTE I JUMPER TERMIN>-L G TO 14 ON PCB TO SELECT flAM ADDRESSES OFFF HEX
OCOO 8*x THRU
I
[v DI (~ 7
r;;:> 07 <~ •
o:\:i r;i> ""' <! K
C!::::> AO (j .. G:> Al (,f
I f ~ +sv =i==-1--r--+-r;:-~~~jl~,~I~,~~ I ' I ' I ' I ' >o I '
Al
~ I 024
SHOZOI
N I:!:> ,.. (~ p
G:> "' ~ ~ M (~
s G> A5 <$ ~ Af (~
u C!:> A7 (~ v
[u ... ~ (i::> At (j
12
A2 WORD
x
" I BIT
A4 STATIC
AS RAM
Al
AT
Al
At
cs cs
TP-1 li========~~-r••v {
Iv 'fO ~ A
.... 0201
13
[v "" <~ .. [v rn <~
15 [!:> All (! D .. 17
..
l'OIIER CONNECTIONS LOC. I
.... (ov) - PINS .. z ~ ~tll : ~:=~ ~~=~ (WIRED BUT NOT USED)
I OF 16
OECOOl:R
ENABLE
D Q10
~ ~~~-1 ' I
I I I I I I I L-
G
NOTE I
1024 WORD 8 BIT RIM LllM-598
N451493-I HE LOC. 8
SH-0201
MICRO PROCJSSOR CIRCUITS
CAR S'ACE EQ.11 PMENT STAIIWIO CIRCUITS
WABCO ~
1& ......... ~
6054, p. 5-7/5-8
.... OIOI
... ....
Ci::>' AQ
G>-"-1--
~;
j
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-•v +ov
AO .. A2
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00
01
02
03
04
05
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u
,~
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ING JUMPERS
C D TO F'
NC
0
0
0
0
0
D
0
0
rys
SS OIFF HEX LS G TO O
H TO I
L'/,°1, TO 2 H TO 3
' 1 . I
c
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~ ~ ~ ~
+sv
.... 0101
' ~''"d-·~ • 2'
'~ ' 3 NOTE I
I OF 11 4 DECOOEA
11 ', A __,--......,.._ ~ m « ~m,.,
Ii> AU (( • F,, .. q;::.
~-ft CONNECTIONS LOC. I THAU 7
~"ed~;l : ~::: :! ,~ -I VOLTS - PINI zo;x
ENABLE
512 W<JID PRCM LPM-596
UN451493-IOXX
10
II
··~" 11 Jl .. I 5
16
17
(OCTAL) NO. s
LOC. 6 & 7 ( l BOA ROS R£qu I RED)
SH. ~Jmf <l D
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8
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! 8ATES
II .... 0107
......._ .. ,LL UP I ,. y ,, '• , QUAD ,a -, INY£RTINI
•} TRI-STATE BUFFER
' 8ATES
'!
•• .. y '' •• . 1} QUAD -INVIRTINI
II TRI-STATE , GATES
•1 17 ,, y 'l) . .. . '; K , L ,, £
-' T I ,_
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+sv -J+,N.v ........ tl.----......J
-
-
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Dl q3
04 q4 CPI CPI
y CJ
I I
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LOC. 19
Ml (:RO PIIIQCE:$99,. CI ~-"-t ll
CAR S'ACE EWIPMENT ST AlllAAIJ CIRCUITS
WRBCC ~
6054, p. 5-9/5-10
SH.~ WAIT ~ 0201 Y 16 +sv
TP-1
o::~~ Ml ~ 14
.... ~BmT4 <i 0207 ~ 2
( [> Ef uo, + SH.I!!:> HI.TA < 0101 IF
~
RUN INDICATOR
22,zy
i I cR CY SH+ ~ BC 0202
A
IS
17
SH. 0101
·-~~~-1'~"--~o~i ~- ~
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WABCO ~
6054, p. 5-11/5-12
O~; ~ INTE ~
SH. 0207
D
c
e
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... (~ J
R_! MEM LOC O
t.£M LOC I
MEM LOC II
•• MEM LOC 24
DO
DI
RI
TP-1
SH. 0207 <~
SH. OJ:01
••
SH. r:-:--... .. ~•u•ul--------< OIOI L!v1 ~
.... OI04
[!i> jlio
'
<l • .... r:::-..... 0101 L.!Y'-~I._N"-T"A _______ , <)
16
04
MEii LOC 40
MEM LOC 48
MEM LOC 51
DI QI
•• Ql 4 BIT LATCH
03 Q3
lo• I\
q· I I I I
•01 QI
DI QI
4 BIT 03 LATCH Ql
•• Q4
h• PRl<JIITY INTERRUPT
I
22,zy 14 J776616-195 ll'l-8!0 LOC. 14
I
••
PRIORITY ENCODER
TP-8
+sv--'IIIN'--+--l
~ tNI j LO"> 0~~;
T I
l -~ DIO G9 10
. ·-"-'-'--r-(AQ
DU ~ \)'----=-.. ;, I >? DU [9
El
r, ...
TP-1
e
~------<A TP-7
)o ' ' IENA9LE I OF I DE:COOER
.\) 014 ~ ..
\) 015 r,:o>, L
\) ---- OJI ~
K
017 G9 .\) ----=-N
~ OOA ~
•• • ~ ACjij ~
•• 11
• x
-
SH. 0201
SH. 0104
SH • 0107
MICRO PROCESSOR CIRCUITS
11••1•.o. OV744 I 2
.J-Jf-/1:. I 11175
CAR S'ACE E~IFMENT STAMJARO CIRCUITS
WABCCJ ~
6054, p. 5-13/5-14
SH.1~ 0201 r.:............
H-:j G>
.r:. ~
SH, OIOI
A>
!!l•I I
1111 I
12
.. II
TP-S
10 I I ENABLE
A -1 TP-1
I OF II Dl:COD!:R
• y
41: .. -I' ' 4' u
SELO
SELi
SELZ
S£L3
SEL4
S£L5
SELi
ULT
SELi
SELi
1£L10
SELi I
SELi!
HLl3
SEL14
lt::LU
SH. 0210
c ~ l ~ 4 SH.
~0209
~ •
-- SH. ~0101
SH. OIOt
SH, 0101
TP-1 l ! D r ~ ...... [!;>.::; II
u.z
N
.. LOO-S03
J776616-1 t9
TP-4
" LOC. 17
SH • 0201
SH. OIOI
SH. 0101
SH. 0101
SH. 0202
AO SELO
SELi
A2 SELZ~) c>hlf
II
l"7:> A3 ~L S[l-3~
~
TP-3
10
K
TP-2
v
II
II
u
ENA8LE
I OF II DECODER
SELi I
... OIII
'"'· OI04
SH. 0104
i! D .... 15
r )D "Yl,b Hr !~
u.z ~ ... ... OI04
N
.. LOO-S03
J776616-119 LOC 18
..
MICRO PROCESSOft ClflCUITS
CAR SPACE EWI l'MENT STAMlARO CIRCUITS
WABCCJ ~
!fl
6054, p. 5-15/5-16
:;:2 A
o~i [_y 101f1Z CLOCK ~ CLOCK lli IC COUNTER
•
C l 1!112 I C?UNTER H COUNTER I ( c ~ 10 +10
C R
:'~o
+1v (••-·,)· t.2K
l~OA 4BIT Q•
1/•• I
LATCH
Oa Qe II v
Ile Qc " ' ••
OD Qo c, ~ V-
ov' I
""·
I
14 0107 _
§> 6GI Sil.mil
:: orJ7 co
12 +sv
1 ...
_Laz,z ~ .... v
c COUNTER
~10 c COUNTER
':'10
!I
COUNTER
f10 c
COUNTER
flO
!!.
TP-1
uu;;_~f;D CLOCK
x
_;:o , I c 1i1------+--------+----1
+sv
1
REAL T It.£ CLOCK LRC-531
JTI6616..Z03 LOC, 20
w
~~--'~~_.,,_......,BT
MICRO i-ROCE$SOR CIRCUITS
SH, 0101
tAR S'AC£ £~11 MNT SfAfollARO CIRCUITS
WABCC -•-.co.MY "j, , --._ '"' UNION SWITCH l SIGNAL IIYISNIII ~ _ ...... ~--· . __ ... __ _
,---.. - - I c:-::"' ID I' 4 51 333 ~·- · PflAWINe NU-
WABCC ~
6054, p. 5-17/5-18
°' 0 Ul ~ ...
'"O
Ul I
....... I.O
' Ul I
Iv 0
:...i-11~ ,
n fL1?ii
I! !:?i; ~-~I
!: n !l
! i I~ i r:
.. :E r D, 'qi
20
01 Dt QI CN AY DI
I 4 ltT M .... T .... i I I .... 4 Ill T 0201 LATCH Ol14 OIOI LATCH r SH.
[)> Qi" co ---- -- 0214 D,
II
D• ~J Ll!Y AZ • ~.l I I I ID• Q v It J CP
SH. OI07 -~ "
-.....-
" ·~1 o, Qi ~ w
D2 Qi ~ 0. QI ~ 4 IIT B SH. 4 BIT " LATCH OZ 14 LATCH t o:~4
O:s ~ o1a2 ex D, Q3 0386 DB_
13
D• °'h~J TP-51 I I I Io. ~~ CP CP
·DI Qi~I I I I I '--i o, °'· 12
Dz ~ .... ~ j s lr~ 2 Oz Qa
9
4 BIT o:':i 4 Bl T SH. LATCH - ~0212
D, LATCH Q 04 2 o, Q, ~ 3 OF I 10
I 10· QM~ - ' o. Q• '
TP-1 CP 3 TP•4 CP I I
o~7 ~ 5EL04 (( ct:>'l'. 5' .... OI07 - LA TCl£D OUTPUT
LL0-515 SH. J776616-201 LOC. 21
0107
-- -- -- --- --- --- --- -- ---- ---- --- ---- -- -- -- -- - -- -- -- -- -- --- -- -- -- -- ---
SH. 0201
SH. 0207
SH. 0207
SH. 0207
:r·1111
yp ... ,
D1 Qi°!
Oz Qi .. BIT I H
~ SH. OIII LATCH _
o, Q,
D• Q4
I CP I J
5'
~~ D
D2 Qi" ~ 4 81T
a ~ .... LATCH OIIZ
o, Q,
' o. Q4 ~
c• c
o, QI
Dz Qi""
.... ~ ~SH. LATCH ••• o, Q,_ __,.,.
---
o. Q7 CP
SH· c:;;> USO (( c:(> )) moG!> SH, 121S F I Olll
SH. 0201
v
o,
~ 01 ; 1 -
4 BIT ~ SH, LATCH _
1
0212
o, Q,, 18
I
Tfl•I
D,
~I •
D, ~~ 02 Qz ~
" 4 Bl T r SH.
o, LATCH- 0 781 EA 0212
Q3 13
o. Q•r---1~ Cl'_ TP-S
o,
02
4 BIT LATCH
o, "'",Lil-~----,--···~""-
o. Q ~ II TP-4 CP
LA TCl£D OUTPUT LL0-515
J776616-201 LOC. 22
ti
o, Qi"~ .. "'ti ~¥2 « l)O ' 10, Qi . Qh D• Qi AY Da
o~i~ I I I H SH. T 11
4 BIT 0101 4 II T
LATCH LATCH
Os Qs AZ •• o, 1 u
~ o. ii. o, J c, • •
r-< •• o, Q•r----t
o, Qil •
02 [ o. ijil
a .. 4 Bl T 4 Bl T LATCH _ LATCH
o, Q o, q;
I " o. Q~ I o. ii.
CP
o, Qr~ I o, Qi
I 12
"' ;c [r Qi • 4 Bl T 4 BIT
LATCH _ LATCH
o, Q . o, Q, 10
I ID• Qh o, if.
TP-1 CP Tl'-,4 CP II
l 5' LATCl£0 OUTPUT
LLD-515 J776616.-201 LOC. 23
• 22 ,z
!!: n ,. 0 .. ,. !
I~ " 0 :0
n
~~ 1l c
nM ... -2 "' ~-~~ '":!i
°' 0 u, .,::,.. ... tO • u, I
"' ~I .....
.......... u, I
!\,)
"' ,,
°' 0 u, ,i:,. ~
'"O
u, I
"' w ......... u, I
"' ,i:,.
!!: .II __ ,
n ~ lo
!~ ~~ nm -s ill-
~I
1287
IZSI
~~ SH. 0113 ns
~
1114
• TP-1 y
~ o~i '
,~ Fl L
~ M
of~;i~ EZ H
~ £Y J
TP-3
- ~ 't SH.
0207
~ FJ 18
~ .. SH. i 0212~
FH X
I4B4 FO~
V TP-8
.. 10
.. II
.... OIOI
.... 0113
.... 0213
.Ql3
" _t!J2
II
.--t~~ I I I T >>---2il-G> 13
>--i ) I I I I , I~~
~< I r"I ~. I_!!l2
N
390
of~l~ 1
olr2
I r'\ ~( ~T
~< 11 I'\ ~u
1481
J4BO
• TP•T
BUSS PORT LBl-511
JTI6616-200 LOC 24
.t~;
-- -- -- - -- -- -- -- -- - -- --- -- -- -- -- -- -- -- ---- -- -- -- -- -- -- -- -- -- ___, -- --
I I~ ill I .. lg ,,, " .. 0 . ~
; ~ • ill i ~ ..
1:u:s, « oi~2 ki>' .
oi~;
SH. 021 S
SH. 0207
SH. 021 Z
I r"I ~< ~ IIBI
M
USS
H
1184
IIDI ..
TP-1
» 15
10 .... 0201
.. 2llG>J
ol~s
o~i
.~.
~~~< I I_.... I" ~
,~< I r"I ~
1681
u
TP-7
BUSS PORT LBl-511
J7766 I 6-200
·:: DU
II
rof~j
I I I I l
LOC. 25
~,
°' 0 Ul ii::.
"O
Ul I
I\)
Ul ........ l11 I
I\)
°'
11 ~-: ; "
"' "' .. I
! N
l ~ ~,
UN4Sl404-0IOI UN4510&4•IIOI LOC SO
LOC II CMIL[ ~REI ~R A/D""TACK
SH· 0209
~ h 21-1 ~? §
GRAY LOC
• ll !
y
10
l BU
! II
:1 •
! 12
~LOC
t
~ l
R
! ,. BR :~ ! ,.
;~ BR LOC
! sH. U9 o seo I cNVTj (~
0210 EK 21-9
J
H n F n E
n D
~ c
~ • ~
22,~Jv' ' A/0 MPXR -,-
4-PINSA
CA
2A
BA
IA
AA .. EA
2 - PIN 13A
PA
12A
NA
IIA
MA
IOA
LA
2 ... PIN 14/1.
RA
UN45 I 404-010 I
SH. 0209
SH, 0209
LOC U (COM!'LEUENT ARY) CML~CTOR 10 BIT BINARY DATA
LOC 2 - PJN 158 ____gaa ... "M )~
• BB
14B .. 138~
PB
128
NB
, ,._:r. ...
10B-2
LB
98
KB
•• •• JI
79-1.1!.
HB
•• Fl
O'
i l_$SQ.
1581
FK:>} FL/
SH, 0211
SH, 02: 11
----'iT ! " " "' 0 .. "' 0
n E !!l> >"' g ~~ i i :on om i g nm I --e ~-~i "':i
.l'..
!
M.Y
LOC .I - PIN Ill
VI • »-i
1••1
ov (u,z)
... SH· Oil I
UN451404-0301 LOC II CABU:
4 OIIIT OISl'LAY (FEET-tlCO) c~ -r
CONNECTOR
~ l § GRAY
Jl•3
9
i § y
JI •<4
OIB~ 1u• 10
~ ; BU
JI -2
II
~ ; JI -I
pas> (ual
It
~ :4 JI --C
,·
l t 0 JI-D
oH!..l_TI
0&85 {T2
0 68 ___ ll~ 14
~ " JI-ti
~ 15 ..
JI-A
::-1---JI-R (COl,M()N)
J ~ on,i \HZJ I (( 1 R Jl-e
L
~ H
C> "·•· ..... I ~t ; . Jl-6
F > 010> {Hal I ~ Y ~N t JI-S
'e
~JI~
·~ BU :·. 0784 (THI
01135 (TH2) JI-J
c :> 0781 (TH4) I (~ V JI-F
.s t .. UN451054-9902
"·~v~ UN451404-0301
LOC 27 FEET DI SPLAY Tl'tACK CABLE SELE~TCH C~
~ I GRAV !!.!
•• + u ;~:s I
~ ~~ T4
T8
.!!.!!
i !
l2
I !
ii
Ill.
LOC U PULL UP RESISTOR -,-
+sv
21-11
21-12
. 26-13
t&-14
26-15
2,-1 e
~ SH. 021 I
~I
FROM CPU
CABLE CONNECTOR ---r--
..
RACK c.-aLE
CONN£rTOR
J-14
RACK
UN451404-0301 LOC 35
c.-su
~
GROUND l.!K 1 /4W STUD +s~
(31-2 i) J735SI 4
DIFF Llr-E RECEIVER CCS-077K
J776616-187 LOC. 31
SH. 0211
FROM CPU
CABLE
~
••
RACK CABLE
~ J-14
••
30
R
UN4SI 404-0301 PCl!S 35 CABLE
~
H
RACK 1.!K l/4W GROU'fD +sv~
STUD (ll-21) J735514
~ D~
MICRO PROCESSOR CIRCUITS
CAR SPACE EWlf'MENT STANDARD CIRCUITS
SH, 0111
WABCO W£STIIIGHOUSE All llAK£ COMPANY "'-~ / UNl·O·N·· SWITC. H & SIGNAL DIVISION
...._,...~ SWISffl.U:POSTlfJl:I..~ ... ~ •••• , j DI 451333 ,. ,.":.:"' .......
11775 '"' ......... -.. ~ •••• j_
WABCO "V'+""Y"
6054, p. 5-27/5-28
'"·-< Ollt
UN451404-0301 LOC 36 CMS LE
~ RACK CABLE
~ J-15
p ~~
TO CPU
CAt!iLE CONNECTOR ---,-
TP-1
~ (~(fo-1:U:,-j,--·~~~~ E 9 2
~ ~:cl 8 7 5
~> ~ <:U: I C 10 I
:c ~ ~ 7
,M • ' .. • I L> ~. . 7
R •
~ II
TP-4
~ << << v • .. .. ~t-i
~ <~ y
• • TP-5 y
~) (, 13 13
~ •• ~ (, .. ] 1 17
~ <• .. .. .. '--<< ..
~ :c .. . .. ~ ~ ~
20 15 20
~ "
~ :c w I 2J
TP-a
' ~ \. 2-4
OIFF Lll'E DRIVER ~1 CCS-076
J776616-IB6 LOC 33 RACK
GROUND STUD
SH. 0109
8
UN4SI 404-0301 LOC 36 CAIILE
~
R
RACK CA8L£
CO,CTOR'
TO CPU
CAaLE CONNECTOR -r-
~) « ' --·« I:& K I C H 30
..,. " I M
..,-------~ 7 F
R H
'T ----~ t p
0
..
.. c
..,. " .. . .,.
20 ,,
..,.. "' W T
x "
DIFF Lll'E DRIVER CCS-076
J776616-IB6 LOC 34
0
..
.. 47
.. RACK
GROUND STUD
..
..
"
40
..
.. MICRO ,.ROC[SS:Q_!t c;J_RCUITS
CAR SPACE EClll PMENT srANlARO CI RCU ITS
WRBCC ~
6054, p. 5-29/5-30
.... 0201
r.;> 0880 <~ ECA RLYI I
' ED OISI c RLY2 l
la"> 0182 <~ EE E RLY3
' O 83 ~ EF H RU4 7
~ 0184 <~ EG K RLY5
~ 0185 <~ M RLYI II
In'> 0886 <~ P RLYt 13
~ 0187 <~ S RLYI 1$
~ U RLYt 17
~ W RLYIO It
(31.y) +sv
+sv (u-21)
CRB-457 J776616-175
UN4~~:o::JOI 2 Dl61T(:~0)015PLAY CABLE CONNECTOR # OF CAR SfACES
I I~ §RAY Jl3
[1---- ; UIR t § ~d 8 • u ~ ~--T
2 U2 ~ V f--t1 ~ .. : , ~ ) 3 ' r--:r-7.> u, 10 ~ D
) ~ eu a== ; "'": 6j ii 4 II ~ ·:
) R { ' G t=1l ' J"• l
• J Tl t y F ~?. T R~ ' ;,_1_____U )
L ., "'µ 13 31
I T Q 9'
c::-:: )) T2R ~ ' µ 7 N 14 ~
~) T4 ! R ~ r . " . ' R • = r--)) I 5 "(. ,.
~ 11 Tf >.:----' ) « 18 •• TR k § ~>-fl
r---~ ' 10 rrgK t" I 1i f
T
• ) II
v 2 01air(aco) '""" I r---~ ' ' "- ""'" I f.-----UN451404-1101
LOC 31
> nf .. : ci , ; UI ~ R ~ YI" .(-pl ~ --+-----------------.....lJU!~P•L--r.(
oPT ICAL goyttµ111 I
TP-1
" TP-t U2
ff s'' , ~ ~L ,• I!_
LOC. 38 r-.':~- ~
'--f. U4 i Tr
8 : o § ! U4R :-PK Ul2 E> F
~: y § ~ ::. l--PM Tr rm [v 11 E
81~: PY
~ T2 TP•I
~ T2R [---p" '! 1185 5:> c "
SI~ y
, T4 TP·7
~ HR 1-pY r Illf §>
S·: .. & • '" , T 20 TP•I
. ; .:. I-P· r .•. E>
SH, 0111
MICRO PROCESSOR CIRCUITS
•«01•.0- DV7441
CAR S'ACE EQJI PIIENT ST AIIJARO CI RCU I TS
WRBCCI wtS1IIICltOUSE Ml 9Mt -MT
~ =.:~c:.!.:=.a:-c•:::::~101 451333
WABCO ~
6054, p. 5-31/5-32
APPENDIX A
SERVICE DATA
WABCC ~
This appendix provides the maintenance technician with printed circuit board schematic diagrams, descriptions, and parts lists and cable and diagrams and parts lists as identified in the following tabulation.
PCB Card Owg. No.
MIM-894 LPM-596 LRM-598 MCP-893 MDM-895 MCC-814 MPI-810 LDD-503 LDI-530 LRC-531 LL0-515 LBI-511 CRB-457 4000156
N451054-0301 N451054-99xx
Description
Memory and I/0 Control (3 Sheets} PROM Card (2 Sheets} 1024 Byte RAM (2 Sheets} Central Processing Unit (2 Sheets) Data Buss/Multiplexer (2 Sheets) Console Card (2 Sheets) Priority Interrupt (2 Sheets) Device Address Decoder (2 Sheets) Device Interrupt Control (2 Sheets) Real-time Clock (2 Sheets) Latched Output (2 Sheets) Buss Port (4 Sheets) Relay Card (2 Sheets) Power Supply Schematic Optical Isolator Interface Cable Card Terminator PCB
A-lA A-2A A-3A A-4A A-SA A-6A A-7A A-BA A-9A A-lOA A-llA A-12A A-13A A-14A A-lSA A-16A A-17A
6054, p. A-1/A-2
WABCD
"-"'•~ CDITTRDL LOGIC. lnC.
MIM-894 Memory and 1/0 Control NINE TECH CIRCLE
• NATICK, MASS. 01760 • 617/655-1170 Dwg. No. 9000112
REV A 12-11-7 PAGE 1 OF
Power Requirements
250 mA @ +5VDC
Load/Drive
Input loading and output drive capability are given only for signals that might normally be employed by the user. Output drive capability is given in terms of reserve capacity - capacity available in addition to that used by a configuration of the following cards: MCP-893, MIM-894, MDM-895, MPl-810, MCC-814. Quantities are in terms of TTL loads.
Inputs
DMAC2 ~ 1
Outputs
CLK 5 OUTS 9
ii 5 ioRo 10
ii 5 READY 9
,12 9 s'YNC 9
MW 10
{Specifications subject to change without notice.)
© Control Logic, Inc., 1974
MEMR
Ml
STACK
9
7
9
9
Appendix A 6054, p. A-lA
CJ'\ !}:,I Oto Vito ,i:,.. (I) ... ::,
p, to ...... . ~ !}:,I !}:,I I
..... IXI
---- .,.._,,._ :. =--~ ':' = = :.:..-=::: -·---·-_____ ......
1
r----ID'ia.
9 LOAD
1ic.
-=- YI UI .l'"I , , rn:;>121z
+Sv
+sv
GIIO
~·"'" ,.. e CL.k
2 • I • ~CLk
TPI
,'> t f f f f • +SY
+ f' f2 ~~ lc4 1cs
d I I I Ii -a_ -:-
~ ~
TP5
TP'7
DHAC t (JD, I I
TPz.
~¢i
--SEE S"EET t FOR REVl'SIO"S
S"'"'+..,N-0 0 0 0 0 O O O
i5m AC:I( II RI
+sv ?
U3 0'5i I"" I <lD Risii'
zi 119 h'l 1,s ho le IE> I+
I It I ~~A (ii; STACK
I
I j '----f-r' 11 -t--lt--l~~HLl"A ~- , I 5~
)>' v [D "fii'ffRI"
~ o.S Co ,:s i'.o Tt.S l.O .&.tS "'CMokv C....CLII! - ----.. (0) (I) (':Q (3) ~4) (S) (Tu, &'1"',ttS)
(.c.}r- --- -.J TP8
-~~~~~~~~~~~~~~~~~~~~'l' ..... ~~--[K>ffE~OV
wif !&:> I ' ... c.:::, ~MW ie .Jr\t1f\Q(?ir" ..
,):, ., ' ['.!:> ±OR:> 1 ,; 21(> :;., t,.,.•, "'"
Diii"~
\ .....
-~ CONnlOt. LOGIC. INC.
~ ---
I ~:e I- ,--c1RC01T BOA •• ·-~ I/0 ANO MEMORY CONTROL -- ,\ 3000150 ID
-i---2
)
~I
°' 0 U1 or:,. :i:,, .. tO
tO tO CD
~ p,
:i:,, I-'· ·~ ..... n:i:,,
-ntll( ....... Mm IPUIFICAIIONI Ml TIC PIMll"UlY fll CIDfffllCI. LOIIC, INC. MIJ IMMJ. N01' K ....-ua.o Ga CICl'CD Oii UIID M nc Miii "fOfl ..... ARUIII GI: UU 01 ~NI llllNOUY IJIIIUII.Y Wllfl1I.N MffllQI,
____ ..... CIRCUIT DIAGRAM
~ '3\JM'PEA. C:-4 IS FACTORY 11'161'71. LLED, :rtJMPER MA'f 81=. '-"ANG,,Eb SY U&ER A::» ReQ(.)IRl!'D
@ RUBBER &TAMP L"TE1!,T At.SY REVISIOM APPROX. AREA SOOWN,U'i5.ING. W>ITE E'POX'( INK.
2. TUT T£AHIIIAL $YIIIOL >-I, l'IN COll11£CflON $YHIOL 0-
NOl'U:
VOLTAGE CONN~CTIO!:iS
.
PIN CONNECTIONS I A c.uc 2 8 lllllN 3 c 4 Clll. D 5 "'' E Cll2. b OuTS F MW 7 ... "_ H 'rNP R DH•~~ J ,--.,
9 K REA.I>"( 10 wlJ L~ II -=mT M .. Ill ~~-- N ll ':sTlloCIC p 0... 14 WO A Dt I 1:HTA s 0,,
I ~LTA T D• ,, ""'"'C u 04.
I V UC
I Ml " Die.
MEHR x 011 +sv v +sv G.ND z GHO
Kl:T n Sill JN:)
5"-'l-"Z.0
)
-- ... - .... -- A RELEASED FOR PRODUCTION l<>/.J,/7'( a.wil-
- 8 Rl:VISE'I> PER ECN NO, 45'19 II lt!fhlJ d..cJJ-
- c l'I.E\l\'oEO ?ER ECN 1-10 4'58S 11/••lrY ... ..., .... - 0 ~1'!!.EO OCD ECN l'I0,4G:.1il'Z. lr/1/1~ "- ,.,,,..
~CARO OUTLINE
~ ,-c==:.t'\....----------- -- - - ... l --- IQ2Q:SQ4QSQ6Q7QIQGQ ~
~ 0 ~ !oe oi llil!ll rru > I ~ (j rn~ v-@
~m ra __ m i:~ ty
'l I.: @•211"-"?-0< TE.l?Htl'I"'' CA/'l•lt»I I IS 821'2 U3 r.c. 'l:NlEL. I 14- -~ us r.c. T,'l:, I 1'3 5"'1404-H U'l r.c. T."1", 'Z. 12. '8N'1~2.N U2.,UC.. r.c. T,T I II ""''l<IH,2.H UI :r.c. T.X, I IQ SN'l4'1"'9'( U.d. :c.c. T.:r. ... 9 555·20o'l kcnt.,...;.. LED :tNDlc.e,:ro~ DIAL.CO I a l(IIOOA ..... CR'(1ll"'- OSC. 10 Mllit 1-\Crn)tlllV. I ..., C822'35 RI RES. 2'21< :t5'% l/4W A.6. 4, E, CkCl58kl02S'<' C2-C5 CAP. .o,uf' t \O" IOOV
I s IC!!.13BFIOllilc: Cl CAP. IU~t:IO"• 35V ~F 4 2000066 --- TEST SPEC CL
I :, 179-052- -- LAIEI..HANOLES M69+ CL
I 2 , .. __
Kit IIAIIIII.LHICIIO CARO, CL
I I 3nrn1151 CAAO,PlllllfEO WIR""' MlM-894 CL ... - -- -- - --·------- .;:,, ::-:o ·" :::...... «-1.8111:--_..._ __ -- c: :'., =ht --- -·
_._ __ .,,.. ,:: ,.u
--CIRCUIT BOARD MIM-894 - - -.~ • .a:. ~ I/0 AND MEMORY CONTROL - -'l " -;;17.;~ 1woo1so 15 rt rr '!!!"' '!!OM-SERIES - - - ---ff-- I - •-:;,
,1 ~8
)
WABCC ~
comRDL LOGIC. me. LPM-596 PROM Card
Owg. No. 9000040 REV A 7/16/7 PAGE 1 OF 1
NINE TECH CIRCLE
• NATICK, MASS. 01780 • 617/855-1170
lhe LPM-596 provides sockets and memory address decoding for two LP-256 256-byte PROMs (erasable and reprogrammable read-only memories) that are removable and may be replaced to "I oad11 a new program or to change a data base.
Although the processor addresses 16,384 bytes of memory directly, it is convenient to consider the memory as divided into "pages" of 256 bytes each and "chapters" of 16 pages each. The LP-256 is an integrated circuit (IC) containing one page (256 bytes). The LPM-596 holds two pages per card.
The processor directly addresses memory via a 14-bit field in the Address Data Latch. When addressing memory on the LPM-596, the 14-bit address is divided into three fields of 8 bits, 4 bits and 2 bits, respectively. The 8-bit field (the least significant 8 bits of the address) is decoded on the memory chip to select one of 256 bytes in an LP-256. The 4-bit field is decoded to one of sixteen outputs by a decoder on the card. Any two of the sixteen outputs are used as page select signals, one for each PROM page on the card. The choice is made by the user via jumpers on the card. The decoders are also equipped with a 2-input negative strobe enable gate. The signal into each input of the 2-input enable gate may be either a normal and a complemented signal, th!t source of which is one bit of the 2-bit address field. The normal or complement signals are selected by the user via jumpers on the card. This selection results in the decoder being enabled by any one of the four possible states of the 2-bit field in the address. This field thus divides a 16K address range into four "chapters" of 16 pages each.
SPECIFICATIONS
Input Loading
Output
Ao-7 Aa-11
Memory Data
Power Requirements
2 ua
1 load (TTL)
1 load (TTL)
150 ma @+SV; 90 ma @-'N typical
(Specifications subject to change without notice.}
AJ2-13 1 load (TTL)
A12-t 3 2 loads (ITL)
© Copyright Control Logic, Inc., 1973
Appendix A 6054, p. A-2A
...
m:x:,, O"tj Ul"tj ,l:l. (l)
... ~ p,
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:IIINF'l'RS
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(II
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CIRCUIT DIAGRAM
+sv
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(OCTAL)
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NOT(S:
PIN CONNECTIONS
2
' 4 s 6 7
R .2
H'o ___, ,,, I Aq ·~" 14 A, ISi ...... 16[A'i"i 11 18. 191 zc -9V Z.! .. sv IZl GHO
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HI MOc. JI M.Q7 I< l .Ml Ao NI A.1. Pl A2. RI ,&.-,_
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1sfTIONS
RZ. +SV ~
15 14
I I 13 f SN'M()4N I ':[C4 I T,C. MOOUI..E T,'X. I I 12 I SN741S4N I zc.s I z.c. Moovu. T. :z:.
11 :Z:Cf,l:C2 r.c. MOOUU: (see: NO'TE !S) 2 10 C9102.S ~t,R2 Rl:'$tST01'( IK:i:S~ l/4W A.IS. -
A/Rl<i t 2eAw• t t w1Re:,_1_~i:i!,~Ti:~<•oi.:10) 2"f. I a 1w.o-z:1e1-ot-G!II I TER"ltt1AL ia,.Ma10"
Lll 7 1!524-AGIO I I SOC.l<ET ~ f°2 I 6CSl!let='IOSIC C.7,C8CAPAC;ITOR IUi':t:IOXlSSV ~E' ~-s cKOS8)(1o!l'<lc1-cto f<:APAi:,r~ .011.1f':t:toXioov I ER=-:J IRITr 4 1003005 TEST SPEC · CL
t I 3 1119-~ I I LAIIEt,IIANDt.£, L596 ICL I I 2 IIIS-096 I I kl1,_HANDL£,IIICAO CAIID. ICL I I I I 1003001 I l CAIIO,PRINTEDWIRINC;.LPM-596 ICL -·- -- -- - ----
-.. --H-- I ,-.---·
===-=--= fe:244~ -- ... ...,~)#j « ........... -:::::-:= -.CIRCUITBOARO LPM-596 ~~ .":. ~ EIGHT 81T,512WORO PROM
H-- ~~-=-~r-~00~3F0-0~6~.--r -- IA .... ·-=-
.,/
ti
LRM-598 1024 te RAM
WABCC ~'V"
conTRDL LOGIC, me. NINE TECH CIRCLE
Owg. No. 9000042 REV A 7-16-73 PAGE 1 OF 1 • NATICK, MASS. 01760 • 6171851>1170
The LRM-598 provides memory address decoding and 1024 bytes of semiconductor random access memory (RAM). ........_ ·
Although the processor addresses 16,384 bytes of memory directly, it is convenient to consider the memory as divided into "pages" of 256 bytes each. The LRM-598 is based on a set of eight RAM integrated circuits, each containing 1024 bits. A byte is made up of one bit from each IC, so that the card contains four pages of memory.
The processor addresses memory via a 14-bit field in the Address/Data Latch. When addressing the LRM-598 1024-byte RAM memory module, the 14-bit address is divided into two fields of l Obits and 4 bits. The ten least significant address bits select one bit from each of the
· eight RAM ICs on the card. The four most significant bits are decoded by a one-of-sixteen decoder on the card. This output is used as a chip-select signal and assigns the memory on the card to a set of four contiguous pages. The output from the decoder is jumper-assigned by the user. There is also a decoder enable. If the system memory is limited to 16K, then the decoder enable signals can be left unwired. They are then pulled high and inverted on the card and thus always enabled. If more than 16K is required, the decoder enable signals may be used as Bank Select signals to enable the decoder and address a 16K bank. The decoder enable logic on each card may also be driven by external logic, where the external logic is controlled via an output ins truction and a device code. Such a scheme could be used to implement extra banks of 4K memaies that are associated with an assigned output device.
SPECIFICATIONS
Input Loading
Output
Ao-9 Al0-13 Bank Select
Memory Data Outputs
Power Requirements
220 ma @+5V typical
10 ua 1 load (TTL) 1 load (TTL)
1 load (TTL)
(Specifications subject to change without notice.)
Memay Data Inputs R/W
© Copyright Control Logic, Inc., 1973
10 ua 1 load (TTL)
Appendix A 6054, Po A-3A
"
"'),I Oto Vl 'ti ~ (1)
" ::s p, 'ti ...... . ~ ),I!)::, I w 0:,
.... .....,._ Nm lPICIFICAnoNI Ml lNl.....,., • CCllr.la usu: • .. ,.,, IIW..L .,, • .......aD • ..... M UKD M nc MS1S R1t IWU'IICNW. Cit 1111.1 • #'IMUUll llfflDlf ....... , ..,..,.. .......... ......... ClllffMII.I.OIIC.INC.'" CIRCUIT DIAGRAM
VOLTAGE CONNECTIONS
1 -, ..... ---.. .. r - r --1-r I A r Re:L. FoR PRe>oucr,o"" c..-t<-~ It)( hx,I
K~ R-4
~~~'"'H~V
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s
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f 22 8 s 21 e It 20 I) !t
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IO
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... .. N u v in ~ " " H u ti tf .. ..
~CARO OUTLINE
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"3
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NOTES:
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PIN CONNECTIONS 00 AL ~t>§
2 ~ I tll "'t>I 3 PJ.. CL. '°'t>~ 4 D~ OI ~03 m !:\04; F MQ!S 5 ...... ~ J;!§_ 7 o~ H.L .... .:
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KEY POS ITIONS 3,9,2~
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2102 rc1-:rc.s :r.c. Mooul.E
Airs A/8 T,J:, T.1:,
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119-052- I I LAIEl.,.~1101.£, L~98 IH-096 I I IUl;_HANDI.E.lffCAO CAIIII. 1003015 I I CAAD:PIUIITEii iiRl~] .. ll(,!~!l_9_!l - - -- -------~~ . . «mnma•u~ ............... ................ --
E"IE. ~L CL CL CL -
~~~~-~-CIRCUIT BOARD LRM-598 i-.:.,;;,:...-;a=--=---t==-----iEIGHT BIT, 1000 WORD RAM
- H-- II -;; 7.cn;-- 1()03014 A : ":' L-SERIES
"=' -··~·T ~1-1
,/
~I
~
MCP-893 Central Processing Unit
Dwg. No. 9000111 REV. B
Power Requirements
7-1-75 PAGE 1 OF 2
220 mA@ +SVDC 80 mA @+12VDC
5 mA@ -5VDC
Load/Drive
WABCC
""' ...... """" conTROL LOGIC. me.
NINE TECH CIRCLE
• NATICK, MASS. 01760 • 6171655-1170
1nput loading and output drive capability are given only for signals that might normally be employed by the user. Output drive capability is given in terms
Inputs
Outputs
of reserve capacity - capacity available in addition to that used by a configura_tion of the following cards: MCP-893, MIM-894, MDM-895, MPl-810,. MCC-814. Quantities are in terms of TTL loads.
HOLD
A15-Ao 20 INTE 19 WAIT 19
HLDA 19 WR 18
SYNC 18 OBIN 18
(Specifications subject to change without notice.)
© Control Logic, Inc., 1 '175
Appendix A 6054, p. A-4A
"'
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p. "ti I-'• . ~ !J:,I :i::, I
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CIRCUIT DIAGRAM
25 -2,;,
21 -2'} -30 -31 -32 -33 -34
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5 s Cl:.1>5&)(1031' Cc?Ato.7,E C./• P. • 01 Ui' t 10% IOOV REF' 4 20000"'8 --- TE'~'T ~C. Cl.
I 3 11'9-~ --- LAHL.HANDI.£. 118'13 CL
I z 113-096 --- ICIT, HANDL[.MICAO CARO. CL
I I "!0001'5'1 --- CARD PAINTED WIAING.MCP-693 CL .. - -- -- - ----................ ---- ,,, - - ~ ...... 18111:IIC. :--~== -crRCUIT BOAROMCP-893 .:.:.,. ·- •w - CENTRAL PROCESSOR
le =~~ ~M-S~~IES ~ -;-..;;;-- 3()()0156 ,: I":" I_.. l - I .. I
~!
WFIBCCI "'4!h'V"
CDMRDL LOGIC. lnC. MOM-895 Data Buss/Multiplexer NINE TECH CIRCU!
Dwg. No. 9000113 REV A 12-11-7 PAGE 1 OF 1 • NATICK, MASS. 01780 • 617/855-1170
Power Requirements
120 rnA @ +SVOC
Load/Drive
Input loading and output drive capability are given only for signals that might normally be employed by the user. Output drive capability is given in terms
Outputs
of reserve capacity - capacity available in addition to that used by a configuration of the following cards: MCP-893, MIM-894, MOM-895, MPl-810, MCC-814. Quantities are in terms of TTL loads.
M07-MOO 017-010 0'7-0'0
07-00 0'7-0'0
1/2 1/2 1
19 1
OMACl CM RES ETC
RESET mrr
1 1 3
9 9
(Specifications subject to change without notice.)
© Control Logic , Inc. , 197 4
Appendix A 6054, p. A-SA
~
°' ):,! Oto Ulto .,::.. CD ... ::,
0, to ...... • x ):,! ):,! I
u, ttt
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2 .. TEST TERMINAL SYIIIIOL >-1. PIN CONNECTION SYMBOL 0-
NOTES:
q
II
5
VOLTAGE CONNECTl':)NS
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14
C>"' I , • II ~ D7
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PIN CONNECTIONS It "-4At034 u<o R.Ec;. PAC. IOK .A e IO C8 \n&S Rt. fl.l=c:.. IOOI<. :ts% Y4W AP
I ., C61~3S P.I 12.e:s 12.K 'is"'/: '.1&.."1....../ A I 8 c.SU.S!S R.~ RE.S ? .. ?.K ± 5"Y. Y,4.w A 13 a 7 15ol>22SIC'l080 121c:3 C,4 c.AP. 2.,2.#J" '! 10-,;, 2ov &PRAC::.'E. I <.. CSl38Ft051{ c. r CAP. 'l UF :t10•/o "-'<'V iof'RAGE 3 5 c.w:o5S'J.1031C c.z..c.c;."' CAP .OIUF :!:10•/o 100V
REF: 4 200006'1 --- TEST Sf>S::. . C.1-
3 ·~05,Z- --- L AIEL.HANOU l'\895 CL
l llll-<196 --- ,or, HANDI.E,IIICRO CARO. CL
I, I I 'a0001'54- --- CARD PRINTED WIRING. HOM-1:-95 CL -- -- - --.. -............... ex ttllfflllll l.llK .. ................... -----....................
I UIT BOARD MDM-,395 -- - -- DATA 8US/l.1ULTI PLEXOR ·- ·- .,,.. -- -H-- 'I - --- --T1 1031 3000153 IB - ':"ti-SERIES
c - -1·
~I ~8
MCC-814Console Card Dwg. No. 9000115
REV B
Power Requirements
180 mA @ +SVDC
Load/Drive
conTRDL LOGIC. me. NINE TECH CIRCLE
7-1-75 PAGE 1 OF 2 •NATICK.MASS. 01760 • 617/655-1170
Input loading and output drive capability are given only for signals that might normally be employed by the user. Output drive capability is given in terms of reserve capacity - capacity available in addition to that used by a configuration of the following cards: MCP-893, MIM-894, MDM-895, MPl-810, MCC-814. Quantities are in terms of TTL loads.
Inputs
SISEL
Outputs
ct 9 RESET RES ETC 6 Dl7-Dlj1 RES ETC 10
(Specifications subject to change without notice.)
© Control Logic, Inc.,
9 20
Appendix A 6054, p. A-6A
,,..
°'!J:I Oto Ulto ~ (D ... ::,
p. to ..... • x >:x:, I
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'1
IO IO
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13
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RE' 2 l20000E>9 TI.ST Sl'>l:C. <:.1.. I l30001f>O CAB!),PAINTEQ ll:IRING, l'\CC-814 CL -- - -............... «....-..-:-. --... -------------- CIRCUIT BOARD,MCC-814 - -·- .... ..,,
CONSOLE CARD - -,, II ---.. ....--.. -··--· 3000159 E
~I
WABCCJ "V' ....... "V'
CDITTRDL LDGIC. lnC. MPl-810 Priority Interrupt
Owg. No. 9000114 REV A
Power Requirements
250 mA @ +5VOC
Load/Drive
NINE TECH CIRCLE
PAGE 1 OF 1 • NATICK, MASS. 01760 • 817/SH-1170
Input loading and output drive capability are given only fer signals that might normally be employed by the user. Output drive capability is given in terms of reserve capacity - capacity available in addition to that used by a configuration of tht following cards: MCP-893, MIM-894, MDM-895, MPl!"'810, MCC-814. Quantities are in terms of TTL levels.
~
IMSEL 2 IR7-11R> 1
Outputs
INT 9 ACKT~ 10 TF:rl'A 20 017-MO" 20
(Specifications subject to change without notice.)
© Copyright ControJ Logic, Inc., 1974
Appendix A 6054, p. A-7A
°' !):, O"tJ Ul"tJ .i::,. (D .. lj
A, "Cl JJ• • >< !):, :i:, I
-..J tJ:j
·ncsr DRAwtNGS MD SNCWK:ATK>NS Ml tHt rttorun, 0, CDNYMll LOCIC1 INC ANO SMALL M>T IC Hl"ROOUttb 011t CDP'ltO Oft UUO AS TH( IAStS fOllt IIANUP'M:JUttl Ofl SALi 01 lll'fWtATUS wnHOUt f.ll'M:Slll' WllflntN '"''**" W.tDI IJICllll CDNTIIOl lOCIC. lflC."' CIRCUIT DIAGRAM
VOLTAGE CONNECTIONS
TP8
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NOTES:
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PIN CONNECTIONS
' \ ... _ ,.,,,.,,
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CL CL CL --
==----=---== r ''/ .....__. d'& ,,&:=· ..ICll ........... ....._.. ·- ..... ..,..
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_,CIRCUIT BOARD MPI-810 PRIORITY INTERRUPT
ff- 11 ~ -;-.;;;-- 3:5 oo 16 2 -T; =-- ~~·.-_:.ERIE$__ - 1-::" , ..... --!±== I --~--- ____ I...., •
.,,i
,1 ~8
WABCC ~
CDITTRDL LOGIC, lnC.
Dwg. No. 9000049 REV
ess Decoder
7-16-73 PAGE 1 OF 1
NINE TECH CIRCLE
•NATICK.MASS. 01760 • 617/65~1170
Control of external logic and peripheral devices generally requires decoding of control byte output from the Basic Processor. Similar decoding circuits are sometimes required by the user in his external logic. This function is supplied by the Device Address Decoder card.
The Device Address Decoder provides logic for decoding a single 4-bit number into one of sixteen separate output levels for the control of peripheral devices and external logic. The card also includes four dual-input NOR gates that the user can employ for his particular needs in decoder enable control, decoded output gating, and so on. Combinations of Device Address Decoders and latches can be used to extend the input/output device addressing capability of an L Series system indefinitely.
The Device Address Decoder, LDD-503, contains a 4-line to 16-line decoder which decodes four binary-coded inputs to 16 mutually exclusive outputs. This circuit is useful as a data distributor for control of various logic functions and peripheral devices. Demultiplexing occurs when both inputs Gl and G2 (pins Kand 10) are at logic 110 11 level. When either or both Gt and G2 are at logic 11 111
, all outputs remain high. Four auxiliary 2-input NOR gates are provided for use as control gates for the decoder or any other user appl ication.
SPECIFICATIONS
Input Loading
Output
Decoder data input Decoder strobe NOR gate inputs
Decoder NOR gates
Power Requirements
60 ma @+SV typical
1 load (TTL) 1 load (TTL) 1 load (TTL)
10 loads (TTL) 10 loads (TTL}
(Specifications subject to change without notice.)
© Copyright Control Logic, Inc., 1973
Appendix A 6054, p. A-8A
"'
O"I ~ Ot-c, (J1 tO .i:,.. (1) ... ::,
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tl1
"'fflUI 0MWtNGS AHD 5".CWtr.AnDfft Mt 'fHt P"Mftffl OI coema. LOCJC, tte:. MD AW.l NOf K JIU1IODlaD Gii COPttD Oii USO M M auts FOii IMNUf'ACTUM. Cllt SM.I OI #'P'AMT\11 WllHOUT UPIKSSU .. MN MIJtUI. IUTOI .... CIClffllOL LOU:, INJC.'" CIRCUIT DIAGRAM
1P2 TP3 ' '
filTt = ll n.
:IEL 12 ;!;!::_ ... •I 'i; S[L 10
~Et.. I! UL IS JO ~ sm
~~ , ... 9 ~ mi 17 • SELIS :.:!.. re, O SlLl
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" • ~'Sn.4 C II "Q.l
CODE 8
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TRUTH TAe\.E 'rH- ~ ACTIVE .. , c.z D c 8 A ~ouTfl'\W
0 0 0 0 0 0 SELO
0 0 0 0 0 I sn., 0 0 0 0 I 0 'SELZ. 0 0 0 0 I I SIEL.3 0 0 0 I 0 0 SE~
0 0 0 I 0 I Sl1.5 0 0 0 I I 0 t.€\4 0 0 0 I I I SEL7
0 0 I 0 0 0 SELi 0 0 I 0 0 I !lltL., 0 0 I 0 I 0 SC.IO 0 0 I 0 I I Si'.LII
0 0 I I 0 0 !IELt1
0 0 I I 0 I SELl'S
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CONNECTIONS -·16 IREVtir>Eo PER. !!CM '"''4-S3B 1,oh/X'I.-~ ~I ~ARD OUTLINE
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,::!:..~?.'( oij ·Jrj
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I t ==•Y :r c.?.
15 14 13 12
PIN CONNECTIONS II I .,. .. ~
A ""' 10 -
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8 S£L13 J ~ REF 4 1003017 TEST SPEC CL 9 sa:1-1.c; K GI I 3 179-052- LAHI..HANIILE L 503 CL 10 G2 L 0 I l 18lHl96 KIT, HANIIL(,IIICRO CARD. CL II c M 8 I I 1003019 CARO,PRINTED WIRING. L00-503 CL 12 A N ,,.. - - -- -- - -13 IY p 2'( -·-·~ 18 Fl 2R ............. ;;;.,-.,. ,A -I 2A :,
_... .... ___ .,,_,.,, « ....... I.NII: IIC. IG 3"' T -- "'r:.£.L... J'}J/u 17 3v ll 'l!l8 ---18 48 v ......... ----- N"!iiirfU ~ --CIRCUIT BOl\RD LD0-503 -19 w 4Y - - -- - -·- .... . .,..
4 TO 16 DECODER( 4 DUAL NOR GATES 20 x -- -121 +sv y +s" u II ~ 1-;-..;;;-- 1Tc503018 Is 22 G.NP l GNP • r > r
l\t. J t'' 5 I o~,c !'!!!!! ':" L-SERIES 3 IC .20 !'!!!!! -::" --JJ.-1 -1-1
·.,._
LDl-530 Device Interrupt Control
Drawing No. 9000143 REV A PAGE 1 OF 2
WAS CC "-".A..""V'
conTROL LOGIC, me. NINE TECH CIRCLE
, NATICK, MASS. 01760 • 6171655-1170
lhe LDl-530 contains a collection of logic useful for extended interfacing to peripheral devices. Included on the card are 12 TTL-level tri-state gates with outputs organized for wiring directly onto Dl3-Dlo on the Input Data Buss, four output latches (two groups of two latches each), and two interrupt control circuits. lhe interrupt control circuits generate interrupt requests to the MPl-810 and LPl-510 Priority Interrupt cards. lhe interrupting device may generate an interrupt request with either a rising-edge clock signal {on IDRCT or IDRC2) or a negative-going pulse {on 1l51fl5T or TI5ifi'2). COSA is the latch control for RTSA and DTRA latched outputs. ~ is the latch control for RTSB and DTRB. COSA and COSB are normally direct LDD-503 Device Address Decoder output select signals. INTA is the direct CPU interrupt acknowledge from the MPl-810. Its logical equivalent for L Series is the inversion of INT ST • Control lines on the tri-state gate inputs are active-low and are normally direct LDD-503 input select signals.
SPECIFICATIONS
Loading and drive are in terms of TTL unit loads.
Input Loading
i'DRPT, i15R'n, IDRCl, IDRC2 4 TN'fA, ~' COSS, D3-Do, tri-state gate controls 2 ~'~ 5 Tri-state data inputs 1
Output Drive
RTSA, RTSB, DTRA, DTRB Dl3-Dlo__ JfflA, IRQB
Power Requirements
200 mA @ +SV, typical.
(Specifications subject to change without notice.)
10 20 10
© Copyright Control Logic, Inc., 1 '175
Appendix A 6054, p. A-9A
,.
m:i:,, o"O l11 "0 .i:,.. (1)
::, 0.,
"O ..... ~
:r :i:,, \,()
ll1
-ntU1: DM....-..s AND 5"'.CWK:AflONS Mt tHt "'°"-ll'TY 01 CGNfllOl LOGiC, PIC. Nm StW.l. Nl7I' R lm"MIOUCI.D oa COPIUI 0111 USO AS M MSts JOit IWM'M:TUllll Oii WI a, Al'PMATUS MTMIOVI' bPIIUSI.Y WMTTIJI ~ IZATIDN ,_ carrJllOl uac,. INC.• CIRCUIT DIAGRAM
O I I.NU,
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:IO!i:C. I 31 '~· .. I • c.
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VOLTAGE CONNECTIONS
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CB2?'2S RI-R'l RE'S 2,21< 1S% Y"w A.e,. Ct«:>StlXl031C c.2- ce CAP. ,OIUl'ilO~ IOOV C.Sl35F'IOSI< C:.I CAI'! IUI' 110% 'el"S>V ~5 --- TE'.:»'T &PEC. C.L 119-0'J.2- --- LA8£l,HANDL£. L530 CL ll3-<l96 --- KIT,HANDL£,IIICRO CAI\O. Cl
3000204 --- CARD~ PRINTED WII\INI;. LO I - 5 30 CL -...... ..-. ....... _..... .... __ ---::E:,:-:: --c1 CUIT OARD LDI-530 ."'!. ::. ~ =- DEVICE INTERRUPT/CONTROL
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1-----1-------'=' ,=,,.--t c 14931 3000 2 03 A _. - • ._.rrn1rr
--- . , - l
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WABCC "'v' ........ 'V"
LRC-531 a~ CDnTRDL LOGIC. lnC. ,--L ... RC..._-53 __ 1_-_l __ Rea __ l_-.;.;ti.;..;;m;.;.e...;C;.;l..;;.o,;.ck;.;;._ __________ --I NINE TECH CIRCLE
Drawing No. 9000144 I REV. A PAGE 1 OF 2 • NATICK, MASS.01760 •617/655-1170
The LRC-531 is a programmable, crystal-controlled interval timer. The clock rate can be changed under program control to rates of 1 Hz, 10 Hz, 100 Hz or 1,000 Hz. Expiration of an interval can be directly sensed by the program a the program can be interrupted. The LRC-531, which is used with M Series, derives its crystal-controlled clock oscillator input from the 2 MHz 01 or 02 clocks on the MIM-894. With L Series, the LRC-531-1 must be used. The LRC-531-1 includes its own on-board 10 MHz crystal oscillator.
The interval is programmed by a 4-bit control input to a latch on the card. FRQSEL transfers the control input into the latch and is normally a direct LDD-503 Device Address Decoder output. Normal wiring for the frequency control is for the followibg correspondence to A register bits: 1 Hz-Ao, 10 Hz-A1, 100 Hz-A2, 1,000 Hz-A3. A 11 111 in the indicated position selects the frequency shown. The program may sample the status of the LRC-531 by reading the two status bits, TIME OUT (normally wired to 010) and MISSED CLOCK (normally wired to 011). This status is placed on the Input Data Suss by the S'mEl signal, normally a direct LDD-503 input select signal. Reading of status by the i,rogram causes the status to be reset. MISSED CLOCK status indicates that more than one interval elapsed without a program status read taking place. A logic 11 111 status indicates that the condition is true.
The card includes complete logic for interfacing to the MPl-810 or LPl-510 Priority Interrupt cards. The logical equivalent of INT ST for M Series is INTA from the MIM-894. iRQ is a direct interrupt request to the Priority Interrupt card and ~ is the corresponding acknowledge from the Priority Interrupt card. When set up for interrupts, the MISSED CLOCK status will always be false.
SPECIFICATIONS
Loading and drive are in terms of TTL unit loads.
Input Loading
Freq. control bits, COUNT IN INT ST STSSEL FRQSEL, ~
Output Drive
Tm TIME OUT I MISSED CLOCK
Power Requirements
LRC-531 LRC-531-1
(Specifications subject to change without notice.)
1 2 3 4
10 20
290 mA @ +5V, typical 330 mA @ +5V, typical
(c) Copyright Control Logic, Inc., 1975
Appendix A 6054, p. A-lOA
°' :t,i Ott, Ultt, .s::,. (D .. :::,
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I-' 0 to
.,,.. ....._. ,... s,tantAtDIS Ml fNl Nm"UTY f1I CDN1aOI. UJCIC. ilC. ,,,., SltM1. ,.,.. • M:PIICIDUCU m aJND CIR U9ID AS M IMfS ,. IMMIFIICYUllll CIII IM.l G' ...... NI WffllDUf ...._, WllffDI MfflUt. wmatl Miiii cama. a.out. INC.. CIRCUIT DIAGRAM
VOLTAGE CONNECTIONS
8
=
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~sv~ ~lc,I~ I •15V I -:- I '1 I I 16 cu
-::- Y4
---- --DfT ~T
I. PIN CONNECYION 5'IMIIOL NOT[$:
( '
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-- - -- -
GMO~ I I ·r -1
I ~,,,
CONNECTIONS ~ - r PIN 14 __ , IOM"1! 111-T"''T I IA.I +_a:
I YI iL-@
~(Oll-:~--.Y) - @
3 3 IS I I 14 I I ·~ cl -1. 12
l I I ._!.
--------...----................... -·-·--~ ::. ~ LJ. , r
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im im till El li!il m
ra mmm m m a~ rm
rn m r~1 rn rn- rn- ;':.il :,1)"1-:, :,••..:.Jiii L-..1 ::, -iBiJ-
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3000206 A
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WABCCI
""'-" ...... ""'-" comADL LOGIC. me.
LL0-515 Latched Output Drawing
REV A 12-1-73 PAGE 1 OF 1
NINE TECH CIRCLE
• NATICK, MASS. 01780 • 617/855-1170
The latched Output Circuit Board, LL0-515, contains 24 latches agonized in six groups of four latches each. Each group of four latches is equipped with its own control line. Eight data I ines enter the card; four I ines driving the inputs of three groups of latches, the other four lines driving the inputs of the other three groups. The eight data lines are pin-assigned for bussing from the low-order 8 bits of the l Series Address/Data latch (A7-o).
The control lines are active low - so long as a control I ine is low, the outputs of the associated latch will follow its inputs. Thus, SEL lines from an LDD-503 may be used directly to control LL0-515 latch groups. latch outputs hold at the last input value when the control line goes high.
All inputs and controls are buffered so that no input represents more than one TTL load. The latches are non-inverting (D outputs are brought out from the latches to compensate for inversion caused by buffering).
There is one spare inverter on the LL0-515.
SPECIFICATIONS
Input loading
Output
Data inputs Control inputs
Data outputs Inverter
Power Requirements
220 ma at +5V (typical)
1 load (TTL) 1 load (TTL)
10 loads (TTL) IO loads (TTL)
(Specifications subject to change without notice.)
© Copyright Control Logic, Inc., 1973
Appendix A 6054, p. A-llA
°' :J;:f oi-c:, U1'1j .i::,. (1) ... !:j
p. '"O ..... . ~ ~:J;:f I-' I-' txJ
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~
?,
G.
GltOUP3 --rz. •
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~
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10
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@xi) ~ lei 1 ~+5" .j. C.I ,.~;u
<wv III
/ l
'
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Owg. No. 9000045 REV A -16-73 PAGE 1 OF 1 • NATICK, MASS. 01760 • 817~1170
The Buss Port Circuit Board, LBl-511, contains 24 single-input, tri ~tate gates organized in six groups of four gates. Inputs accept either TTL or DTL logic levels. There is a control input for each group of four circuits which determines the state of the outputs.
The outputs are standard low impedance TTL levels 111 11 and 11 011 or a high impedance state. A logic 11 111 at the control input places the output in the high impedance state. These circuits may be expanded by wiring additional circuits to the output buss lines. Up to 128 circuits may be connected to each common buss.
On the L Series Buss Pa"t, each set of four gates is equipped with its own control line. Of the six groups of four gates, three are pin-assigned for bussing onto the four most significant bits of the· Input Data Buss. The other three groups are pin-assigned for bussing onto the four least significant bits of the Input Data Buss. This makes it possible for the user to do much of his wiring using bussing strips. It also means a larger number of separate input devices can be accommodated by a single Buss Port Card. For example, the card can handle three separate 8-bit inputs, two 8-bit inputs and two 4-bit inputs and so on - up to six separately addressed 4-bit inputs.
SPECIFICATIONS
Input Loading
Output
Data inputs Control inputs
Data outputs
Power Requirements
1 load (TTL) 4 loads (TTL)
10 loads (TTL)
200 ma @+-5V typical
(Specifications subject to change without notice.)
Appendix A 6054, p. A-12A
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RELAY CARD CRB-457
Description
The CRB-457 relay card contains 10 Fo"" "A 11 (SPST) reed relays and may be used with Control Logic type logic modules such as the CNG-152T or similar units. The relay card couples low drive power and millisecond operation with relatively high power handling capability and open circuit isolation. IC drivers are protected from destructive turn-off by a diode resistor network on the card. The coil requires about 3 .8 V for operation which precludes using it between a logical output and ground. However, if used between the supply voltage (5 Vdc) and the logical output, the coil is readily energized by a logical 110 11 output (current sink).
Conversely, the coil is de-energized when the logical output is pulled up to the 5 V supply voltag~ or at the logical 11111 state.
See Figure 1 for cireuit connection.
Specifications
Piek-up Voltage Drop-Out Actuate Time Bounce Turn-off Spike Coil Resistance Coi I Loading Contact Ratings (maximum)
DC AC Load <..urrent Volts <..ontact Resistance Breakdown Vdc (minimum) Insulation Resistance
Life 3 W Load 10 x 106 Operations
Logic Diagram
3 .a V maximum 1 .0 V minimum 0 .2 ms typical 0.1 ms typical 250 JJS at 1 volt 500 n 7 TIL loads
10 W 10 VA 0.5 A 50V 0.2 n 250 1011 Q
10 W loac 0. 1 x 10 operations
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Appendix A 6054, p. A-16A
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