Carbon Nanotube Imperfection-Immune Digital VLSI · 3. Electrical breakdown (back-gate) 1. Grow and...

Carbon Nanotube Imperfection-Immune

Digital VLSI

H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong, J. Zhang

Subhasish Mitra

Robust Systems Group

Department of EE & Department of CS

Stanford University

Carbon Nanotube (CNT)Diameter (D) : 0.5 - 3 nm

D

S. Iijima

Carbon Nanotube FET (CNFET)

2

Ideal CNFET Inverter

N+ doped

Semiconducting

CNTs

Gates

Input

P+ doped

Semiconducting

CNTs Lithographic pitch

4nm

Sub-lithographic pitch

Output

Vdd

Gnd

3

CNFET Technology Milestones

4

1998

First CNFET

demonstration

[Delft, IBM]

1998

First CNFET

demonstration

[Delft, IBM]

2001

Single-CNT

logic gates

[IBM]

2001

Single-CNT

logic gates

[IBM]

2006

Single-CNT

ring osc.

[IBM]

2006

Single-CNT

ring osc.

[IBM]

2004

Best single-CNT

CNFET

[Stanford]

2004

Best single-CNT

CNFET

[Stanford]

CNFETs: BIG Promise, BUT

� Major barriers for a decade

� Mis-positioned nanotubes

� Metallic nanotubes

� Processing alone inadequate

Imperfection-immune

design essential

5

Wanted: (A+C) (B+D)

Got : B+D

Out

A B

C D

Vdd

A C

B D

Gnd

Wanted: A′C′ + B′D′

Got: A′C′ + B′D′ + A′D′

Mis-positioned CNTs �� Incorrect Logic

6

Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)

CNFET with s-CNT CNFET with m-CNT

Metallic CNTs

Typical: 10 – 50% grown CNTs metallic

Cu

rre

nt

Vg

Transistor

Vg

Cu

rre

nt

No gate

control

7

Results

� Yesterday

� SSI single-CNT ring oscillator

� Today

� Imperfection-immune VLSI circuits

8

CNFET Technology Milestones

9

1998

First CNFET

demonstration

[Delft, IBM]

2001

Single-CNT

logic gates

[IBM]

2001

Single-CNT

logic gates

[IBM]

2006

Single-CNT

ring osc.

[IBM]

2006

Single-CNT

ring osc.

[IBM]

2004

Best single-CNT

CNFET

[Stanford]

2004

Best single-CNT

CNFET

[Stanford]

2008

Mis-positioned-

CNT-immune

VLSI logic gates

[Stanford]

2008

Flexible

CNT

circuits

[UIUC]

2009

Imperfection-

immune adders

& latches

[Stanford]

2009

Defect-

tolerant

logic gates

[USC]

2009

Monolithic

3D CNT

circuits

[Stanford]

2010

Ultra-short

channel

CNFETs

[IBM]

CNFET Technology Outlook

Problem Challenge Status

CNT alignment

& positioningCorrect function

Metallic CNTCorrect function

Low leakage

CNT densityHigh current

density

CNT dopingComplementary

CNFETs

10

Outline

� Introduction

� Mis-positioned-CNT-immune logic

� Metallic-CNT-immune logic

� CNT variations

� Conclusion

11Patil, IEEE TCAD 2008, Symp. VLSI Tech. 2008

1. Grow CNTs

Mis-positioned-CNT-Immune NAND

12

BA

A

B

Out

1. Grow CNTs

2. Extended gate & contacts

CRUCIAL

13


Vdd

Gnd

BA

A

B

Out

1. Grow CNTs


3. Etch gate & CNTs

4. Chemically dope P & N regions

Vdd

Gnd

14


BA

A

B

Out

1. Grow CNTs


3. Etch gate & CNTs

4. Chemically dope P & N regions

Etched region

ESSENTIAL

� Graph algorithms

� All possible functions

Vdd

Gnd

15


Automated Algorithms

� Given: Layout

� Determine

• Mis-positioned-CNT immune ?

16


17

E

Doped

Doped

Gate B

Contact

Doped

Contact

Gate A

Doped

Etched

1

1A B

1

1

0

Contact

Contact

B

Contact

Contact

AGA GB

Intended:

A or B


18

E

Doped

Doped

Gate B

Contact

Doped

Contact

Gate A

Doped

Etched

C-D-A-D-C : A

1

1A B

1

1

0

Contact

Contact

B

Contact

Contact

AGA GB

Intended:

A or B


19

Gate B

Contact

Doped

Contact

Gate A

Doped

Etched

C-D-A-D-C : A

C-D-B-D-C : B

1

1A B

1

1

0

B

Contact

Contact

AE

Doped

Doped

Contact

Contact

GA GB

Intended:

A or B


20

E

Doped

Doped

Gate B

Contact

Doped

Contact

Gate A

Doped

Etched

C-D-A-D-C : A

C-D-B-D-C : B

C-D-B-D-A-D-B-D-C : A & B

1

1A B

1

1

0

Contact

Contact

B

Contact

Contact

AGA GB

Intended:

A or B


21

E

Doped

Doped

Gate B

Contact

Doped

Contact

Gate A

Doped

Etched

C-D-A-D-C : A

C-D-B-D-C : B


C-D-E-D-C : 0

…

1

1A B

1

1

0

Contact

Contact

B

Contact

Contact

AGA GB

Intended:

A or B


22

E

Doped

Doped

Gate B

Contact

Doped

Contact

Gate A

Doped

Etched

Intended:

A or B

Implemented:

A or B or

(A & B) or 0

==

A or B

C-D-A-D-C : A

C-D-B-D-C : B


C-D-E-D-C : 0

…

1

1A B

1

1

0

Contact

Contact

B

Contact

Contact

AGA GB

Automated Algorithms

� Given: Logic function

� Produce

• Mis-positioned-CNT immune layout

23

Mis-positioned-CNT-Immune Layout

24

Gates

Out = A + (B + C)(D + E)

Etched regionsCNTs

CB

Vdd / Gnd Contact

A

Output Contact

ED

Intermediate

Contact

� Immune to LARGE number of mis-positioned CNTs

� Efficient

Most Importantly

� VLSI processing

� No die-specific customization

� VLSI design flow

� Immune library cells

25

CNT Growth on Silicon Substrates

� Highly mis-positioned

� Not desirable for VLSI

26

10 µm 4 µm

27

SEM image (grown CNTs)

Quartz wafer with catalyst

Aligned CNT growth

99.5% CNTs aligned

Quartz wafer

First Wafer-Scale Aligned CNT Growth

28

� Silicon substrates for VLSI

� Low temperature (90oC – 120oC) processing

2 µm 2 µm

Before transfer After transfer

Target Substrate (SiO2/Si)Source Substrate (Quartz)

Thermal Release Adhesive Tape

Wafer-Scale CNT Transfer

29

First VLSI Demonstration

10µm10µm10µm

Mis-positioned-CNT-immune logic gates

NAND, NOR, AND-OR-INV, OR-AND-INV

NOR pullup

Etched Region

0

50

100

off

off

off

on

on

off

on

on

A

B

off = 2V, on = -2V

Current (µA)

0

0.75

1.5

off

off

off

on

on

off

on

on

A

B

off = 5V, on = -5V

Current (µA)

NAND pullup

Outline

� Introduction



� CNT variations

� Conclusion

30Patil, IEDM 2009, Shulaker, Nanoletters 2011, Wei, IEDM 2009, Symp. VLSI Tech. 2010

Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)

CNFET with s-CNT CNFET with m-CNT

Metallic CNTs

Typical: 10 – 50% grown CNTs metallic

Cu

rre

nt

Vg

Transistor

Vg

Cu

rre

nt

No gate

control

31

m-CNT Processing Options

� Grow 0% m-CNTs

� Open challenge

� Remove m-CNTs after growth

� 99.99% removal required

32

Existing m-CNT Removal

� Sort CNTs

� Inadequate

� SDB

� Single Device electrical Breakdown

� Not scalable

33

SDB Technique

� Current-induced m-CNT breakdown

� Single-device level

34

m-CNTs

s-CNTs

Collins, Science 2001

SDB Technique



35

m-CNTs

s-CNTs


Gate

off

SDB Technique



36

m-CNTs

s-CNTs


Gate

off

High Voltage

Gnd

SDB Technique



37

m-CNTs

s-CNTs


Gate

off

High Voltage

Gnd

m-CNT broken

SDB Technique



38

m-CNTs

s-CNTs


Gate

off

High Voltage

Gnd

m-CNT broken

Current density (µA / µm)

102

101

100

10-1

100 102 104 106

Ion / Ioff

Before SDB After

SDB

Major SDB Challenges

� Incorrect logic

� m-CNT fragments

� Impractical for giga-scale ICs

� Internal node access

39

Incorrect Logic with SDB

40

Output Contact

Gnd Contact

Intermediate Contact

A B

C D

off

off

off

off

Gnd

High

Broken

High

Pull-up Network

Vdd

Incorrect Logic !

Wanted:

(A + B) • (C + D)

Got:

(C + D)

VMR: m-CNT Immune Design

� New approach: VLSI Metallic CNT Removal

� Sufficient

• All logic designs

� VLSI processing & design flows

41

Final intended design

VDD

GND

VMR Example

42

m-CNTs (no gate control)

s-CNTs

Silicon Back-GateBack-Gate Oxide

1. Grow and transfer CNTs

VMR Steps

Back-Gate Oxide

43

2. Fabricate VMR electrodes


Silicon Back-Gate

Back-Gate Oxide

VMR ElectrodesVMR ElectrodesVMR ElectrodesVMR ElectrodesVMR Electrodes

Inter-digitated VMR electrodes

Electrical breakdown friendly

44

VMR Steps


3. Electrical breakdown (back-gate)


High voltage Gnd

Silicon Back-Gate

Back-Gate Oxide

VMR ElectrodesVMR ElectrodesVMR ElectrodesVMR ElectrodesVMR Electrodes

Inter-digitated VMR electrodes

Electrical breakdown friendly

45

VMR Steps



4. Etch CNTs : predefined regions

(mis-positioned-CNT-immune design)

5. Etch unneeded VMR electrodes


CNFET contacts

not removed

46

VMR Steps



4. Etch CNTs : predefined regions

(mis-positioned-CNT-immune design)

5. Etch unneeded VMR electrodes

6. Top-gates (mis-positioned-CNT-immune design), doping, wires


47

VMR Steps

Theorem

48

� VMR works for arbitrary logic design

if

� Any two transistors in series

� Connected through contact

• Minimum pitch

� Immune library cells: very small impact

First Experimental Demonstration

49

Half-adder Sum D-latch

Imperfection-immune CNT VLSI circuits

Arithmetic & storage elements

First Monolithic CNT 3D ICs

50

Conventional via, NOT TSV2-layer CNT XOR

Outline

� Introduction



� CNT variations

� Conclusion

51Zhang, IEEE TCAD 2009, DAC 2009, DAC 2010

CNT Variations Challenging

� Probabilistic modeling essential [Borkar 07]

52

CNFET Ion variations

OthersCNT diametervariations

CNT density variations

m-CNTs

Channel lengthvariations

Probabilistic CNT Growth Model

� Probability (m-CNT) = pm

� Probability (s-CNT) = ps = 1 - pm

53

2

2 13 0.22

3 3

=

s-CNT m-CNT

3

10.04

3

=

3

20.3

3

=

2

1 23 0.44

3 3

=

m-CNT Removal Alone Inadequate

54

m-CNTs removed

s-CNTs intact

m-CNT

Must be highly unlikely

No CNTs left !

prob. = (pm)3

= (33%)3

= 4%

Probabilistic Design a MUST

55

DesignProcessing

� % grown m-CNTs

� CNT density variations

� Special layouts

� CNFET sizing

Processing & Design Co-Optimization

LeakageNoise margin Delay variations

Special Layouts

56

Yield

low

high

low high

CNT

variation-

agnostic

design

Upsize CNFETs

New technique

� Aligned-active layouts

� Engineered CNT correlations

1

Cost

Outline

� Introduction



� CNT variations

� Conclusion

57

Thanks to our Sponsors

Photo credits:H. Dai, ibm.com, Nanoletters, Nature, Science, Stanford, Wikipedia

58

CNFET Technology Outlook

Problem Challenge Status

CNT alignment

& positioningCorrect function

Metallic CNTCorrect function

Low leakage

CNT densityHigh current

density

CNT dopingComplementary

CNFETs

59

Conclusion

� Imperfection-immune design essential

� New solutions: practical, elegantly simple

60

� Next challenge: CNT variations

� CNT correlation � unique layouts

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Carbon Nanotube Imperfection-Immune Digital VLSI · 3. Electrical breakdown (back-gate) 1. Grow and...

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