Card Management Solution Subsystem v3.0 Product Guide€¦ · Alveo Card Management Solution...

Alveo Card ManagementSolution Subsystem v3.0

Product GuideVivado Design Suite

PG348 (v3.0) November 24, 2020

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Table of ContentsChapter 1: Introduction.............................................................................................. 4

Features........................................................................................................................................4IP Facts..........................................................................................................................................5

Chapter 2: Overview......................................................................................................6Navigating Content by Design Process.................................................................................. 15Applications................................................................................................................................15Licensing and Ordering............................................................................................................ 16

Chapter 3: Product Specification......................................................................... 17Performance.............................................................................................................................. 17Resource Utilization.................................................................................................................. 17Port Descriptions.......................................................................................................................18Register Space........................................................................................................................... 19

Chapter 4: Designing with the Subsystem..................................................... 30Clocking...................................................................................................................................... 30Resets..........................................................................................................................................30Addressing................................................................................................................................. 30Interrupts................................................................................................................................... 31

Chapter 5: Design Flow Steps.................................................................................32Customizing and Generating the Subsystem........................................................................ 32Constraining the Subsystem....................................................................................................33Simulation.................................................................................................................................. 35Synthesis and Implementation................................................................................................35

Chapter 6: Example Design..................................................................................... 36Overview.....................................................................................................................................36Implementing the Example Design........................................................................................ 37Example Design Files................................................................................................................ 38

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Appendix A: Upgrading............................................................................................. 39Changes from v2.0 to v3.0........................................................................................................39Changes from v1.0 to v2.0........................................................................................................39

Appendix B: Debugging.............................................................................................41Finding Help on Xilinx.com...................................................................................................... 41Debug Tools............................................................................................................................... 42Hardware Debug....................................................................................................................... 43

Appendix C: Additional Resources and Legal Notices............................. 44Xilinx Resources.........................................................................................................................44Documentation Navigator and Design Hubs.........................................................................44References..................................................................................................................................44Revision History......................................................................................................................... 45Please Read: Important Legal Notices................................................................................... 46




Chapter 1

IntroductionThe Alveo™ Card Management Solution Subsystem (CMS Subsystem) is a MicroBlaze™-baseddesign compatible with U200, U250, U280, U50, and next-generation Alveo acceleration cards.

CMS firmware autonomously reads sensor information from the TI MSP432 satellite controllerover UART and writes instantaneous, maximum, and average values to a shared memory forcollection by the host software. Sensor information is monitored and gathered for:

• Voltages

• Currents

• Temperatures

• Fan Speed

• Power

The CMS solution also provides a message based mailbox interface to enable other cardmanagement functions including:

• Satellite controller firmware updates

• Card information reporting

• QSFP status and control

Features• Sensor Monitoring: Reports key voltage rails, current values, temperatures, power values, and

fan speed from the satellite controller.

• Card Information: Reports card information from the satellite controller, including MACaddresses.

• Satellite Controller Firmware Update: Provides satellite controller firmware update interface.

• QSFP Diagnostics and Control: Reports QSFP diagnostics and provides the QSFP controlinterface via the satellite controller.

• QSFP Low Speed I/O Status: Reports QSFP low speed I/O status via the satellite controller.

Chapter 1: Introduction




IP FactsLogiCORE™ IP Facts Table

Subsystem Specifics

Supported Device Family1 UltraScale+™

Note: This solution is targeted to U200, U250, U280, U50, and next-generationAlveo cards.

Supported User Interfaces AXI4-Lite

Resources Performance and Resource Use web page

Provided with Subsystem

Design Files IP integrator HIP Subsystem

Example Design VHDL/Verilog

Test Bench N/A

Constraints File Xilinx Design Constraints (XDC)

Simulation Model N/A

Supported S/W Driver N/A

Tested Design Flows2

Design Entry Vivado® Design Suite

Simulation N/A.

Synthesis N/A

Support

All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:1. For a complete list of supported devices, see the Vivado® IP catalog.2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.

Chapter 1: Introduction


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Chapter 2

OverviewThe CMS solution is the MicroBlaze™ microprocessor and firmware solution. Softwareconfiguration of the CMS subsystem is not required (the CMS is fixed function).

The CMS IP latest compatibility satellite controller firmware loads are listed in Table 1.

Table 1: Satellite Controller Firmware Compatibility

CMS Firmware Version Alveo Card Satellite Controller Firmware Version1.8.10 U200 4.6.6

U250 4.6.6

U280 (1) 4.3.10

U50 5.1.7

Next-generation 7.1.9

Notes:1. Limited features are supported for the Alveo U280 card.

RECOMMENDED: The CMS IP is also backward compatible, with the default satellite controller firmwareshipped with the Alveo cards, and may not support the latest functions and capabilities. Upgrade the Alveocard satellite controller firmware to the version listed in Table 1. For more information on upgrading to thelatest firmware refer to Getting Started with Alveo Data Center Accelerator Cards (UG1301).

Sensor Monitoring

• CMS firmware polls for sensor information from the satellite controller (TI MSP432)approximately every 120 ms.

• Communication with the satellite controller is via a UART interface and GPIO handshake lines.

• CMS firmware processes sensor information and writes instantaneous, maximum, and averagevalues to a shared memory (memory mapped) for collection by the host software.

• Sensor information is gathered and monitored for:

○ Voltage

○ Current

○ Temperature

○ Power

Chapter 2: Overview


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○ Fan Speed

• Host software must poll the shared memory (REG_MAP) for updated sensor information.

Note: Fan speed is reported only for active cards with local fans. Passive cards do not contain fans.

Note: HBM Temperature reporting must be enabled on compatible Alveo cards via the REG_MAP controlregister (CONTROL_REG).

Figure 1: Card Management Solution Subsystem Block Diagram

ManagementMicroBlaze

MicroBlazeLMB Memory

MicroBlazeReset AXI GPIO

(MB_RESETN_REG)

Register MapAXI BRAM

(REG_MAP)

AXI UART

AXI GPIO

WatchDogTimer

Interrupt Controller

Host <-> MicroBlaze Communication

AXILITE

Host Interrupt Controller

(HOST_INTC)

*HBMTemp

x 2

HBM*CATTRIP Interrupt

LMB

RESET

INT

Card Management Solution (CMS) Subsystem

AXI LITEHost Interface

*U50/U280 and next-generation Alveo cards only

UART

Host Interrupt

Satellite Controller InterfaceGPIO

X2/4

X23179-102620

Mailbox Interface

A section of the register map is reserved for a dedicated host to CMS mailbox interface. Themailbox start location is defined by register HOST_MSG_OFFSET_REG.

The Mailbox may be used to request:

• Satellite controller firmware update

• Card information reporting

• QSFP diagnostics and control

Chapter 2: Overview




• QSFP low speed I/O status and control

Using the Mailbox

The Mailbox message flow is as follows:

1. The host checks availability of the message buffer by confirming CONTROL_REG[5] is 0.

2. The host writes a message to MAILBOX offset in the REG_MAP.

3. The host sets CONTROL_REG[5] to 1 to indicate a new message is available.

4. CMS firmware polls CONTROL_REG[5] to determine new message available.

5. CMS firmware reads the message payload defined by the length field in the message header.

6. CMS firmware reports processing errors to HOST_MSG_ERROR_REG.

7. CMS firmware performs the requested action defined by the opcode in the message header.

Message Headers

Each message written to the mailbox has a 32-bit Header. The format of the header is defined in Table 2.

Note: The message payload is transmitted in network byte order, but headers are transmitted in littleendian mode.

Table 2: Message Header Format

Message Header [11:0] Message Header [23:12] Message Header [31:24]Message Length (bytes) Reserved Opcode

Satellite Controller Firmware Update

The satellite controller firmware can be updated using the Mailbox Interface. The messagesrequired to perform this function are defined in Table 3.

Table 3: Message Header Opcodes

Opcode Name Description0x5 CMS_OP_MSP432_FW_ERASE Performs mass erase on the MSP432 EEPROM to remove old

firmware. (1)

0x1 CMS_OP_MSP432_FW_SEC Begins the MSP432 firmware update. This message willprovide the MSP432 EEPROM firmware start location andthe length of the firmware image to be transferred. Themessage will also contain the firmware image. If the imageis too big for a single message, additional firmware data canbe sent using CMS_OP_MSP432_FW_DATA messages. (2)

0x2 CMS_OP_MSP432_FW_DATA Continues the MSP432 firmware update. This message willsend additional sections of the MSP432 FW image. (3)

Chapter 2: Overview




Table 3: Message Header Opcodes (cont'd)

Opcode Name Description0x3 CMS_OP_MSP432_JUMP Forces the MSP432 to jump to new EEPROM location. (4) (5)

Notes:1. This will enable BSL mode of MSP432.2. Assumes MSP432 BSL mode is enabled3. Assumes MSP432 BSL mode is enabled.4. Assumes MSP432 BSL mode is enabled.5. The MSP432 will exit BSL mode after the jump is complete.

Message Format

Table 4: CMS_OP_MSP432_FW_SEC (0x1)

32-bit Word Field Type Field Description[0] Host request Message header

[1] Host request Starting address of the BSL firmware section.

[2] Host request Length of BSL firmware section in bytes.

[3:n] Host request Firmware data (1)

Notes:1. If the firmware data is too large to fit in this message, use CMS_OP_MSP432_FW_DATA messages to send the

remaining data.

Table 5: CMS_OP_MSP432_FW_DATA (0x02)


[1:n] Host request Firmware data (1)

Notes:1. Multiple messages may be required to send all firmware data.

Table 6: CMS_OP_MSP432_JUMP (0x03)


[1:n] Host Request BSL Jump address

Table 7: CMS_OP_MSP432_FW_ERASE (0x05)


Notes:1. There is no payload for this command. The CMS will instruct the MSP432 to enter BSL mode (if required) and erase

the flash to prepare for the firmware update.

Chapter 2: Overview




Card Information Reporting

Card information can be requested from the satellite controller using the mailbox interface. Cardinformation includes:

• Card name

• Card revision

• Card serial number

• Satellite controller version

• Configuration mode

• Total power available

• MAC addresses

Note: The Mailbox supports two MAC addressing schemes:

• Legacy mode which reports up to 4 MAC addresses.

• Dynamic mode, a scalable solution to support reporting on Alveo cards with more than 4 MACaddresses.

Note: The first 8 MAC addresses are also reported via the REG_MAP.

The messages required to perform this function are defined in Table 8.


Opcode Name Description0x4 CMS_OP_BOARD_INFO_REQ Host request for the card information from MSP432.

CMS will respond by populating the message buffer withcard information and updating the message header lengthfield.

Message Format

Table 9: CMS_OP_BOARD_INFO_REQ (0x04)

32-bit Word Field Type Field Description[0] Host request/CMS response Message header

[1:n] CMS response Card information response by CMS. This is packed as anarray of uint8s. Each card information field will be definedas <Key><Length><Payload>. See Table 10 for the list ofsupported keys and corresponding length/payloadinformation generated by CMS.

Chapter 2: Overview




Table 10: Card Information Sensor ID

Sensor ID Name Key Length Payload

SNSR_ID_BOARD_SN 0x21 Variable (n) n-1 characters ASCII Text + termination string 0x00

SNSR_ID_MAC_ADDRESS0 0x22 0x12 17 characters ASCII Text + termination string 0x00




SNSR_ID_BOARD_REV 0x26 Variable (n) n-1 characters ASCII Text + termination string 0x00

SNSR_ID_BOARD_NAME 0x27 Variable (n) n-1 characters ASCII Text + termination string 0x00

SNSR_ID_SAT_VERSION 0x28 Variable (n) n-1 characters ASCII Text + termination string 0x00

SNSR_ID_TOTAL_POWER_AVAIL 0x29 0x1 0x00 = 75W0x01 = 150W0x02 = 225W0x04 = 300W

SNSR_ID_FAN_PRESENCE 0x2A 0x1 ASCII Text

SNSR_ID_CONFIG_MODE 0x2B 0x1 0: Slave_Serial_x11: Slave_Select_Map_x82: Slave_Map_x163: Slave_Select_Map_x324: JTag_Boundary_Scan_x15: Master_SPI_x16: Master_SPI_x27: Master_SPI_x48: Master_SPI_x89: Master_BPI_x810: Master_BPI_x1611: Master_Serial_x112: Master_Select_Map_x813: Master_Select_Map_x16

SNSR_ID_NEW_MAC_SCHEME 0x4B 0x8 Bytes 1-2: Number of contiguous MAC addresses.Bytes 3-8: Hex value of the first MAC address.

Chapter 2: Overview




Figure 2: Card Information Message Response Example

Key=0x27 Length=0x0d

0x000x81 0x00Message Header

(little endian)

Message Payload(network byte order)

0x04

Key=0x26

Length=0x02 Key=0x21

Length=0x0d

Key=0x22 Length=0x12




Key=0x2a Length=0x01

Key=0x2b Length=0x01

Key=0x29 Length=0x01 Key=0x28

Length=0x04

0x00

0x41 0x4c

0x56

0x55

0x50

0x45

0x35

0x51

0x4f 0x20

0x30 0x20

0x00

0x31 0x00

0x35 0x30 0x31

0x32

0x39

0x31

0x43

0x31 0x31

0x53 0x50

0x4d 0x00

0x35

0x00

0x2e 0x30

0x070x50

0x33 0x00

0x32 0x00

0x31 0x00

0x37 0x30 0x3a 0x30

0x3a 0x30 0x36 0x3a

0x41 0x3a 0x33 0x35

0x30 0x30 0x3a 0x30

0x30 0x00

270d414c56454f2055353020505100

SNSR_ID_BOARD_NAME = ALVEO U50 PQ

26023100

SNSR_ID_BOARD_REV = 1210d35303132313131394353504d00

SNSR_ID_BOARD_SN = 50121119CSPM

221230303a30413a33353a30363a37303a303000

SNSR_ID_MAC_ADDRESS0 = 00:0A:35:06:70:00

231230303a30413a33353a30363a37303a303100


241230303a30413a33353a30363a37303a303200


251230303a30413a33353a30363a37303a303300


2a01 50

SNSR_ID_FAN_PRESENCE = P2b0107

SNSR_ID_CONFIG_MODE = Master_SPI_x4

290100

SNSR_ID_TOTAL_POWER_AVAIL = 75W2804352e3000

SNSR_ID_SAT_VERSION = 5.0

0x37 0x30 0x3a 0x30

0x3a 0x30 0x36 0x3a

0x41 0x3a 0x33 0x35

0x30 0x30 0x3a 0x30

0x37 0x30 0x3a 0x30

0x3a 0x30 0x36 0x3a

0x41 0x3a 0x33 0x35

0x30 0x30 0x3a 0x30

0x37 0x30 0x3a 0x30

0x3a 0x30 0x36 0x3a

0x41 0x3a 0x33 0x35

0x30 0x30 0x3a 0x30

Sensor ID Key

Length

Payload

Payload Termination

Length Opcode

X24819-111220

Chapter 2: Overview




Figure 3: Dynamic MAC Address Response Example

0x70 0x00

Message Header

(little endian)

Message Payload

(network byte order)

Opcode 4B080800000A35067000SNSR_ID_MAC_ADDRESS0 = 00:0A:35:06:70:00SNSR_ID_MAC_ADDRESS1 = 00:0A:35:06:70:01SNSR_ID_MAC_ADDRESS2 = 00:0A:35:06:70:02SNSR_ID_MAC_ADDRESS3 = 00:0A:35:06:70:03SNSR_ID_MAC_ADDRESS4= 00:0A:35:06:70:04SNSR_ID_MAC_ADDRESS5 = 00:0A:35:06:70:05SNSR_ID_MAC_ADDRESS6 = 00:0A:35:06:70:06SNSR_ID_MAC_ADDRESS7 = 00:0A:35:06:70:07

Length

Key=0x4B

Length=0x08

0x000x81 0x00 0x04

0x08 0x00

0x00 0x0A 0x35 0x06

X24820-111220

QSFP Management

The mailbox interface supports the following QSFP management features:

• QSFP diagnostics and control

• Low speed I/O status

Note: QSFP diagnostic read access is only supported on Alveo U50 and next-generation cards.

Note: QSFP control write access is limited to bytes 86-98 on page 0x00 on Alveo U50 and next-generation cards.

Note: Low Speed I/O status is only supported on Alveo U50 and next-generation cards and is limited toRESTL and LPMOD.

The messages required to perform these functions are defined in Table 11.


Opcode Name Description0xB CMS_OP_READ_QSFP_DIAGNOSTICS Host requests QSFP diagnostic information.0xC CMS_OP_WRITE_QSFP_CONTROL Host request to write to QSFP control bytes. Limited to 13

control bytes on page 0x00.

0xD CMS_OP_READ_QSFP_LOW_SPEED_IO Host requests to read to single QSFP low speed I/O byte.0xE CMS_OP_WRITE_QSFP_LOW_SPEED_IO Host requests to write to single QSFP low speed I/O byte.

Chapter 2: Overview




Message Format

Table 12: CMS_OP_READ_QSFP_DIAGNOSTICS (0x0B)

32-bit Word Field Type Field Description[0] Host Request/CMS Response Message header

[1] Host Request QSFP 0/1

[2] CMS Response Size in bytes

[3:n] CMS Response Diagnostic Data

Table 13: CMS_OP_WRITE_QSFP_CONTROL (0x0C)

32-bit Word Field Type Field Description[0] Host Request Message header


[2] Host Request Size in bytes (13)

[3:n] Host Request Control Data

Table 14: CMS_OP_READ_QSFP_LOW_SPEED_IO (0x0D)



[2] CMS Response Low Speed I/O Data (1 byte)7-2: Reserved1: LPMOD0: RESTL

Table 15: CMS_OP_WRITE_QSFP_LOW_SPEED_IO (0x0E)



[2] Host Request Low Speed I/O Data (1 byte)7-2: Reserved1: LPMOD0: RESTL

Chapter 2: Overview




Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. This document covers the following designprocesses:

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado®

timing, resource use, and power closure. Also involves developing the hardware platform forsystem integration. Topics in this document that apply to this design process include:

• Port Descriptions

• Register Space

• Clocking

• Resets

• Chapter 6: Example Design

ApplicationsThe CMS Subsystem is designed for in-band card management systems for plug-in PCIe® cardsfor servers typically deployed in data centers.

A typical configuration deployment configuration is shown in Figure 4.

Chapter 2: Overview




Figure 4: CMS Subsystem Typical Configuration

ManagementMicroBlaze

MicroBlazeLMB Memory

MicroBlazeReset AXI

GPIO(MB_RESETN

_REG)

CPURegister

MapAXI BRAM

(REG_MAP)

AXI UART

AXIGPIO

WatchDogTimer

Interrupt Controller

TI MSP432Satellite

Controller

Host <-> MicroBlaze Communication

MicroBlaze <-> Satellite Controller Communication

AXILITE

BMC

Host Interrupt

Controller (HOST_INTC)

PCIeSubsystem

PCIe

SM Bus

*HBMIP

*HBM Temp1, HBM Temp2

*HBM CATTRIP Interrupt

Sensors

Shell

Server

LMB

RESET

INT

Host Interrupt

*U50/U280 and next-generation Alveo cards only

Card Management Solution (CMS) SubsystemAlveo

UART

GPIO

X22660-102620

Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®

Design Suite under the terms of the Xilinx End User License.

Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.

Chapter 2: Overview


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Chapter 3

Product Specification

PerformanceFor full details about performance and resource use, visit the Performance and Resource Use webpage.

Resource UtilizationFor full details about performance and resource use, visit the Performance and Resource Use webpage.

Chapter 3: Product Specification








Port DescriptionsThe CMS Subsystem ports are shown in the following figure.

Figure 5: CMS Subsystem IP Symbol

I/O Signal DescriptionTable 16: CMS Subsystem I/O Descriptions

Port Name I/O Clock Descriptions_axi_ctrl I/O aclk_ctrl AXI4-Lite Control Slave interface

aclk_ctrl I N/A AXI4-Lite Control Clock Pin (50 MHz)

aresetn_ctrl I aclk_ctrl AXI4-Lite Control Reset Pin. Active-Low reset.

interrupt_hbm_cattrip I async HBM CATTRIP Interrupt 1, 2

hbm_temp_1 I async HBM temperature bus from HBM device 11

hbm_temp_2 I async HBM temperature bus from HBM device 2 1

satellite_gpio I async GPIO signals from MSP432 Satellite Controller

satellite_uart I/O async UART interface to MSP432 Satellite Controller

interrupt_host O aclk_ctrl Host Interrupt generated by the CMS Subsystem inthe event of a Watchdog timeout.

Notes:1. This port will only be visible on Alveo cards supporting HBM.2. HBM IP CATTRIP outputs should be ORed together to form a single interrupt bit into CMS Subsystem.





Register SpaceTable 17: CMS Subsystem Register Address Space

Address (hex) Name Access Type Description0x000000-0x1FFFF Reserved N/A Reserved

0x020000 MB_RESETN_REG RWMicroBlaze reset register.Active low.Default 0x0 (reset active)

0x021000-0x021FFF Reserved N/A Reserved

0x022000-0x022FFF HOST_INTCSee AXI Interrupt Controller(INTC) LogiCORE IP Product

Guide (PG099)

Host Interrupt Controller31:1 - Reserved0 - Watchdog Timeout

0x021000-0x021FFF Reserved N/A Reserved

0x028000-0x029FFF REG_MAP See REG_MAP RegisterDefinitions

Host/CMS shared memorymap

The sensors listed in Table 18 are a super-set of all Alveo™ card sensors. Refer to the relevantAlveo card documentation to determine which sensors are valid for U200, U250, U50, and next-generation cards.

Table 18: REG_MAP Register Definitions (0x028000)

Address (hex) Name Access Type Description0x0000 REG_MAP_ID_REG RO Register Map ID. (0x74736574)0x0004 FW_VERSION_REG RO Firmware Version (0x0C01080A)

0x0008 STATUS_REG ROCMS Status Register:31:28 - MSP432 Mode (Normal = 1)27:0 - Reserved

0x000C ERROR_REG RO

CMS Error Register:31:28 - Reserved27 - MSP432 Communication Error (1=Error, useCONTROL_REG to clear)26:0 - Reserved

0x0010 Reserved N/A N/A0x0014 PROFILE_NAME_REG RO Software profile (0x434D5341)



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Table 18: REG_MAP Register Definitions (0x028000) (cont'd)

Address (hex) Name Access Type Description

0x0018 CONTROL_REG RW

CMS Control Register:31:29 - Reserved28 - VCCINT Current Scaling. 1=enable,0=disable.

Note: This feature scales the VCCINT currentvalues received from the satellite controllerbased on the power cable attached and shouldbe enabled on Alveo U200 and U250 cards.

27 - HBM Temperature Monitoring. 1=enable,0=disable.

Note: This feature enables monitoring of HBMtemperature sensors and should be enabled onAlveo U50 and next generation cards.

26:7 - Reserved6 - Set to reboot MicroBlaze.5 - Mailbox Message Status. Set to 1 by host toindicate new message present in Mailbox.Cleared to 0 by CMS when message has beenprocessed4:2 - Reserved1 - Set to Reset ERROR_REG. Self clears whenfinished.0 - Set to reset MAX and AVG sensor values, selfclearing.

0x001C Reserved N/A N/A

0x0020 12V_PEX_MAX_REG RO12V_PEX Max VoltageUnsigned 32b int (mV)

0x0024 12V_PEX_AVG_REG RO12V_PEX Average VoltageUnsigned 32b int (mV)

0x0028 12V_PEX_INS_REG RO12V_PEX Instantaneous VoltageUnsigned 32b int (mV)

0x002C 3V3_PEX_MAX_REG RO3V3_PEX Max VoltageUnsigned 32b int (mV)

0x0030 3V3_PEX_AVG_REG RO3V3_PEX Average VoltageUnsigned 32b int (mV)

0x0034 3V3_PEX_INS_REG RO3V3_PEX Instantaneous VoltageUnsigned 32b int (mV)

0x0038 3V3_AUX_MAX_REG RO3V3_AUX Max VoltageUnsigned 32b int (mV)

0x003C 3V3_AUX_AVG_REG RO3V3_AUX Average VoltageUnsigned 32b int (mV)

0x0040 3V3_AUX_INS_REG RO3V3_AUX Instantaneous VoltageUnsigned 32b int (mV)

0x0044 12V_AUX_MAX_REG RO12V_AUX Max VoltageUnsigned 32b int (mV)







0x0048 12V_AUX_AVG_REG RO12V_AUX Average VoltageUnsigned 32b int (mV)

0x004C 12V_AUX_INS_REG RO12V_AUX Instantaneous VoltageUnsigned 32b int (mV)

0x0050 DDR4_VPP_BTM_MAX_REG RODDR4 VPP BTM Max VoltageUnsigned 32b int (mV)

0x0054 DDR4_VPP_BTM_AVG_REG RODDR4 VPP BTM Average VoltageUnsigned 32b int (mV)

0x0058 DDR4_VPP_BTM_INS_REG RODDR4 VPP BTM Instantaneous VoltageUnsigned 32b int (mV)

0x005C SYS_5V5_MAX_REG ROSYS_5V5 Max VoltageUnsigned 32b int (mV)

0x0060 SYS_5V5_AVG_REG ROSYS_5V5 Average VoltageUnsigned 32b int (mV)

0x0064 SYS_5V5_INS_REG ROSYS_5V5 Instantaneous VoltageUnsigned 32b int (mV)

0x0068 VCC1V2_TOP_MAX_REG ROVCC1V2_TOP Max VoltageUnsigned 32b int (mV)

0x006C VCC1V2_TOP_AVG_REG ROVCC1V2_TOP Average VoltageUnsigned 32b int (mV)

0x0070 VCC1V2_TOP_INS_REG ROVCC1V2_TOP Instantaneous VoltageUnsigned 32b int (mV)

0x0074 VCC1V8_MAX_REG ROVCC1V8 Max VoltageUnsigned 32b int (mV)

0x0078 VCC1V8_AVG_REG ROVCC1V8 Average VoltageUnsigned 32b int (mV)

0x007C VCC1V8_INS_REG ROVCC1V8 Instantaneous VoltageUnsigned 32b int (mV)

0x0080 VCC0V85_MAX_REG ROVCC0V85 Max VoltageUnsigned 32b int (mV)

0x0084 VCC0V85_AVG_REG ROVCC0V85 Average VoltageUnsigned 32b int (mV)

0x0088 VCC0V85_INS_REG ROVCC0V85 Instantaneous VoltageUnsigned 32b int (mV)

0x008C DDR4_VPP_TOP_MAX_REG RODDR4_VPP_TOP Max VoltageUnsigned 32b int (mV)

0x0090 DDR4_VPP_TOP_AVG_REG RODDR4_VPP_TOP Average VoltageUnsigned 32b int (mV)

0x0094 DDR4_VPP_TOP_INS_REG RODDR4_VPP_TOP Instantaneous VoltageUnsigned 32b int (mV)

0x0098 MGT0V9AVCC_MAX_REG ROMGT0V9AVCC Max VoltageUnsigned 32b int (mV)







0x009C MGT0V9AVCC_AVG_REG ROMGT0V9AVCC Average VoltageUnsigned 32b int (mV)

0x00A0 MGT0V9AVCC_INS_REG ROMGT0V9AVCC Instantaneous VoltageUnsigned 32b int (mV)

0x00A4 12V_SW_MAX_REG RO12V_SW Max VoltageUnsigned 32b int (mV)

0x00A8 12V_SW_AVG_REG RO12V_SW Average VoltageUnsigned 32b int (mV)

0x00AC 12V_SW_INS_REG RO12V_SW Instantaneous VoltageUnsigned 32b int (mV)

0x00B0 MGTAVTT_MAX_REG ROMGTAVTT Max VoltageUnsigned 32b int (mV)

0x00B4 MGTAVTT_AVG_REG ROMGTAVTT Average VoltageUnsigned 32b int (mV)e

0x00B8 MGTAVTT_INS_REG ROMGTAVTT Instantaneous VoltageUnsigned 32b int (mV)

0x00BC VCC1V2_BTM_MAX_REG ROVCC1V2_BTM Max VoltageUnsigned 32b int (mV)

0x00C0 VCC1V2_BTM_AVG_REG ROVCC1V2_BTM Average Voltage.Unsigned 32b int (mV)

0x00C4 VCC1V2_BTM_INS_REG ROVCC1V2_BTM Instantaneous Voltage.Unsigned 32b int (mV)

0x00C8 12VPEX_I_IN_MAX_REG RO12VPEX_I_IN Max Current.Unsigned 32b int (mA)

0x00CC 12VPEX_I_IN_AVG_REG RO12VPEX_I_IN Average Current.Unsigned 32b int (mA)

0x00D0 12VPEX_I_IN_INS_REG RO12VPEX_I_IN Instantaneous Current.Unsigned 32b int (mA)

0x00D4 12V_AUX_I_IN_MAX_REG RO12V_AUX_I_IN Max Current.Unsigned 32b int (mA)

0x00D8 12V_AUX_I_IN_AVG_REG RO12V_AUX_I_IN Average Current.Unsigned 32b int (mA)

0x00DC 12V_AUX_I_IN_INS_REG RO12V_AUX_I_IN Instantaneous Current.Unsigned 32b int (mA)

0x00E0 VCCINT_MAX_REG ROVCCINT Max Voltage.Unsigned 32b int (mV)

0x00E4 VCCINT_AVG_REG ROVCCINT Average Voltage.Unsigned 32b int (mV)

0x00E8 VCCINT_INS_REG ROVCCINT Instantaneous Voltage.Unsigned 32b int (mV)

0x00EC VCCINT_I_MAX_REG ROVCCINT_I Max Current.Unsigned 32b int (mA)







0x00F0 VCCINT_I_AVG_REG ROVCCINT_I Average Current.Unsigned 32b int (mA)

0x00F4 VCCINT_I_INS_REG ROVCCINT_I Instantaneous Current.Unsigned 32b int (mA)

0x00F8 FPGA_TEMP_MAX_REG ROFPGA_TEMP Max Temperature.Unsigned 32b int (C)

0x00FC FPGA_TEMP_AVG_REG ROFPGA_TEMP Average Temperature.Unsigned 32b int (C)

0x0100 FPGA_TEMP_INS_REG ROFPGA_TEMP Instantaneous Temperature.Unsigned 32b int (C).

0x0104 FAN_TEMP_MAX_REG ROFAN_TEMP Max Temperature.Unsigned 32b int (C)

0x0108 FAN_TEMP_AVG_REG ROFAN_TEMP Average Temperature.Unsigned 32b int (C)

0x010C FAN_TEMP_INS_REG ROFAN_TEMP Instantaneous Temperature.Unsigned 32b int (C).

0x0110 DIMM_TEMP0_MAX_REG RODIMM_TEMP0 Max Temperature.Unsigned 32b int (C)

0x0114 DIMM_TEMP0_AVG_REG RODIMM_TEMP0 Average Temperature.Unsigned 32b int (C)

0x0118 DIMM_TEMP0_INS_REG RODIMM_TEMP0 Instantaneous Temperature.Unsigned 32b int (C).

0x011C DIMM_TEMP1_MAX_REG RODIMM_TEMP1 Max Temperature.Unsigned 32b int (C)




0x012C DIMM_TEMP2_AVG_REG RODIMM_TEMP2 Average Temperature.Unsigned 32b int (C)




0x013C DIMM_TEMP3_INS_REG RODIMM_TEMP3 Instantaneous Temperature.Unsigned 32b int (C).







0x0140 SE98_TEMP0_MAX_REG ROSE98_TEMP0 Max Temperature.Unsigned 32b int (C)

0x0144 SE98_TEMP0_AVG_REG ROSE98_TEMP0 Average temperature.Unsigned 32b int (C)

0x0148 SE98_TEMP0_INS_REG ROSE98_TEMP0 Instantaneous temperature.Unsigned 32b int (C).

0x014C SE98_TEMP1_MAX_REG ROSE98_TEMP1 Max Temperature.Unsigned 32b int (C)

0x0150 SE98_TEMP1_AVG_REG ROSE98_TEMP1 Average Temperature.Unsigned 32b int (C)

0x0154 SE98_TEMP1_INS_REG ROSE98_TEMP1 Instantaneous Temperature.Unsigned 32b int (C).

0x0158 SE98_TEMP2_MAX_REG ROSE98_TEMP2 Max Temperature.Unsigned 32b int (C)

0x015C SE98_TEMP2_AVG_REG ROSE98_TEMP2 Average Temperature.Unsigned 32b int (C)

0x0160 SE98_TEMP2_INS_REG ROSE98_TEMP2 Instantaneous Temperature.Unsigned 32b int (C).

0x0164 FAN_SPEED_MAX_REG ROFAN_SPEED Max Speed.Unsigned 32b int (RPM)

0x0168 FAN_SPEED_AVG_REG ROFAN_SPEED Average Speed.Unsigned 32b int (RPM)

0x016C FAN_SPEED_INS_REG ROFAN_SPEED Instantaneous Speed.Unsigned 32b int (RPM).

0x0170 CAGE_TEMP0_MAX_REG ROCAGE_TEMP0 Max Temperature.Unsigned 32b int (C)

0x0174 CAGE_TEMP0_AVG_REG ROCAGE_TEMP0 Average Temperature.Unsigned 32b int (C)

0x0178 CAGE_TEMP0_INS_REG ROCAGE_TEMP0 Instantaneous Temperature.Unsigned 32b int (C).

0x017C CAGE_TEMP1_MAX_REG ROCAGE_TEMP1 Max Temperature.Unsigned 32b int (C)




0x018C CAGE_TEMP2_AVG_REG ROCAGE_TEMP2 Average Temperature.Unsigned 32b int (C)










0x019C CAGE_TEMP3_INS_REG ROCAGE_TEMP3 Instantaneous Temperature.Unsigned 32b int (C).

0x01A0-0x01A4 MAC_ADDRESS_0 RO 48-bit MAC Address.

0x01A8-0x01AC MAC_ADDRESS_1 RO 48-bit MAC Address.

0x01B0-0x01B4 MAC_ADDRESS_2 RO 48-bit MAC Address.

0x01B8-0x01BC MAC_ADDRESS_3 RO 48-bit MAC Address.

0x01C0-0x01C4 MAC_ADDRESS_4 RO 48-bit MAC Address.

0x01C8-0x01CC MAC_ADDRESS_5 RO 48-bit MAC Address.

0x01D0-0x01D4 MAC_ADDRESS_6 RO 48-bit MAC Address.

0x01D8-0x01DC MAC_ADDRESS_7 RO 48-bit MAC Address.

0x01E0-0x025C Reserved N/A N/A

0x0260 HBM_TEMP1_MAX_REG ROHBM1_TEMP Max Temperature.Unsigned 32b int (C)

0x0264 HBM_TEMP1_AVG_REG ROHBM1_TEMP Average Temperature.Unsigned 32b int (C)

0x0268 HBM_TEMP1_INS_REG ROHBM1_TEMP Instantaneous Temperature.Unsigned 32b int (C).

0x026C VCC3V3_MAX_REG RO VCC3V3 Max Voltage.Unsigned 32b int (mV)

0x0270 VCC3V3_AVG_REG RO VCC3V3 Average Voltage.Unsigned 32b int (mV)

0x0274 VCC3V3_INS_REG RO VCC3V3 Instantaneous Voltage.Unsigned 32b int (mV)

0x0278 3V3PEX_I_IN_MAX_REG RO 3V3PEX_I_IN Max Current.Unsigned 32b int (mA)

0x027C 3V3PEX_I_IN_AVG_REG RO 3V3PEX_I_IN Average Current.Unsigned 32b int (mA)

0x0280 3V3PEX_I_IN_INS_REG RO 3V3PEX_I_IN Instantaneous Current.Unsigned 32b int (mA)

0x0284 VCC0V85_I_MAX_REG RO VCC0V85_I Max Current.Unsigned 32b int (mA)

0x0288 VCC0V85_I_AVG_REG RO VCC0V85_I Average Current.Unsigned 32b int (mA)






Address (hex) Name Access Type Description0x028C VCC0V85_I_INS_REG RO VCC0V85_I Instantaneous Current.

Unsigned 32b int (mA)0x0290 HBM_1V2_MAX_REG RO HBM_1V2 Max Voltage.

Unsigned 32b int (mV)0x0294 HBM_1V2_AVG_REG RO HBM_1V2 Average Voltage.

Unsigned 32b int (mV)0x0298 HBM_1V2_INS_REG RO HBM_1V2 Instantaneous Voltage.

Unsigned 32b int (mV)0x029C VPP2V5_MAX_REG RO VPP2V5 Max Voltage.

Unsigned 32b int (mV)0x02A0 VPP2V5_AVG_REG RO VPP2V5 Average Voltage.

Unsigned 32b int (mV)0x02A4 VPP2V5_INS_REG RO VPP2V5 Instantaneous Voltage.

Unsigned 32b int (mV)0x02A8 VCCINT_BRAM_MAX_REG RO VCCINT_BRAM Max Voltage.

Unsigned 32b int (mV)0x02AC VCCINT_BRAM_AVG_REG RO VCCINT_BRAM Average Voltage.

Unsigned 32b int (mV)0x02B0 VCCINT_BRAM_INS_REG RO VCCINT_BRAM Instantaneous Voltage.

Unsigned 32b int (mV)0x02B4 HBM_TEMP2_MAX_REG RO HBM2_TEMP Max Temperature.

Unsigned 32b int (C)0x02B8 HBM_TEMP2_AVG_REG RO HBM2_TEMP Average Temperature.

Unsigned 32b int (C)0x02BC HBM_TEMP2_INS_REG RO HBM2_TEMP Instantaneous Temperature.

Unsigned 32b int (C).0x02C0 12V_AUX1_MAX_REG RO 12V_AUX1 Max Voltage.

Unsigned 32b int (mV)0x02C4 12V_AUX1_AVG_REG RO 12V_AUX1 Average Voltage.

Unsigned 32b int (mV)0x02C8 12V_AUX1_INS_REG RO 12V_AUX1 Instantaneous Voltage.

Unsigned 32b int (mV)0x02CC VCCINT_TEMP_MAX_REG RO VCCINT Max Temperature.

Unsigned 32b int (C)0x02D0 VCCINT_TEMP_AVG_REG RO VCCINT Average Temperature.

Unsigned 32b int (C)0x02D4 VCCINT_TEMP_INS_REG RO VCCINT Instantaneous Temperature.

Unsigned 32b int (C).0x02D8 PEX_12V_POWER_MAX_REG RO PEX_12V Max Power.

Unsigned 32b int (mW)






Address (hex) Name Access Type Description0x02DC PEX_12V_POWER_AVG_REG RO PEX_12V Average Power.

Unsigned 32b int (mW)0x02E0 PEX_12V_POWER_INS_REG RO PEX_12V Instantaneous Power.

Unsigned 32b int (mW)0x02E4 PEX_3V3_POWER_MAX_REG RO PEX_3V3 Max Power.

Unsigned 32b int (mW)0x02E8 PEX_3V3_POWER_AVG_REG RO PEX_3V3 Average Power.

Unsigned 32b int (mW)0x02EC PEX_3V3_POWER_INS_REG RO PEX_3V3 Instantaneous Power.

Unsigned 32b int (mW)0x02F0 AUX_3V3_I_MAX_REG RO AUX_3V3_I Max Current.

Unsigned 32b int (mA)0x02F4 AUX_3V3_I_AVG_REG RO AUX_3V3_I Average Current.

Unsigned 32b int (mA)0x02F8 AUX_3V3_I_INS_REG RO AUX_3V3_I Instantaneous Current.

Unsigned 32b int (mA)0x02FC Reserved N/A N/A0x300 HOST_MSG_OFFSET_REG RO Offset of MAILBOX inside register map.0x0304 HOST_MSG_ERROR_REG RO 0x0: "CMC_HOST_MSG_NO_ERR"

0x1: "CMC_HOST_MSG_BAD_OPCODE_ERR"0x2:"CMC_HOST_MSG_BRD_INFO_MISSING_ERR"0x3: "CMC_HOST_MSG_LENGTH_ERR"0x4: "CMC_HOST_MSG_SAT_FW_WRITE_FAIL"0x5: "CMC_HOST_MSG_SAT_FW_UPDATE_FAIL"0x6: "CMC_HOST_MSG_SAT_FW_LOAD_FAIL"0x7: "CMC_HOST_MSG_SAT_FW_ERASE_FAIL"0x9: "CMC_HOST_MSG_CSDR_FAILED"0xA: "CMC_HOST_MSG_QSFP_FAIL"

0x0308 Reserved N/A N/A0x030C HOST_STATUS2_REG RO Bits 31:1 - Reserved

Bit 0 - REG_MAP Ready ('0'=false, '1'=true)This bit indicates the REG_MAP is ready. Mailboxfeatures/reading of sensor values should not beattempted until this bit is set.

0x0310 Reserved N/A N/A0x0314 VCC1V2_I_MAX_REG RO VCC1V2_I Max Current

Unsigned 32b int (mA)0x0318 VCC1V2_I_AVG_REG RO VCC1V2_I Average Current

Unsigned 32b int (mA)0x031C VCC1V2_I_INS_REG RO VCC1V2_I Instantaneous Current

Unsigned 32b int (mA)0x0320 V12_IN_I_MAX_REG RO V12_IN_I Max Current

Unsigned 32b int (mA)






Address (hex) Name Access Type Description0x0324 V12_IN_I_AVG_REG RO V12_IN_I Average Current.

Unsigned 32b int (mA)0x0328 V12_IN_I_INS_REG RO V12_IN_I Instantaneous Current

Unsigned 32b int (mA)0x032C V12_IN_AUX0_I_MAX_REG RO V12_IN_AUX0_I Max Current

Unsigned 32b int (mA)0x0330 V12_IN_AUX0_I_AVG_REG RO V12_IN_AUX0_I Average Current

Unsigned 32b int (mA)0x0334 V12_IN_AUX0_I_INS_REG RO V12_IN_AUX0_I Instantaneous Current

Unsigned 32b int (mA)0x0338 V12_IN_AUX1_I_MAX_REG RO V12_IN_AUX1_I Max Current

Unsigned 32b int (mA)0x033C V12_IN_AUX1_I_AVG_REG RO V12_IN_AUX1_I Average Current

Unsigned 32b int (mA)0x0340 V12_IN_AUX1_I_INS_REG RO V12_IN_AUX1_I Instantaneous Current

Unsigned 32b int (mA)0x0344 VCCAUX_MAX_REG RO VCCAUX Max Voltage

Unsigned 32b int (mV)0x0348 VCCAUX_AVG_REG RO VCCAUX Average Voltage.

Unsigned 32b int (mV)0x034C VCCAUX_INS_REG RO VCCAUX Instantaneous Voltage

Unsigned 32b int (mV)0x0350 VCCAUX_PMC_MAX_REG RO VCCAUX_PMC Max Voltage

Unsigned 32b int (mV)0x0354 VCCAUX_PMC_AVG_REG RO VCCAUX_PMC Average Voltage

Unsigned 32b int (mV)0x0358 VCCAUX_PMC_INS_REG RO VCCAUX_PMC Instantaneous Voltage

Unsigned 32b int (mV)0x035C VCCRAM_MAX_REG RO VCCRAM Max Voltage

Unsigned 32b int (mV)0x0360 VCCRAM_AVG_REG RO VCCRAM Average Voltage

Unsigned 32b int (mV)0x0364 VCCRAM_INS_REG RO VCCRAM Instantaneous Voltage

Unsigned 32b int (mV)

0x0368-0x036C Reserved N/A N/A

0x0370 POWER_GOOD_INS_REG RO Bits 31:1 - ReservedBit 0 : 0 = Power Good, 1 = Power Bad

0x0374-0x0C48 Reserved N/A N/A

0x0C4C CORE_BUILD_VERSION_REG RO Core Build Version0x0C50 OEM_ID_REG RO OEM ID

0x0C54-0x0FFC Reserved N/A N/A






Address (hex) Name Access Type DescriptionHOST_MSG_OFFSET

_REG-0x1FFCMAILBOX RW Mailbox Interface

See Mailbox Interface for more details.





Chapter 4

Designing with the SubsystemThis section includes guidelines and additional information to facilitate designing with thesubsystem.

ClockingTable 19: Clocks

Clock Description

aclk_ctrl This clock pin should be connected to the control path AXI-Lite clock used in the design (50MHz).

ResetsThe CMS Subsystem uses a single active-low reset pin, aresetn_ctrl. This reset should besynchronous to aclk_ctrl and will reset the entire CMS design.

Additionally a host accessible register, MB_RESETN_REG can be used to reset the CMSMicroBlaze subsystem.

Note: Following power-up or assertion of aresetn_ctrl, MB_RESETN_REG will be reset to 0x0 placingthe MicroBlaze subsystem into the reset state. Driver firmware will be required to write 0x1 to this registerto take the MicroBlaze Subsystem out of reset.

AddressingThe CMS Subsystem requires 256k of Address space (0x4_0000).

Chapter 4: Designing with the Subsystem




InterruptsExternal interrupts in the CMS Subsystem are defined in the following table.

Table 20: External CMS Interrupts

Interrupt Name Direction Descriptioninterrupt_hbm_cattrip Input This interrupt is received from the HBM subsystem

indicating a HBM CATTRIP has occurred.

interrupt_host Output This interrupt is generated by the CMS IP towards the hostin the event of a watchdog timeout. The watchdog timer willexpire if left unserviced for approximately four seconds. Thehost can clear the interrupt via the HOST_INTC interruptcontroller.See HOST_INTC register description for more information.

Chapter 4: Designing with the Subsystem




Chapter 5

Design Flow StepsThis section describes customizing and generating the subsystem, constraining the subsystem,and the simulation, synthesis, and implementation steps that are specific to this IP subsystem.More detailed information about the standard Vivado® design flows and the IP integrator can befound in the following Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

• Vivado Design Suite User Guide: Designing with IP (UG896)

• Vivado Design Suite User Guide: Getting Started (UG910)

• Vivado Design Suite User Guide: Logic Simulation (UG900)

Customizing and Generating the SubsystemThis section includes information about using Xilinx® tools to customize and generate thesubsystem in the Vivado® Design Suite.

If you are customizing and generating the subsystem in the Vivado IP integrator, see the VivadoDesign Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailedinformation. IP integrator might auto-compute certain configuration values when validating orgenerating the design. To check whether the values do change, see the description of theparameter in this chapter. To view the parameter value, run the validate_bd_designcommand in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parametersassociated with the IP subsystem using the following steps:

1. Select the IP from the IP catalog.

2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the VivadoDesign Suite User Guide: Getting Started (UG910).

Chapter 5: Design Flow Steps


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug994-vivado-ip-subsystems.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug896-vivado-ip.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug910-vivado-getting-started.pdf

https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug900-vivado-logic-simulation.pdf






Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896).

Constraining the SubsystemRequired Constraints

The following constraints are required for this subsystem.

Alveo Card (U200/U250) I/O ConstraintsSatellite UART

set_property PACKAGE_PIN BA19 [get_ports satellite_uart_rxd]set_property -dict {IOSTANDARD LVCMOS12} [get_ports satellite_uart_rxd]set_property PACKAGE_PIN BB19 [get_ports satellite_uart_txd]set_property -dict {IOSTANDARD LVCMOS12 DRIVE 4} [get_ports satellite_uart_txd]

Satellite GPIO

set_property PACKAGE_PIN AR20 [get_ports satellite_gpio_tri_io[0]]set_property -dict {IOSTANDARD LVCMOS12} [get_ports satellite_gpio_tri_io[0]]set_property PACKAGE_PIN AM20 [get_ports satellite_gpio_tri_io[1]]set_property -dict {IOSTANDARD LVCMOS12} [get_ports satellite_gpio_tri_io[1]]set_property PACKAGE_PIN AM21 [get_ports satellite_gpio_tri_io[2]]set_property -dict {IOSTANDARD LVCMOS12} [get_ports satellite_gpio_tri_io[2]]set_property PACKAGE_PIN AN21 [get_ports satellite_gpio_tri_io[3]]set_property -dict {IOSTANDARD LVCMOS12} [get_ports satellite_gpio_tri_io[3]]

Alveo U280 I/O ConstraintsSatellite UART

set_property PACKAGE_PIN E28 [get_ports satellite_uart_rxd]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_uart_rxd]set_property PACKAGE_PIN D29 [get_ports satellite_uart_txd]set_property -dict {IOSTANDARD LVCMOS18 DRIVE 4} [get_portssatellite_uart_txd]






Satellite GPIO

set_property PACKAGE_PIN K28 [get_ports satellite_gpio_tri_io[0]]set_property -dict {IOSTANDARD LVCMOS18} [get_portssatellite_gpio_tri_io[0]]set_property PACKAGE_PIN J29 [get_ports satellite_gpio_tri_io[1]]set_property -dict {IOSTANDARD LVCMOS18} [get_portssatellite_gpio_tri_io[1]]set_property PACKAGE_PIN K29 [get_ports satellite_gpio_tri_io[2]]set_property -dict {IOSTANDARD LVCMOS18} [get_portssatellite_gpio_tri_io[2]]set_property PACKAGE_PIN J31 [get_ports satellite_gpio_tri_io[3]]set_property -dict {IOSTANDARD LVCMOS18} [get_portssatellite_gpio_tri_io[3]]

Alveo Card (U50) I/O ConstraintsSatellite UART

set_property PACKAGE_PIN BB26 [get_ports satellite_uart_rxd]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_uart_rxd]set_property PACKAGE_PIN BB25 [get_ports satellite_uart_txd]set_property -dict {IOSTANDARD LVCMOS18 DRIVE 4} [get_ports satellite_uart_txd]

Satellite GPIO

set_property PACKAGE_PIN C16 [get_ports satellite_gpio_tri_io[0]]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_gpio_tri_io[0]]set_property PACKAGE_PIN C17 [get_ports satellite_gpio_tri_io[1]]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_gpio_tri_io[1]]

Alveo Card (Next Generation) I/O ConstraintsSatellite UART

set_property PACKAGE_PIN BJ42 [get_ports satellite_uart_rxd]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_uart_rxd]set_property PACKAGE_PIN BH42 [get_ports satellite_uart_txd]set_property -dict {IOSTANDARD LVCMOS18 DRIVE 4} [get_ports satellite_uart_txd]

Satellite GPIO

set_property PACKAGE_PIN BE46 [get_ports satellite_gpio_tri_io[0]]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_gpio_tri_io[0]]set_property PACKAGE_PIN BH46 [get_ports satellite_gpio_tri_io[1]]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_gpio_tri_io[1]]set_property PACKAGE_PIN BF45 [get_ports satellite_gpio_tri_io[2]]





set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_gpio_tri_io[2]]set_property PACKAGE_PIN BF46 [get_ports satellite_gpio_tri_io[3]]set_property -dict {IOSTANDARD LVCMOS18} [get_ports satellite_gpio_tri_io[3]]

SimulationFor comprehensive information about Vivado® simulation components, as well as informationabout using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation(UG900).

Synthesis and ImplementationFor details about synthesis and implementation, see the Vivado Design Suite User Guide: Designingwith IP (UG896).







Chapter 6

Example DesignThis chapter contains information about the example design provided in the Vivado® DesignSuite.

OverviewThe top module instantiates all components of the core and example design that are needed toimplement the design in hardware, as shown in the following figure.

The example design demonstrates connections required to add the CMS Subsystem to a PCIebased platform design. Implementing the example design in hardware enables you to read cardsensor values via the CMS shared memory map.

Chapter 6: Example Design




Figure 6: Card Management Solution Example Design

BaseClocking

XDMAPCIe

Subsystem

AXIInterrupt

Controller

CMS Subsystem

(DUT)

AXIInter-

connect

host

_int

erru

pt

pcie_perstn_rst

pcie_mgt_clk

pcie_clk

aclk_ctrl,aresetn_ctrl

AXI-Lite AXI-Lite

AXI-Litesatellite_uart

satellite_gpio

X23148-091919

Implementing the Example DesignAfter following the steps described in Design Flow Steps to generate the core, implement theexample design as follows:

1. Right-click the core in the Hierarchy window, and select Open IP Example Design.

2. When a new window pops up, asking you to specify a directory for the example design,select a new directory or keep the default directory. A new project is automatically created inthe selected directory and it is opened in a new Vivado window.

3. In the Flow Navigator (left-side pane), click Run Implementation and follow the directions.

Related Information

Design Flow Steps





Example Design FilesThe following table shows the files delivered as part of the example design.

Table 21: Example Design Constraints File

Name Description<component_name>_exdes.xdc Top-level constraints file for the example design





Appendix A

Upgrading

Changes from v2.0 to v3.0Parameter Changes

There are no parameter changes.

Port Changes

Table 22: Port Changes

v2_0 v3_0 Notessatellite_gpio satellite_gpio Changed from master GPIO interface type in v2.0 to input interrupt type

in v3.0 to enable direct connection with the CMS MicroBlaze™ InterruptController.

Other Changes

• Moved to Core Firmware

• MicroBlaze Instruction memory increased to 128k

Changes from v1.0 to v2.0Parameter Changes

There are no parameter changes.

Port Changes

Table 23: Port Changes

v1_0 v2_0 Notess_axi_ctrl_mgmt s_axi_ctrl Removed reference to MGMT

aclk_ctrl_mgmt aclk_ctrl Removed reference to MGMT

Appendix A: Upgrading




Table 23: Port Changes (cont'd)

v1_0 v2_0 Notesaresetn_ctrl_mgmt aresetn_ctrl Removed reference to MGMT

clk_cmc N/A Port Removed

clk_cmc_locked N/A Port Removed

N/A interrupt_hbm_cattrip New port visible on HBM Alveo cards only

N/A hbm_temp_1 New port visible on HBM Alveo cards only

N/A hbm_temp_2 New port visible on HBM Alveo cards only

Other Changes

• Address map range changed to 256k

• New base addresses for all host accessible registers

Appendix A: Upgrading




Appendix B

DebuggingThis appendix includes details about resources available on the Xilinx® Support website anddebugging tools.

If the IP requires a license key, the key must be verified. The Vivado® design tools have severallicense checkpoints for gating licensed IP through the flow. If the license check succeeds, the IPcan continue generation. Otherwise, generation halts with an error. License checkpoints areenforced by the following tools:

• Vivado Synthesis

• Vivado Implementation

• write_bitstream (Tcl command)

IMPORTANT! IP license level is ignored at checkpoints. The test confirms a valid license exists. It does notcheck IP license level.

Finding Help on Xilinx.comTo help in the design and debug process when using the subsystem, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.

DocumentationThis product guide is the main document associated with the subsystem. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.

Appendix B: Debugging


https://www.xilinx.com/support.html

https://forums.xilinx.com/




https://www.xilinx.com/support/download.html



Solution CentersSee the Xilinx Solution Centers for support on devices, software tools, and intellectual propertyat all stages of the design cycle. Topics include design assistance, advisories, and troubleshootingtips.

Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.

Answer Records for this subsystem can be located by using the Search Support box on the main Xilinx support web page. To maximize your search results, use keywords such as:

• Product name

• Tool message(s)

• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.

• Customize the solution beyond that allowed in the product documentation.

• Change any section of the design labeled DO NOT MODIFY.

To ask questions, navigate to the Xilinx Community Forums.

Debug ToolsThere are many tools available to address CMS Subsystem design issues. It is important to knowwhich tools are useful for debugging various situations.



https://www.xilinx.com/support/solcenters.htm






Vivado Design Suite Debug FeatureThe Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly intoyour design. The debug feature also allows you to set trigger conditions to capture applicationand integrated block port signals in hardware. Captured signals can then be analyzed. Thisfeature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®

devices.

The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Hardware DebugHardware issues can range from link bring-up to problems seen after hours of testing. Thissection provides debug steps for common issues. The Vivado® debug feature is a valuableresource to use in hardware debug. The signal names mentioned in the following individualsections can be probed using the debug feature for debugging the specific problems.

General ChecksEnsure that all the timing constraints for the core were properly incorporated from the exampledesign and that all constraints were met during implementation.

• Does it work in post-place and route timing simulation? If problems are seen in hardware butnot in timing simulation, this could indicate a PCB issue. Ensure that all clock sources areactive and clean.

• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring thelocked port.

• If your outputs go to 0, check your licensing.



https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf



Appendix C

Additional Resources and LegalNotices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.

Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:

• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.

• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:

• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.

Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

ReferencesThese documents provide supplemental material useful with this guide:

Appendix C: Additional Resources and Legal Notices




https://www.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs

https://www.xilinx.com/cgi-bin/docs/rdoc?t=docnav



1. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

2. Vivado Design Suite User Guide: Designing with IP (UG896)

3. Vivado Design Suite User Guide: Getting Started (UG910)

4. Vivado Design Suite User Guide: Logic Simulation (UG900)

5. AXI Interrupt Controller (INTC) LogiCORE IP Product Guide (PG099)

6. Getting Started with Alveo Data Center Accelerator Cards (UG1301)

Revision HistoryThe following table shows the revision history for this document.

Section Revision Summary11/24/2020 Version 3.0

Chapter 1: Introduction • Updated the list of supported Alveo cards to include U50 and next-generation.

• Added a list of card management features supported through mailboxinterface.

Features • Added list of card management features supported through mailboxinterface.

• Removed voltage monitoring, current monitoring, temperature monitoring,fan speed monitoring, and power monitoring from features list.

IP Facts • Updated the list of supported Alveo cards to include U50 and next-generation.

Table 1: Satellite Controller FirmwareCompatibility

Added table.

Figure 1: Card Management SolutionSubsystem Block Diagram

Moved figure from the introduction and revised it to include next-generationcards.

Sensor Monitoring Added section.

Mailbox Interface Added sub-sections for supported features.

Card Information Reporting Added section.

Satellite Controller Firmware Update Added section.

QSFP Management Added section.

Figure 4: CMS Subsystem TypicalConfiguration

Revised figure.

Register Space Updated and added register descriptions.

Alveo Card (Next Generation) I/OConstraints

Updated section.

08/24/2020 Version 3.0

General Updates • Firmware update• Control Register update for Clock Scaling and HBM Support (bits 28:27)• Removed references to DRIVE 4 from Satellite GPIO constraints







https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_intc;v=latest;d=pg099-axi-intc.pdf

https://www.xilinx.com/cgi-bin/docs/bkdoc?v=latest;k=accelerator-cards;d=ug1301-getting-started-guide-alveo-accelerator-cards.pdf



Section Revision Summary06/03/2020 Version 3.0

General Updates • Moved to 'Core Firmware'• Fixed issues in 2019.2 Letter of Limitations

10/30/2019 Version 2.0

Chapter 6: Example Design Added Example Design

Test Bench Added Test Bench information

05/22/2019 Version 1.0

Initial release. N/A

Please Read: Important Legal NoticesThe information disclosed to you hereunder (the "Materials") is provided solely for the selectionand use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials aremade available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES ANDCONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TOWARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANYPARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, includingnegligence, or under any other theory of liability) for any loss or damage of any kind or naturerelated to, arising under, or in connection with, the Materials (including your use of theMaterials), including for any direct, indirect, special, incidental, or consequential loss or damage(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of anyaction brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinxhad been advised of the possibility of the same. Xilinx assumes no obligation to correct anyerrors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materialswithout prior written consent. Certain products are subject to the terms and conditions ofXilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms containedin a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe orfor use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which canbe viewed at https://www.xilinx.com/legal.htm#tos.

AUTOMOTIVE APPLICATIONS DISCLAIMER

AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOTWARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONSTHAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS ASAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING



https://www.xilinx.com/legal.htm#tos





OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TESTSUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATIONWITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TOAPPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCTLIABILITY.

Copyright

© Copyright 2019-2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal,Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in theUnited States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG andused under license. All other trademarks are the property of their respective owners.





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