Carrier Mobility and VelocityCarrier Mobility and Velocity

MobilityMobility - the ease at which a carrier - the ease at which a carrier (electron or hole) moves in a (electron or hole) moves in a semiconductorsemiconductor– Symbol: Symbol: nn for electrons and for electrons and pp for holes for holes

Drift velocityDrift velocity – the speed at which a – the speed at which a carrier moves in a crystal when an carrier moves in a crystal when an electric field is presentelectric field is present– For electrons: vFor electrons: vdd = = n n EE

– For holes: For holes: v vdd = = p p EE

H

L

W

Va

Va

ResistanceResistance

A

L

WH

LR

Resistivity and ConductivityResistivity and Conductivity

Fundamental material propertiesFundamental material properties

1

11

ipnopon nqpnq

ResistivityResistivity

dn

d

ipdn

opon

Nq

N

nNq

pnq

1

1

1

2

n-type n-type semiconductorsemiconductor

p-type p-type semiconductorsemiconductor

ap

apa

in

opon

Nq

NNn

q

pnq

1

1

1

2

Drift CurrentsDrift Currents

EpnAqIL

VE

pnAqL

VI

pnqAL

V

R

VI

opon

a

opona

opon

aa

1

DiffusionDiffusion

When there are changes in the When there are changes in the concentration of electrons and/or concentration of electrons and/or holes along a piece of semiconductorholes along a piece of semiconductor– the Coulombic repulsion of the carriers the Coulombic repulsion of the carriers

force the carriers to flow towards the force the carriers to flow towards the region with a lower concentration.region with a lower concentration.

Diffusion CurrentsDiffusion Currents

opondiffdiffdiff

opopdiff

diff

onondiff

diff

pDnDqJJA

Idx

dpqDpqDJ

A

Idx

dnqDnqDJ

A

I

pn

p

p

n

n

Relationship between Relationship between Diffusivity and MobilityDiffusivity and Mobility

q

kTD

q

kTD

p

p

n

n

Mobility vs. Dopant Mobility vs. Dopant Concentration in SiliconConcentration in Silicon

http://www.ioffe.ru/SVA/NSM/Semicond/Si/electric.html#Hall

Wafer CharacterizationWafer Characterization

X-ray DiffractionX-ray Diffraction– Crystal Orientation Crystal Orientation

Van der Pauw or Hall MeasurementsVan der Pauw or Hall Measurements– ResistivityResistivity– MobilityMobility

Four Point ProbeFour Point Probe– ResisitivityResisitivity

Hot Point ProbeHot Point Probe– n or p-type materialn or p-type material

Van der PauwVan der Pauw

Four equidistant Four equidistant Ohmic contactsOhmic contacts

Contacts are small Contacts are small in areain area

Current is injected Current is injected across the diagonalacross the diagonal

Voltage is measured Voltage is measured across the other across the other diagonaldiagonal Top view of Van der Pauw sample

http://www.eeel.nist.gov/812/meas.htm#geom

CalculationCalculation

Resistance is determined with and Resistance is determined with and without a magnetic field applied without a magnetic field applied perpendicular to the sample.perpendicular to the sample.

FRRt

R

B

tH

22ln14,2334,12

24,13

F is a correction factor that F is a correction factor that takes into account the takes into account the geometric shape of the geometric shape of the sample.sample.

Hall MeasurementHall Measurement

See See http://www.eeel.nist.gov/812/hall.htmlhttp://www.eeel.nist.gov/812/hall.html for a more complete explanationfor a more complete explanation

http://www.sp.phy.cam.ac.uk/SPWeb/research/QHE.htmlhttp://www.sp.phy.cam.ac.uk/SPWeb/research/QHE.html

CalculationCalculation

Measurement of resistance is made while Measurement of resistance is made while a magnetic field is applied perpendicular a magnetic field is applied perpendicular to the surface of the Hall sample.to the surface of the Hall sample.– The force applied causes a build-up of carriers The force applied causes a build-up of carriers

along the sidewall of the samplealong the sidewall of the sample The magnitude of this buildup is also a function of The magnitude of this buildup is also a function of

the mobility of the carriersthe mobility of the carriers

where A is the cross-sectional area.where A is the cross-sectional area.

L

A

R

RR

L

HHH

Four Point ProbeFour Point Probe

Probe tips must Probe tips must make an Ohmic make an Ohmic contactcontact– Useful for SiUseful for Si– Not most compound Not most compound

semiconductorssemiconductors

S when t 2ln

S when t 2

I

VtI

VS

Hot Point ProbeHot Point Probe

Simple method to determine whether Simple method to determine whether material is n-type or p-typematerial is n-type or p-type– Note that the sign of the Hall voltage, Note that the sign of the Hall voltage,

VVHH, and on , and on R R13,2413,24 in the Van der Pauw in the Van der Pauw measurement also provide information measurement also provide information on doping.on doping.

Visual Information on Crystal Visual Information on Crystal Orientation and DopingOrientation and Doping

Used on wafers that are less than 200 mm in diameter (8 inches)

Key InventionsKey Inventions

Three discoveries made integrated Three discoveries made integrated circuits possible:circuits possible:– Invention of the transistorInvention of the transistor

(1949 by Brattain, Bardeen, and (1949 by Brattain, Bardeen, and Schockley; Nobel prize 1972)Schockley; Nobel prize 1972)

– Development of planar transistor Development of planar transistor technologytechnology(1959 by Bob Noyce and Jean Hoerni; (1959 by Bob Noyce and Jean Hoerni; Noyce was a founder of Intel)Noyce was a founder of Intel)

– Invention of integrated circuitInvention of integrated circuit(1959 by Kilby; Nobel prize 2000)(1959 by Kilby; Nobel prize 2000)

The First TransistorThe First Transistor

The first transistor, a point The first transistor, a point contact pnp Ge device, was contact pnp Ge device, was invented in 1947 by John invented in 1947 by John Bardeen, Walter Brattain, Bardeen, Walter Brattain, and William Shockley. They and William Shockley. They received the Nobel Prize in received the Nobel Prize in physics in 1956.physics in 1956.

The first integrated circuitThe first integrated circuit

The first integrated circuit The first integrated circuit was invented by Jack Kilby was invented by Jack Kilby of TI. He received the of TI. He received the Nobel Prize in 2000.Nobel Prize in 2000.

Levels of Integrated CircuitsLevels of Integrated Circuits Small Scale Integration (SSI)Small Scale Integration (SSI)

1-10 transistors1-10 transistors Medium Scale Integration (MSI)Medium Scale Integration (MSI)

up to 100 transistorsup to 100 transistors Large Scale Integration (LSI)Large Scale Integration (LSI)

up to 10,000 transistorsup to 10,000 transistors Very Large Scale Integration (VLSI)Very Large Scale Integration (VLSI)

millions of transistorsmillions of transistors Ultra Large Scale IntegrationUltra Large Scale Integration Wafer Scale IntegrationWafer Scale Integration System on a Chip (SOC)System on a Chip (SOC) 3D IC3D IC

Increase in Complexity of Increase in Complexity of ChipsChips

Moore’s LawMoore’s Law

Gordon Moore observed (1965) that Gordon Moore observed (1965) that the number of transistors on a Si chip the number of transistors on a Si chip was doubling every year. Later, was doubling every year. Later, revised this to every 18 months.revised this to every 18 months.– This cannot continue forever; when This cannot continue forever; when

components reach size of atoms, the components reach size of atoms, the physics changes.physics changes.

– Currently, there is no known solution. Currently, there is no known solution.

Historical TrendsHistorical Trends of Minimum Feature Size of Minimum Feature Size

Minimum Minimum Feature Size: Feature Size: 13% reduction 13% reduction each year; each year; recently closer recently closer to 10%.to 10%.

Projections from 1997 Projections from 1997 RoadmapRoadmap

The fundamental assumption is that Si will be the The fundamental assumption is that Si will be the material of choice and that Moore’s law will apply until material of choice and that Moore’s law will apply until 20122012

Scaling as a Function of Cycle Scaling as a Function of Cycle TimeTime

1)(

7.0

2

12

TSTCARR

S

S is the minimum feature size

T is the cycle time

CARR is the Compound Annual Reduction Rate

On average, the minimum feature size On average, the minimum feature size decreases by decreases by 10-13%/10-13%/year. Currently at 45 or year. Currently at 45 or 32 nm node32 nm node

Where are we today?Where are we today?

Semiconductor TrendsSemiconductor Trends Overall chip size has been increasing by Overall chip size has been increasing by

16%/16%/year over past 35 yearsyear over past 35 years– Recently 6.3%/year for microprocessors and Recently 6.3%/year for microprocessors and

12%/year for DRAM12%/year for DRAM– Major limitation is the number of pads that can Major limitation is the number of pads that can

be placed on the chip to get signals in and outbe placed on the chip to get signals in and out Trends are now projected by the SIA Trends are now projected by the SIA

national Technology Roadmap for national Technology Roadmap for Semiconductors Semiconductors

Current version is called Current version is called International Technology Roadmap for SemiconductorInternational Technology Roadmap for Semiconductorss

Cost of Designing a ChipCost of Designing a Chip

The cost of designing a chip has The cost of designing a chip has increased with the complexity of the increased with the complexity of the chip.chip.– Initially, the cost seemed to follows Initially, the cost seemed to follows

Moore’s law—the cost doubled every Moore’s law—the cost doubled every time the complexity doubled.time the complexity doubled.

– The controlling factor was the The controlling factor was the development of CAD and modeling development of CAD and modeling software.software.

CleanroomsCleanrooms

Federal Standard

TC 209 ISO

1

2

1 3

10 4

100 5

1,000 6

10,000 7

100,000 8

9

First Line of Protection: Bunny First Line of Protection: Bunny SuitsSuits

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