1

1

2

2

3

3

4

4

D D

C C

B B

A A

1 18

Carte Blanche for the Apple II

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\CarteBlanche.SchDoc

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IISLOT

APPLE II SLOTAPPLEIISLOT.SchDoc

SYS_JTAG

JTAG INTERFACECON_10WBOXHDREDGEM.SchDoc

SYS_JTAG

APPLEBUS

NB2PBIO

SPI+ID

I2C

CLOCKS

SRAM

BOOTPROM

SVGA

IDE

SDIO

SYSCLK

ENABLE

FPGAXC3S500E-4PQ208.SchDoc

ENABLE

IISLOTAPPLEBUS

LEVEL TRANSLATORLEVELTRANSLATOR.SchDoc

NB2PBIO

SPI+ID

I2C

CLOCKS

PERIPHERAL BDPERIPHERAL.SchDoc

AIISAIIB

SYS_JTAG

1V2 POWER SUPPLYPSU_1084_1V2.SchDoc

1V8 POWER SUPPLYPSU_1084_1V8.SchDoc

2V5 POWER SUPPLYPSU_1084_2V5.SchDoc

3V3 POWER SUPPLYPSU_1084_3V3.SchDoc

FPGAPOWERFPGAPOWER.SchDoc

TOP LEVEL COLOUR CODE:

PINK:GREEN:BLUE:RED:

I/O CONNECTION/REAL WORLD ACCESSINTERNAL PROCESS/SERVICESYSTEM CORE/USER AVAILABLEPOWER RELATED SERVICE

SRAM

HIGH SPEED RAMSRAM-128Kx8x2.SchDoc

BOOTPROM

BOOT PROMM25Pxx SPI_BOOT.SchDoc

SVGA

VIDEO INTERFACESVGA.SchDoc

SDIO

SERIAL DATA IO CARDSDIO.SchDoc

IDE

IDE INTERFACEIDE.SchDocROM

RAM

IDE

SD

VGA

SYSCLK

ON BOARD OSCILLATORSYSCLK.SchDoc

SYSCLK

BARCODE/SERIAL NUMBER

SN1

SERIAL NUMBERFD1Fiducial - Round

FD2Fiducial - Round

NOTES IN TURQUOISE REFER TOXILINX DOCUMENTATION.

1

1

2

2

3

3

4

4

D D

C C

B B

A A

2 18

JTAG INTERFACE

30/09/2009 9:39:02 PM

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12345678910

J210W MALE BOXED HEADER

JTAG PROGRAMMING INTERFACE

HOST_HARD_TDI_NHOST_HARD_TDO_N

HOST_HARD_TCK_N

HOST_HARD_TMS_N

HOST_SOFT_TDI_N

HOST_SOFT_TDO_N

HOST_SOFT_TCK_NHOST_SOFT_TMS_N

VREF

SYS_JTAG

TMSTDO

TDITCK

JTAG

TMSTDOTDITCK

JTAG

HARD

SOFT

VREF

SYS_JTAG

R14K7 1%

R24K7 1%

R34K7 1%

R44K7 1%

R656R 1%

R556R 1%

3V3

IF YOU ARE CONNECTING THIS INTERFACE TOUSER BOARD A OR USER BOARD B

DO NOT CONNECT THE REF PIN. REFERTO THE APPLELOGIC WEBSITE FOR DETAILS

GND

(DS312-P104)

28 BIT DEVICE ID:

XC3S250E -0x1C 1A 093

XC3S500E -0x1C 22 093

3V3

R74K7 1%

R84K7 1%

R94K7 1%

R104K7 1%

1

1

2

2

3

3

4

4

D D

C C

B B

A A

3 18

FPGA POWER CONFIG.

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\FPGAPOWER.SchDoc

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VCCAUX7

VCCAUX149

VCCAUX111

VCCAUX92

VCCAUX195

VCCAUX66

VCCAUX166

VCCAUX44

VCCINT170

VCCINT117

VCCINT13

VCCINT67

VCCO_0201

VCCO_0176

VCCO_0191

VCCO_1114

VCCO_1125

VCCO_1143

VCCO_288

VCCO_273

VCCO_259

VCCO_321

VCCO_346

VCCO_338

U3GXC3S250E-4PQ208C

GND156

GND198

GND10

GND131

GND17

GND182

GND27

GND95

GND37

GND121

GND52

GND141

GND53

GND173

GND70

GND188

GND79

GND208

GND85

GND105

U3HXC3S250E-4PQ208C

GND

3V3

3V3

C251uF 16V

C270.1uF 16V

C210.1uF 16V

C220.1uF 16V

C180.1uF 16V

C171uF 16V

C190.1uF 16V

C230.1uF 16V

C260.1uF 16V

GND

GND

2V5 1V2

GND

3V3

GND

3V3

1V2

C130.1uF 16V

C140.1uF 16V

C150.1uF 16V

GND

2V5

C160.1uF 16V

C240.1uF 16V

C200.1uF 16V3V33V3

C291uF 16V

C310.1uF 16V

C300.1uF 16V

GND

3V3

C320.1uF 16V

C330.1uF 16V

C340.1uF 16V

C350.1uF 16V

GND

2V5

C360.1uF 16V

(DS312-P112)

C281uF 16V

POR REQUIREMENTS:1. - VCCINT - 1.2V2. - VCCAUX - 2.5V3. - VCCO BANK 0+1+2+3 - 3.3V

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

4 18

AII BUS LEVEL TRANSLATORS

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\LEVELTRANSLATOR.SchDoc

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NC1

A02

A13

A35

A46

A57

A24

A68

A79

GND10

NC11

A812

A913

A1014

A1115

A1216

A1317

A1418

A1519

GND20

NC21

A1622

A1723

A1824

A1925

A2026

A2127

A2228

A2329

GND30

NC31

A2432

A2533

A2634

A2735

A2836

A2937

A3038

A3139

GND40

B3141

B3042

B2943

B2844

B2745

B2646

B2547

B2448

OE449

VCC50

B2351

B2252

B2153

B2054

B1955

B1856

B1757

B1658

OE359

VCC60

B1561

B1462

B1363

B1264

B1165

B1066

B967

B868

OE269

VCC70

B771

B672

B573

B474

B375

B276

B177

B078

OE179

VCC80

U1IDTQS34X245Q3G

NC1

A02

A13

A35

A46

A57

A24

A68

A79

GND10

NC11

A812

A913

A1014

A1115

A1216

A1317

A1418

A1519

GND20

NC21

A1622

A1723

A1824

A1925

A2026

A2127

A2228

A2329

GND30

NC31

A2432

A2533

A2634

A2735

A2836

A2937

A3038

A3139

GND40

B3141

B3042

B2943

B2844

B2745

B2646

B2547

B2448

OE449

VCC50

B2351

B2252

B2153

B2054

B1955

B1856

B1757

B1658

OE359

VCC60

B1561

B1462

B1363

B1264

B1165

B1066

B967

B868

OE269

VCC70

B771

B672

B573

B474

B375

B276

B177

B078

OE179

VCC80

U2IDTQS34X245Q3G

GND

GND

GND

GND

GND

GND

GND

GND

TPS

TPS

TPS

TPS

TPS

TPS

TPS

TPS

123

D1BAV70

R111K 1%

5V0P

C61uF 16V

TPS

C3

0.1uF 16V

C4

0.1uF 16V

C5

0.1uF 16V

C7

0.1uF 16V

C8

0.1uF 16V

C9

0.1uF 16V

C11

0.1uF 16V

C12

0.1uF 16V

GND

GND

GND

GND

GND

GND

GND

GND

3.3V TO 5.0V TRANSLATORS

4.2V TRANSLATOR POWER

GND

IISLOTAPPLEBUS

C100.1uF 16V

5V0P

GND

GND

-BUS-DEV_SEL

BUS-PHASE0

BUS-USER1

BUS-PHASE1

BUS-Q3

BUS-7M

BUS-3M58

BUS-INH

BUS-RESET

BUS-IRQ

BUS-NMIBUS-DMA

BUS-RDY

BUS-IOSTROBE

BUS-SYNC

BUS-R/WBUS-A15BUS-A14

BUS-A13

BUS-A12

BUS-A11

BUS-A10

BUS-A9

BUS-A8

BUS-A7

BUS-A6

BUS-A5

BUS-A4

BUS-A3

BUS-A2

BUS-A1

BUS-A0

-BUS-IO_SELBUS-D0

BUS-D1

BUS-D2

BUS-D3

BUS-D4

BUS-D5

BUS-D6

BUS-D7

BUS-DMAINBUS-DMAOUT

BUS-INTINBUS-INTOUT

AIISLOT

-BUS-DEV_SEL

BUS-PHASE0

BUS-USER1

BUS-PHASE1

BUS-Q3

BUS-7M

BUS-3M58

BUS-INH

BUS-RESET

BUS-IRQ

BUS-NMIBUS-DMA

BUS-RDY

BUS-IOSTROBE

BUS-SYNC

BUS-R/WBUS-A15BUS-A14

BUS-A13

BUS-A12

BUS-A11

BUS-A10

BUS-A9

BUS-A8

BUS-A7

BUS-A6

BUS-A5

BUS-A4

BUS-A3

BUS-A2

BUS-A1

BUS-A0

-BUS-IO_SELBUS-D0

BUS-D1

BUS-D2

BUS-D3

BUS-D4

BUS-D5

BUS-D6

BUS-D7

BUS-DMAINBUS-DMAOUT

BUS-INTINBUS-INTOUT

AIISLOT

BUS_ENABLE

BUS_ENABLE

BUS_ENABLE

BUS_ENABLE

BUS_ENABLE

BUS_ENABLE

BUS_ENABLE

BUS_ENABLE

ENABLEENABLE

ENABLEBUS_ENABLE

APPLE II BUSDISABLED DURING

CONFIG

1

1

2

2

3

3

4

4

D D

C C

B B

A A

5 18

APPLE II BUS INTERFACE

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1

3

5

7

9

11

13

15

17

19

21

23

2527

29

31

33

35

37

39

41

43

45

47

49 2

4

6

8

10

12

14

16

18

20

22

2426

28

30

32

34

36

38

40

42

44

46

48

50

J1

II/IIE EXPANSION SLOT

BUS_D4

BUS_A10

BUS_D3

BUS_A6

BUS_D2

BUS_R_W

BUS_D1 BUS_A1BUS_A0

BUS_A9

BUS_A2

BUS_IOSTROBE

BUS_A3

BUS_A8

BUS_A4

BUS_D7BUS_D6

BUS_D0

BUS_A7

BUS_RESET

BUS_A11

BUS_A5BUS_D5

BUS_7M

+12V

BUS_A12BUS_A13BUS_A14BUS_A15

BUS_RDYBUS_DMABUS_NMI

BUS_IRQ

BUS_INH_12V_5V0BUS_3M58

BUS_Q3

BUS_PHASE0

5V0GND

N_BUS_DEV_SEL

N_BUS_IO_SEL

BUS_PHASE1BUS_USER1

BUS_SYNC

INT_INDMA_IN

-BUS-DEV_SELBUS-PHASE0BUS-USER1BUS-PHASE1BUS-Q3BUS-7MBUS-3M58BUS-INHBUS-RESETBUS-IRQBUS-NMI

BUS-DMABUS-RDYBUS-IOSTROBEBUS-SYNCBUS-R/WBUS-A15BUS-A14BUS-A13BUS-A12BUS-A11BUS-A10BUS-A9BUS-A8BUS-A7BUS-A6BUS-A5BUS-A4BUS-A3BUS-A2BUS-A1BUS-A0-BUS-IO_SEL

BUS-D0BUS-D1BUS-D2BUS-D3BUS-D4BUS-D5BUS-D6BUS-D7

BUS-DMAIN

BUS-DMAOUT

BUS-INTIN

BUS-INTOUT

AIISLOTIISLOT

GND

_12V_5V0

+12V

5V0P

C1220uF 10V

GND

3V3

C2220uF 10V

GND

5V0P

DMA_OUTINT_OUT

5.0V INTERFACE

[IOSYNC - AIII]

[M2SEL - IIGS]

[TP1 - IIe] [PH0 - AIII]

[C02x - AIII]

SLOT DEFINITION FOR APPLE II/II+/IIe/IIGS AND III

[IO SYNC IIe]

TO CARD

1

1

2

2

3

3

4

4

D D

C C

B B

A A

6 18

1V2 POWER SUPPLY

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\PSU_1084_1V2.SchDoc

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C4047uF 10VR17

0R 1%

R16330R 1%

1V2

1V2P

1.2V Output

C41220uF 10V

5V0P

GND

C380.1uF 16V

C3910uF 10V

1 2

NT3

1V2

GND GND GND GND

IN3

OUT2

ADJ

1

U5REG1084

R1

I1

.= .003mA

Vout = 1.25 (1+ ) + [0.000,120 x 120]0330

Vout = (1.25 x 1.00) + 0.0144

Vout = 1.25 + 0.0144

Vout = 1.2644v

Vout = 1.25 (1+ ) + [(IAdj) (R2)]R2R1

IAdj = 120uA

R1 TO BE IN THE 100R RANGE

R2IAdj

.= 120uA

0v

1

1

2

2

3

3

4

4

D D

C C

B B

A A

7 18

PERIPHERAL BD INTERFACE

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\PERIPHERAL.SchDoc

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23 45 67 89 10

1

11 1213 1415 1617 1819 2021 22

2425 2627 2829 3031 32

23

33 3435 3637 3839 4041 4243 44

4647 4849 5051 5253 54

45

55 5657 5859 60

1009997

9695949392919089

98

888786858483828180797877

757473727170696867

76

666564636261

MH1 MH2

MH3 MH4

HDR1MOLEX - 53751 - 1009

3V3P

5V0P

2V5P

1V2P

1V8P

GND

GND

SCLSDA

LineIn_LLineIn_RMicIn

TCK_HARD_PBTDO_HARD_PBTDI_HARD_PB

TMS_SOFT_PB

TMS_HARD_PBTDI_SOFT_PB

TCK_SOFT_PB

JTAG_CNCT_PB

EXTSPI_SCLKEXTSPI_CS_N0

EXTSPI_CS_N1

EXTSPI_DIN

TDO_SOFT_PB

EXTSPI_DOUT

CLK_ENCLK_EXT0

CLK_EXT2CLK_EXT1

ONE_WIRE_DB_PBONE_WIRE_PIO1

PB_SPARE4

ONE_WIRE_PIO2

PB_SPARE1PB_SPARE2PB_SPARE3

ONE_WIRE_ID

LineOut_RLineOut_L

R12680R 1%

R13680R 1%

R14330R 1%

R15330R 1%

_5V0

5V0P

_12V

+12V

P12G

N12G

P5G

M5G

GND

LED10603 LED GREEN

LED20603 LED GREEN

LED30603 LED GREEN

LED40603 LED GREEN

PBIO0PBIO1PBIO2PBIO3PBIO4PBIO5PBIO6PBIO7PBIO8PBIO9PBIO10PBIO11PBIO12PBIO13PBIO14PBIO15PBIO16PBIO17PBIO18PBIO19PBIO20PBIO21PBIO22PBIO23PBIO24PBIO25PBIO26PBIO27PBIO28PBIO29PBIO30PBIO31PBIO32PBIO33PBIO34PBIO35PBIO36PBIO37PBIO38PBIO39PBIO40PBIO41PBIO42PBIO43PBIO44PBIO45PBIO46PBIO47PBIO48PBIO49

SCLSDA

I2CI2C

CLK_EXT2

CLK_EXT0

CLK_EXT1

CLK_EN

CLOCKSCLOCKS

EXTSPI_DIN

EXTSPI_CS_N0

EXTSPI_DOUT

EXTSPI_SCLK

ONE_WIRE_IDEXTSPI_CS_N1

ONE_WIRE_DB_PB

SPI+IDSPI+ID

012345678910111213141516171819202122232425262728293031323334353637383940414243444546474849

NB2PBIONB2PBIO

5V0P

OPTIONAL POWER

5V0

GND

1

23

J3POWERJACK RA 3PIN

GND

1 2

NT1

1 2

NT2

C6447uF 10V

5V0P

GND

14mA

14mA

8mA

8mA

S1MOUNTING HOLE 3MM SOLDER STANDOFF

S2MOUNTING HOLE 3MM SOLDER STANDOFF

S3MOUNTING HOLE 3MM SOLDER STANDOFF

1

1

2

2

3

3

4

4

D D

C C

B B

A A

8 18

1V8 POWER SUPPLY

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\PSU_1084_1V8.SchDoc

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C4447uF 10VR19

56R 1%

R18120R 1%

1V8

1V8P

1.8V Output

C45220uF 10V

C420.1uF 16V

C4310uF 10V

1 2

NT4

1V85V0P

GND GND GND GND GND

IN3

OUT2

ADJ

1

U6REG1084

R1

I1

.= 01mA

Vout = 1.25 (1+ ) + [0.000,120 x 120]56120

Vout = (1.25 x 1.455) + 0.0144

Vout = 1.818 + 0.0144

Vout = 1.8324v

Vout = 1.25 (1+ ) + [(IAdj) (R2)]R2R1

IAdj = 120uA

R1 TO BE IN THE 100R RANGE

R2IAdj

.= 120uA

0.58v

1

1

2

2

3

3

4

4

D D

C C

B B

A A

9 18

3V3 POWER SUPPLY

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\PSU_1084_3V3.SchDoc

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C5247uF 10VR23

91R 1%

R2256R 1%

3V3

3V3P

3.3V Output

C5110uF 10V

C53220uF 10V

C500.1uF 16V

1 2

NT6

3V35V0P

GND GND GND GND GND

IN3

OUT2

ADJ

1

U7REG1084

R1

I1

.= 22mA

Vout = 1.25 (1+ ) + [0.000,120 x 91]9156

Vout = (1.25 x 2.625) + 0.01092

Vout = 3.28125 + 0.01092

Vout = 3.292v

Vout = 1.25 (1+ ) + [(IAdj) (R2)]R2R1

IAdj = 120uA

R1 TO BE IN THE 100R RANGE

R2IAdj

.= 120uA

2.029v

1

1

2

2

3

3

4

4

D D

C C

B B

A A

10 18

2V5 POWER SUPPLY

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\PSU_1084_2V5.SchDoc

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C4847uF 10VR21

120R 1%

R20120R 1%

2V5

2V5P

2.5V Output

C4710uF 10V

C49220uF 10V

C460.1uF 16V

1 2

NT5

2V55V0P

GND GND GND GND GND

IN3

OUT2

ADJ

1

U6REG1084

R1

I1

.= 01mA

Vout = 1.25 (1+ ) + [0.000,120 x 120]120120

Vout = (1.25 x 2.00) + 0.0144

Vout = 2.500 + 0.0144

Vout = 2.5144v

Vout = 1.25 (1+ ) + [(IAdj) (R2)]R2R1

IAdj = 120uA

R1 TO BE IN THE 100R RANGE

R2IAdj

.= 120uA

1.258v

1

1

2

2

3

3

4

4

D D

C C

B B

A A

11 18

256K x8 SRAM MEMORY

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C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\SRAM-128Kx8x2.SchDoc

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A1430

A1221

A716

A615

A514

A413

A34

A23

A12

A01

IO06

IO17

IO210

GND9

VCC24

WE12

A1329

A817

A918

A1120

OE28

A1019

CS5

IO727

IO626

IO523

IO422

IO311

A1531

A1632

VCC8

GND25

U9IS63LV1024-15J

GND

3V3

C551uF 16V

C580.1uF 16V

C540.1uF 16V

3V3

GND

3V3

GND GND

3V3

SRAM_NWESRAM_NCS1

SRAM_A2SRAM_A3SRAM_A4SRAM_A5SRAM_A6SRAM_A7SRAM_A8SRAM_A9SRAM_A10SRAM_A11

SRAM_A1

SRAM_D0SRAM_D1SRAM_D2SRAM_D3SRAM_D4SRAM_D5SRAM_D6SRAM_D7

SRAM_A0

SRAM_A12SRAM_A13SRAM_A14SRAM_A15SRAM_A16

A1430

A1221

A716

A615

A514

A413

A34

A23

A12

A01

IO06

IO17

IO210

GND9

VCC24

WE12

A1329

A817

A918

A1120

OE28

A1019

CS5

IO727

IO626

IO523

IO422

IO311

A1531

A1632

VCC8

GND25

U10IS63LV1024-15J

GND

3V3

C571uF 16V

C590.1uF 16V

C561uF 16V

3V3

GND

3V3

GND GND

3V3

SRAM_NWESRAM_NCS0

SRAM_A2SRAM_A3SRAM_A4SRAM_A5SRAM_A6SRAM_A7SRAM_A8SRAM_A9SRAM_A10SRAM_A11

SRAM_A1

SRAM_D0SRAM_D1SRAM_D2SRAM_D3SRAM_D4SRAM_D5SRAM_D6SRAM_D7

SRAM_A0

SRAM_A12SRAM_A13SRAM_A14SRAM_A15SRAM_A16

SRAM_NOE

SRAM

BUS_A[16..0]D[7..0]

NWE

SRAM_NCS[1..0]NOE

SRAM

SRAM_A[16..0]SRAM_D[7..0]

SRAM_NWE

SRAM_NCS[1..0]

SRAM_NOE

SRAM_NOE

BANK 0 BANK 1

1

1

2

2

3

3

4

4

D D

C C

B B

A A

12 18

SPI SYSTEM BOOT FLASH

30/09/2009 9:39:03 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\M25Pxx SPI_BOOT.SchDoc

TITLE:

SIZE:

DATE:FILE:

VERSION:

SHEET OFTIME:

A4 CB500E CHKD: SRKH

C370.1uF 16V

GND

3V3

GND

S1

Q2

W3

VSS4

D5

C6

HOLD7

VCC8

U4M25P80-VMW6

3V3

DINDOUT

SCLK

BOOT_CS_N

BOOTPROM

BOOTPROM

BANK 2 = 3V3

XC3S250E

XC3S500E

1,353,728 BITS

2,270,208 BITS

8,192,000 BITS

(ID=0x13)

(75MHz)

Power up Time (POR):VCC(min) to S low: 10uS

1

1

2

2

3

3

4

4

D D

C C

B B

A A

13 18

SVGA 2BPP VIDEO PORT

30/09/2009 9:39:03 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\SVGA.SchDoc

TITLE:

SIZE:

DATE:FILE:

VERSION:

SHEET OFTIME:

A4 CB500E CHKD: SRKH

RED

GREEN

BLUE

5V0P

SCLSDA

GNDBLUE0

SDA

RED0RED1

HSYNCVSYNC

SCL

GREEN0GREEN1

BLUE1

SVGASVGA

SCLSDA

GREEN0GREEN1

BLUE0BLUE1

HSYNCVSYNC

RED0RED1

R44680R 1%

R45330R 1%

R46680R 1%

R47330R 1%

R48680R 1%

R49330R 1%

RED

RED0

RED1

GREEN

BLUE

GREEN0

GREEN1

BLUE0

BLUE1

HSYNCVSYNC

GND1

VSYNC2

HSYNC3

GND4

RED5

GND6

GREEN7

5VDC8

BLUE9

DDC DAT10

DDC CLK11

NC12

DETECT13

GND14

MH1MH2MH3MH4

J6Apple Mini-VGA

9 10

3 45 67 8

J7Header 2x4, RA

REDGREEN BLUE

HSYNC

VSYNC

SCLSDA

GND

GND

GND

GND

GND

Colour level

MSB (1) 330R

LSB (0) 680R

1

1

0.83V

1

0

0.56V

0

1

0.27V

0

0

0.00V

SVGA DB15 CONNECTORSVGAIO.SchDoc

(AUDIO - LEFT) (AUDIO - RIGHT)

(AUDIO - LEFT)

(AUDIO - RIGHT)

1

1

2

2

3

3

4

4

D D

C C

B B

A A

14 18

IDE INTERFACE

30/09/2009 9:39:03 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\IDE.SchDoc

TITLE:

SIZE:

DATE:FILE:

VERSION:

SHEET OFTIME:

A4 CB500E CHKD: SRKH

RESET- GNDD7 D8

D9D10D11D12D13D14D15D0

D1D2D3D4D5D6

KEYGND

GND

GND

GNDGNDGNDCSEL

IOCS16-PDIAG-A2CS1-

DASP-CS0-A0A1INTRQDMACK-IORDYDIOR-DIOW-DMARQ

INTRQ

CS1

A2

D3

INTRQ

IORD

IOWR

DASP

RESET

CSEL

IOCS16

DMARQ

DMACK

PDIAG

IORDY

CS0

A1A0

D4D5D6D7D8D9D10D11D12D13D14D15

D2D1D0

IDEIDE

DMARQ

IORDY

PBIO12

PBIO28

GND

GNDGNDGND

GND

GND

INTRQ

DMARQ

IORDY

PBIO27PBIO28

GND

135 6

42

79 10

8

1113 14

12

15 1617 181921 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

J42x20 IDC HEADER

PBIO44

PBIO43

PBIO42

PBIO41

PBIO40

PBIO5

PBIO6

PBIO7

PBIO8PBIO9

PBIO11PBIO12

PBIO13PBIO14PBIO15

PBIO16

PBIO17

PBIO18

PBIO19

PBIO20

PBIO21

PBIO22PBIO23

PBIO24

PBIO25

PBIO26

PBIO27

PBIO20PBIO25PBIO15PBIO14PBIO13PBIO16PBIO8PBIO9 PBIO7

PBIO10PBIO10PBIO5

PBIO11

PBIO17PBIO19PBIO26

PBIO6

PBIO21

PBIO41

PBIO23PBIO22

PBIO18PBIO42

PBIO24PBIO43

PBIO40PBIO44

IDE SIGNAL NAMES

1

1

2

2

3

3

4

4

D D

C C

B B

A A

15 18

SDIO INTERFACE

30/09/2009 9:39:03 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\SDIO.SchDoc

TITLE:

SIZE:

DATE:FILE:

VERSION:

SHEET OFTIME:

A4 CB500E CHKD: SRKH

GND3V3

GND

GNDGND

GND

R364K7 1%

3V3

R374K7 1%

3V3

R384K7 1%

3V3

R391K 1%

3V3

R404K7 1%

3V3

R414K7 1%

3V3

R424K7 1%

3V3

R434K7 1%

3V3

DAT0

CMDCLK

PROTECTDETECT

DAT1DAT2DAT3 SDIO

SDIO

SDIO_DETECTSDIO_PROTECT

PBIO47PBIO48PBIO49

DO/MISO

SPI

CS

DIN/MOSI

SCLK

EXTSPI_DINEXTSPI_SCLK

EXTSPI_DOUTD2D3CMD

CLK

D0D1

DET

WPEXTSPI_DOUTPBIO47

PBIO48PBIO49EXTSPI_DIN

EXTSPI_SCLKSDIO_DETECT

SDIO_PROTECT

C601uF 16V

C610.1uF 16V

3V3 3V3

GND GND

CD

WPCOM

2345678

19MH1

MH2

J5SDAMB-012

GND3V3

GNDGND

GNDGND

SDIO

N/A

N/A

DET

WP

1

1

2

2

3

3

4

4

D D

C C

B B

A A

16 18

14.31818MHZ SYS CLOCK

30/09/2009 9:39:03 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\SYSCLK.SchDoc

TITLE:

SIZE:

DATE:FILE:

VERSION:

SHEET OFTIME:

A4 CB500E CHKD: SRKH

SYSCLKSYSCLK

SYSCLK

C620.1uF 16V

R5056R 1%

GND

GND

3V3 3V3

EN1

NC2

GND3

OUT4

NC5

VCC6

X1FXO-HC735-14.31818MHZ

SYSCLK[14.31818MHZ]

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

17 18

CARTE BLANCHE FPGA

30/09/2009 9:39:03 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\XC3S500E-4PQ208.SchDoc

TITLE:

SIZE:

DATE:FILE:

VERSION:

SHEET OFTIME:

A2 CB500E CHKD: SRKH

BANK 0

IO_L16N_0/HSWAP206

IO_L16P_0205

IO_L15N_0203

IO_L15P_0202

IO_L14N_0/VREF_0200

IO_L14P_0199

IO_L13N_0197

IO_L13P_0196

IO_L12N_0/VREF_0193

IO_L12P_0192

IO_L11N_0190

IO_L11P_0189

IO187

IO_L10N_0/GCLK11186

IO_L10P_0/GCLK10185

IO_L08N_0/GCLK7181

IO_L08P_0/GCLK6180

IO/VREF_0179

IO_L07N_0/GCLK5178

IO_L07P_0/GCLK4177

IO_L05N_0172

IO_L05P_0171

IO_L04N_0/VREF_0168

IO_L04P_0167

IO_L03N_0165

IO_L03P_0164

IO_L02N_0/VREF_0163

IO_L02P_0162

IO_L01N_0161

IO_L01P_0160

U3AXC3S250E-4PQ208C

BANK 1

IO_L16N_1/LDC2153

IO_L16P_1/LDC1152

IO_L15N_1/LDC0151

IO_L15P_1/HDC150

IO_L14N_1147

IO_L14P_1146

IO_L13N_1145

IO_L13P_1144

IO_L12N_1/A0140

IO_L12P_1139

IO_L11N_1/A1138

IO_L11P_1/A2137

IO_L10N_1/A3/RHCLK7135

IO_L10P_1/A4/RHCLK6134

IO_L09N_1/A5/RHCLK5133

IO_L09P_1/A6/RHCLK4132

IO_L08N_1/A7/RHCLK3129

IO_L08P_1/A8/RHCLK2128

IO_L07N_1/A9/RHCLK1127

IO_L07P_1/A10/RHCLK0126

IO_L06N_1/VREF_1123

IO_L06P_1122

IO_L05N_1/A11120

IO_L05P_1/A12119

IO_L04N_1116

IO_L04P_1115

IO_L03N_1/VREF_1113

IO_L03P_1112

IO_L02N_1/A13109

IO_L02P_1/A14108

IO_L01N_1/A15107

IO_L01P_1/A16106

U3BXC3S250E-4PQ208C

BANK 2

IO_L17N_2/CCLK103

IO_L17P_2/VS0/A17102

IO_L16N_2/VS1/A18100

IO_L16P_2/VS2/A1999

IO/VREF_298

IO_L15N_2/A2097

IO_L15P_2/A2196

IO_L14N_2/A2294

IO_L14P_2/A2393

IO_L13N_290

IO_L13P_289

IO_L12N_2/DIN/D087

IO_L12P_2/M086

IO/M184

IO_L11N_2/D1/GCLK383

IO_L11P_2/D2/GCLK282

IO_L09N_2/D3/GCLK1578

IO_L09P_2/D4/GCLK1477

IO/D576

IO_L08N_2/D6/GCLK1375

IO_L08P_2/D7/GCLK1274

IO_L06N_269

IO_L06P_268

IO_L05N_265

IO_L05P_264

IO_L04N_263

IO_L04P_262

IO_L03N_2/MOSI/CSI_B61

IO_L03P_2/DOUT/BUSY60

IO_L01N_2/INIT_B56

IO_L01P_2/CSO_B55

U3CXC3S250E-4PQ208C

BANK 3

IO_L16N_350

IO_L16P_349

IO_L15N_348

IO_L15P_347

IO/VREF_345

IO_L14N_342

IO_L14P_341

IO_L13N_340

IO_L13P_339

IO_L12N_336

IO_L12P_335

IO_L11N_334

IO_L11P_333

IO_L10N_3/LHCLK731

IO_L10P_3/LHCLK630

IO_L09N_3/LHCLK529

IO_L09P_3/LHCLK428

IO_L08N_3/LHCLK325

IO_L08P_3/LHCLK224

IO_L07N_3/LHCLK123

IO_L07P_3/LHCLK022

IO_L06N_319

IO_L06P_318

IO_L05N_316

IO_L05P_315

IO_L04N_312

IO_L04P_311

IO_L03N_39

IO_L03P_38

IO_L02N_3/VREF_35

IO_L02P_34

IO_L01N_33

IO_L01P_32

U3DXC3S250E-4PQ208C

IP204

IP159

IP169

IP_L06P_0174

IP_L06N_0175

IP_L09P_0/GCLK8183

IP_L09N_0/GCLK9184

IP194

IP110

IP118

IP124

IP130

IP/VREF_1136

IP148

IP154

IP142

IP54

IP_L02P_257

IP_L02N_258

IP_L07P_271

IP_L07N_2/VREF_272

IP_L10P_2/RDWR_B/GCLK080

IP_L10N_2/M2/GCLK181

IP91

IP101

IP6

IP14

IP/VREF_320

IP26

IP32

IP43

IP51

U3EXC3S250E-4PQ208C

DONE104

PROG_B1

TCK158

TDI207

TDO157

TMS155

U3FXC3S250E-4PQ208C

GND

LED50603 LED GREEN

LOADED

APPLEBUS

-BUS-DEV_SEL

BUS-PHASE0

BUS-USER1

BUS-PHASE1BUS-Q3

BUS-7MBUS-3M58

BUS-INH

BUS-RESET

BUS-IRQ

BUS-NMIBUS-DMA

BUS-RDY

BUS-IOSTROBE

BUS-SYNC

BUS-R/W

BUS-A15BUS-A14BUS-A13BUS-A12BUS-A11BUS-A10BUS-A9BUS-A8BUS-A7BUS-A6BUS-A5BUS-A4BUS-A3BUS-A2BUS-A1BUS-A0

-BUS-IO_SEL

BUS-D0BUS-D1BUS-D2BUS-D3BUS-D4BUS-D5BUS-D6BUS-D7

BUS-DMAINBUS-INTIN

BUS-DMAOUTBUS-INTOUT

AIISLOT

SYS_JTAG

SCLSDA

I2CI2C

CLK_EXT2

CLK_EXT0

CLK_EXT1

CLK_EN

CLOCKSCLOCKS

EXTSPI_DIN

EXTSPI_CS_N0

EXTSPI_DOUT

EXTSPI_SCLK

ONE_WIRE_IDEXTSPI_CS_N1

ONE_WIRE_DB_PB

SPI+IDSPI+ID

012345678910111213141516171819202122232425262728293031323334353637383940414243444546474849

NB2PBIONB2PBIO

PBIO0PBIO1PBIO2PBIO3PBIO4PBIO5PBIO6PBIO7PBIO8PBIO9PBIO10PBIO11PBIO12PBIO13PBIO14PBIO15PBIO16PBIO17PBIO18PBIO19PBIO20PBIO21PBIO22PBIO23PBIO24PBIO25PBIO26PBIO27PBIO28PBIO29PBIO30PBIO31PBIO32PBIO33PBIO34PBIO35PBIO36PBIO37PBIO38PBIO39PBIO40PBIO41PBIO42PBIO43PBIO44PBIO45PBIO46PBIO47PBIO48PBIO49

SCLSDA

EXTSPI_CS_N0

EXTSPI_CS_N1

CLK_ENCLK_EXT0

CLK_EXT2CLK_EXT1

ONE_WIRE_ID

TCK_HARD

TDO_HARDTDI_HARD

TMS_SOFT

TMS_HARD

TDI_SOFT

TDO_SOFT

TCK_HARDTDO_HARDTDI_HARD

TMS_HARD

BUS_D4

BUS_A10

BUS_D3

BUS_A6

BUS_D2

BUS_R_W

BUS_D1

BUS_A1BUS_A0

BUS_A9

BUS_A2BUS_A3

BUS_A8

BUS_A4

BUS_D7BUS_D6

BUS_D0

BUS_A7

BUS_RESET

BUS_A11

BUS_A5

BUS_D5

BUS_7M

BUS_A12BUS_A13BUS_A14BUS_A15

BUS_RDYBUS_NMI

BUS_IRQ

BUS_INH

BUS_3M58BUS_Q3

BUS_PHASE0BUS_PHASE1

BUS_USER1BUS_SYNC

BUS_DMA

EXTSPI_DIN

BUS_IOSTROBE

N_BUS_IO_SEL

N_BUS_DEV_SEL

3V3VREF

LOADED

R340R 1%

M0 = H

M2 = LEXTERNAL PULL DOWN

R35180R 1%

2V5

H = PROGRAMMED (LOADED)

H = RELOAD DISABLED

EXTERNAL PULL DOWN

INTERNAL PULL UP

RESISTOR FOR 3.3V OPERATIONTDI, TDO, TCK AND TMS ALL REQUIRE SERIES

INTERNAL PULL UPLOW BY DEFAULT

H = PROGRAMMED

R30 56R 1%R31 56R 1%R32 56R 1%R33 56R 1%

EXTSPI_SCLK

BUS_7M

EXTSPI_DOUT

TCK_SOFT

BANK 1 = 3V3

BANK 2 = 3V3

BANK 3 = 3V3

BANK 0 = 3V3

TCK_SOFT

M0, M1, M2SET EXTERNAL SPI MASTER

BOOT FROM EXTERNAL SPI FLASH

TMSTDO

TDITCK

JTAG

TMSTDOTDITCK

JTAG

HARD

SOFT

VREF

SYS_JTAG

INPUT ONLY

BANK 0, 1, 2 & 3 = 3V3

[14.31818MHZ]

DCM X1Y0 INPUT

DCM X1Y1 INPUT

GCLK4 - PBIO21 - EXT CLOCK

DINDOUT

SCLK

BOOT_CS_NBOOTPROMBOOTPROM

PROM_CSBUS_INTINBUS_DMAINBUS_DMAOUTBUS_INTOUT

SYSCLK

SRAM

BUS_A[16..0]D[7..0]

NWE

SRAM_NCS[1..0]NOE

SRAM

SRAM_A[16..0]SRAM_D[7..0]

SRAM_NWE

SRAM_NCS[1..0]SRAM_NOE

GCLK0 - 7.159MHZ

DCM X0Y1 INPUT

DCM X0Y0 INPUT

GCLK15 - PBIO25 - EXT CLOCK

GCLK 10 - PBIO26 - EXT CLOCK

GND

EXTSPI_DINEXTSPI_SCLK

PROM_CS

ONE_WIRE_ID

EXTSPI_DOUT

M1 = L

R27 560R 1%GND

[M0]

R24560R 1%

GND

BY HSWAP PRIOR TOCONFIGUARATION

M0 = HEXTERNAL PULL UP

[M1]

HSWAP = LEXTERNAL PULL DOWN

[HSWAP]

TO ENABLE PULL UP RESISTORSON ALL IO

VSx = HINTERNAL PULL UP BY

[VS0, VS1, VS2]

HSWAP PRIOR TO CONFIGVS = FAST READ (0x0B)

[7.159MHZ]

SRAM128KB x8 x 2 BANKS (0 & 1)

IS63LV1024/IDT71V124 - 15nS

SERIAL PROM (FPGA BOOT)1MB x8 (8Mb)

M25P80 - 75MHz

SRAM_A0

N_BUS_DEV_SELBUS_PHASE0

BUS_Q3BUS_3M58

BUS_A13BUS_A14BUS_A15BUS_R_W

BUS_IOSTROBEBUS_SYNC

BUS_IRQ

SRAM_A5

PBIO6

GCLK0 GCLK1 GCLK3GCLK2

GCLK4 GCLK5 GCLK6 GCLK7

GCLK8 GCLK9 GCLK10 GCLK11

GCLK 8 - 14.31818MHZ

GCLK12 GCLK13 GCLK14 GCLK15

R29

47K 1%2V5

VCCAUX = 2V5

INTERNAL XC3SxxxE RESISTANCE VALUESRPU - PULL UP RESISTOR (VCCO = 3V3) = 10K8 OHMS

RPD - PULL DOWN RESISTOR (VCCO = 3V3) = 34K5 OHMS

HSWAPHSWAP HIGH = INT PULLUPS OFF

HSWAP LOW= INT PULLUPS ON

(INT PULLED UP VIA FIXED RESISTOR)

[LO= 0.11V]

XC3S250E XC3S500E

(UG332-P47)

(UG332-P34)

(UG332-P61)

(UG332-P100)(DS312-P79)

(DS312-P72)

(XAPP453-P13)

NOTE:

DOUT OSCILLATESDURING CONFIG.

PINS USED BY PB04

(UG332-P227)SPI BOOT THREE TIMESFPGA WILL ATTEMPT

INIT_B ASSERTSDURING CONFIG.

GCLK2 - PBIO24 - EXT CLOCK

OC

(UG332-P98)

(UG332-P98)

CS1

A2

D3

INTRQ

IORD

IOWR

DASP

RESET

CSEL

IOCS16

DMARQ

DMACK

PDIAG

IORDY

CS0

A1A0

D4D5D6D7D8D9D10D11D12D13D14D15

D2D1D0

IDEIDE

DAT0

CMDCLK

PROTECTDETECT

DAT1DAT2DAT3 SDIO

SDIO

SVGA

SCLSDA

SDIO_DETECTSDIO_PROTECT

PBIO45PBIO46

PBIO47PBIO48PBIO49

DO/MISO

SPI

CS

DIN/MOSI

SCLK

EXTSPI_DINEXTSPI_SCLK

EXTSPI_DOUT

EXTSPI_DINEXTSPI_SCLK

EXTSPI_DOUT

CLK_EXT2

INTRQ

DMARQ

IORDY

PBIO44

PBIO43

PBIO42

PBIO41

PBIO40

PBIO5

PBIO6

PBIO7

PBIO8PBIO9

PBIO10

PBIO11PBIO12

PBIO13PBIO14PBIO15

PBIO16

PBIO17

PBIO18

PBIO19

PBIO20

PBIO21

PBIO22PBIO23

PBIO24

PBIO25

PBIO26

PBIO27PBIO28

SYSCLKSYSCLKSYSCLK

SYSCLK

IORDY

BUS_PHASE1

PBIO38

BUS_USER1

PBIO32

BUS_A10BUS_A11BUS_A12BUS_DMABUS_RDYBUS_INH

SDIO_DETECT

BUS_NMIBUS_INTOUTBUS_DMAOUT

BUS_INTINBUS_DMAIN

EXTSPI_CS_N0EXTSPI_CS_N1

SRAM_A10SRAM_A11

SRAM_D4

SDIO_PROTECT

SRAM_NWE

CLK_EXT2

PBIO41

SRAM_A3SRAM_A2SRAM_A1

CLK_ENSRAM_D7CLK_EXT1

SRAM_A13SRAM_A14SRAM_A16SRAM_A15PBIO19PBIO0PBIO1PBIO2PBIO3PBIO8PBIO4PBIO7PBIO5

PBIO12

PBIO13PBIO14PBIO15PBIO16

PBIO18

INTRQ

PBIO21

PBIO23

PBIO26

PBIO27PBIO28PBIO29PBIO30PBIO31

DMARQ

N_BUS_IO_SEL

[M2]

3V3[M0]R28 1K 1%

R25 1K 1%

3V3R26 1K 1%

3V3

[14.31818MHZ]

PBIO44BUS_D0BUS_A0BUS_D1BUS_A1

BUS_D2

BUS_A2

BUS_D3

PBIO39

BUS_A3

BUS_D4

BUS_A4

BUS_D5

BUS_A5

BUS_D6

BUS_A6

BUS_D7

BUS_A7

BUS_A8

PBIO37

BUS_A9

BUS_RESETPBIO47

PBIO48

SRAM_A6

PBIO25PBIO24

SRAM_A12

SRAM_D3PBIO20

PBIO17SRAM_D6PBIO40

PBIO45

PBIO46

PBIO42SDASCL

PBIO43TDO_SOFTPBIO10SRAM_D0SRAM_NCS1SRAM_D5

SRAM_NOE

PBIO9

TMS_SOFT

TDI_SOFT

PBIO11SRAM_NCS0

SRAM_D1

SRAM_D2

PBIO22SRAM_A4

CLK_EXT0

SRAM_A9

SRAM_A8SRAM_A7

PBIO33ONE_WIRE_ID

PBIO34PBIO35PBIO36

GCLK5 - PBIO22 - EXT CLOCKGCLK6 - PBIO23 - EXT CLOCKGCLK7 - CLK_EXT0 - EXT CLOCK

GLOBAL CLOCK ALLOCATIONS

PBIO0PBIO1

PBIO2PBIO3

PBIO4

BLUE0

SDA

RED0RED1

HSYNCVSYNC

SCL

GREEN0GREEN1

BLUE1

SVGA

SDIO CS

SDIO DAT2

SDIO DAT1

VGA VSYNC

VGA HSYNC

VGA GREEN0

VGA GREEN1

VGA BLUE0

VGA BLUE1

VGA RED1

VGA RED0

TURN OFF OTHERSPI DEVICES DURING

CONFIG

[PULLED UP AT INTERFACE]

PBIO49

3V3

GNDBUS_ENABLE

LOADED

ENABLEENABLEENABLE

BUS_ENABLE

NC1

A2

GND3

Y4

VCC5

U11SN74LVC1G04DBV

APPLE II BUSDISABLED DURINGFPGA CONFIG

KFEST4.7uF 16V

GND

(AUDIO - LEFT)

(AUDIO - RIGHT)

(AUDIO - LEFT)

(AUDIO - RIGHT)

(AUDIO - LEFT)

(AUDIO - RIGHT)

Device XC3S250ESystem Gates 250KLogic Cells 5,508Dedicated Multipliers 12Common logic Blocks 612Block RAM Bits 216k (27.6KB)Distributed RAM Bits 38k (4.8KB)User IO 158 (32 Input Only)Min-Max DCM Input 5MHz-300MHzDCMs 4

Device XC3S500ESystem Gates 500KLogic Cells 10,476Dedicated Multipliers 20Common logic Blocks 1,164Block RAM Bits 360k (45KB)Distributed RAM Bits 73k (9.1KB)User IO 158 (32 Input Only)Min-Max DCM Input 5MHz-300MHzDCMs 4

1

1

2

2

3

3

4

4

D D

C C

B B

A A

18 18

AII SVGA MOUNTING BOARD

30/09/2009 9:39:04 PM

C:\AppleLogic\CarteBlanche\CB1_TEMPLATE\SVGAIO.SchDoc

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A4 CB500E CHKD: SRKH

1 23 45 67 89 10

J810W MALE HEADER

SVGA

RD

GR

BL

4

G4

G1

G2

G3

9

G5

11

SDA

HS

VS

SCL

J9HDR-15S11G1R

INTERFACE

VGND

NC1

NC2NC3

SVGA_REDSVGA_GREEN SVGA_BLUE

SVGA_HSYNC

SVGA_VSYNC

SVGA_SCLSVGA_SDA

VGND

SVGA_GREEN

SVGA_VSYNC

SVGA_SDA

SVGA_RED

SVGA_BLUE

SVGA_SCL

SVGA_HSYNC

VGND

(AUDIO - LEFT) (AUDIO - RIGHT)

(AUDIO - LEFT)

(AUDIO - RIGHT)