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Vol.:(0123456789) 1 3 Journal of Materials Science: Materials in Electronics (2019) 30:2389–2402 https://doi.org/10.1007/s10854-018-0512-0 CBRAM devices based on a nanotube chalcogenide glass structure M. R. Latif 1  · P. H. Davis 2  · W. B. Knowton 1,2  · M. Mitkova 1 Received: 15 October 2018 / Accepted: 4 December 2018 / Published online: 15 December 2018 © Springer Science+Business Media, LLC, part of Springer Nature 2018 Abstract CBRAM nano-ionic devices are emerging as a competitive technology solution for transistor free memory, offering low power consumption, fast switching, and non-volatility. However, due to the process by which switching is achieved in these devices, namely stochastic growth of a conductive filament bridging the two electrodes within the amorphous material between the electrodes, they suffer from reliability problems. In this work we present devices built with a nanotube struc- ture of chalcogenide glasses to confine the growing conductive bridge. This structure is found to greatly improve device reliability and switching speed. Furthermore, the technology does not involve additional steps, is cost-effective, and is fully compatible with conventional CMOS technology. We have verified the process of conductive bridge growth with scanning electron microscopy and atom force microscopy and characterized the devices in terms of their current–voltage character- istics, memory window, endurance, and retention, all of which show excellent parameters. Their performance stability is also demonstrated at 130 °C, while multilevel switching is established by application of a variety of compliance currents. 1 Introduction In the last few decades the semiconductor industry has seen tremendous growth, paving the way for better, faster, more cost effective and energy efficient products, driven by intensive down-scaling of the devices based on Moore’s Law [1]. However, continued scaling over the years is now fac- ing a dilemma as it has arrived at the point where device physics poses severe scaling challenges for future devices [2]. Memory is one of the essential components in today’s electronics market. All modern electronic products have memory either embedded into the device itself or attached externally. In addition, advancements in personal electronic devices have resulted in a dramatic increase in the demand for memory, more specifically non-volatile memory. Based on the fundamental operation mechanism underpinning the Flash cell, there are several limitations from both applica- tion and scaling perspectives. On the application side, it is impossible to achieve properties like fast programming, quick access, and high memory density concurrently with random access. Scaling is another fundamental challenge to Flash technology for future nonvolatile memory applica- tions. Even though NAND Flash has high density based on a new 3D architecture [3], it faces many difficulties to continue scaling down. It is generally believed that the feature size of a traditional Flash cell is difficult to scale down below 20 nm [4]. The demand for new quality memory solutions has spurred the development of new memristive resistance change devices. Accordingly, researchers are working on a variety of potential solutions applying different materials and tech- nologies. Perhaps the most mature among these potential replacements for Flash is phase change technology, which was a subject of intensive investigations for half a century [5]. However, phase change does not fulfill the requirements for high density memory formation because of its high form- ing and set/reset voltages, which require big transistors to supply the necessary voltage, thus leading to formation of large chips. Additionally, thermal disturbance due to device operation relying on Joule heating prevents narrow adjacent cells from performing, or requires a specific scheme for ther- mal power dissipation and very thermally stable materials. Even though new technological developments try to respond to the characteristic issues with these devices [6] many of their specific problems remain unresolved. A serious * M. Mitkova [email protected] 1 Department of Electrical and Computer Engineering, Boise State University, 1910 University Dr., Boise, ID 83725-2075, USA 2 Micron School of Materials Science and Engineering, Boise State University, 1910 University Dr., Boise, ID 83725-2090, USA
Transcript
Page 1: CBRAM devices based on a nanotube chalcogenide glass …The CBRAM devices were fabricated utilizing masks with multiple vias dimensions. The electrode materials were tung-sten and

Vol.:(0123456789)1 3

Journal of Materials Science: Materials in Electronics (2019) 30:2389–2402 https://doi.org/10.1007/s10854-018-0512-0

CBRAM devices based on a nanotube chalcogenide glass structure

M. R. Latif1 · P. H. Davis2 · W. B. Knowton1,2 · M. Mitkova1

Received: 15 October 2018 / Accepted: 4 December 2018 / Published online: 15 December 2018 © Springer Science+Business Media, LLC, part of Springer Nature 2018

AbstractCBRAM nano-ionic devices are emerging as a competitive technology solution for transistor free memory, offering low power consumption, fast switching, and non-volatility. However, due to the process by which switching is achieved in these devices, namely stochastic growth of a conductive filament bridging the two electrodes within the amorphous material between the electrodes, they suffer from reliability problems. In this work we present devices built with a nanotube struc-ture of chalcogenide glasses to confine the growing conductive bridge. This structure is found to greatly improve device reliability and switching speed. Furthermore, the technology does not involve additional steps, is cost-effective, and is fully compatible with conventional CMOS technology. We have verified the process of conductive bridge growth with scanning electron microscopy and atom force microscopy and characterized the devices in terms of their current–voltage character-istics, memory window, endurance, and retention, all of which show excellent parameters. Their performance stability is also demonstrated at 130 °C, while multilevel switching is established by application of a variety of compliance currents.

1 Introduction

In the last few decades the semiconductor industry has seen tremendous growth, paving the way for better, faster, more cost effective and energy efficient products, driven by intensive down-scaling of the devices based on Moore’s Law [1]. However, continued scaling over the years is now fac-ing a dilemma as it has arrived at the point where device physics poses severe scaling challenges for future devices [2]. Memory is one of the essential components in today’s electronics market. All modern electronic products have memory either embedded into the device itself or attached externally. In addition, advancements in personal electronic devices have resulted in a dramatic increase in the demand for memory, more specifically non-volatile memory. Based on the fundamental operation mechanism underpinning the Flash cell, there are several limitations from both applica-tion and scaling perspectives. On the application side, it is

impossible to achieve properties like fast programming, quick access, and high memory density concurrently with random access. Scaling is another fundamental challenge to Flash technology for future nonvolatile memory applica-tions. Even though NAND Flash has high density based on a new 3D architecture [3], it faces many difficulties to continue scaling down. It is generally believed that the feature size of a traditional Flash cell is difficult to scale down below 20 nm [4]. The demand for new quality memory solutions has spurred the development of new memristive resistance change devices.

Accordingly, researchers are working on a variety of potential solutions applying different materials and tech-nologies. Perhaps the most mature among these potential replacements for Flash is phase change technology, which was a subject of intensive investigations for half a century [5]. However, phase change does not fulfill the requirements for high density memory formation because of its high form-ing and set/reset voltages, which require big transistors to supply the necessary voltage, thus leading to formation of large chips. Additionally, thermal disturbance due to device operation relying on Joule heating prevents narrow adjacent cells from performing, or requires a specific scheme for ther-mal power dissipation and very thermally stable materials. Even though new technological developments try to respond to the characteristic issues with these devices [6] many of their specific problems remain unresolved. A serious

* M. Mitkova [email protected]

1 Department of Electrical and Computer Engineering, Boise State University, 1910 University Dr., Boise, ID 83725-2075, USA

2 Micron School of Materials Science and Engineering, Boise State University, 1910 University Dr., Boise, ID 83725-2090, USA

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competitor to phase change technology is ReRAM based on transition metal oxides (TMO). Although ReRAM offers cheap technology—it requires only two additional patterning masks for embedding of a ReRAM layer—ReRAM suffers from a small memory window (on/off ratio) and compulsory performance instability native to its operational nature based on alignment of anion vacancies, whose dynamics are quite stochastic [7, 8]. This instability of the vacancies charge and the high power consumption of ReRAM prevent the mass application of these devices.

In recent years, interest in the emerging Conductive Bridge Random Access Memory (CBRAM), based on Pro-grammable Metallization Cell (PMC) technology platform [9], has grown substantially, because CBRAM does not suffer from the majority of the drawbacks of the devices discussed above. The CBRAM structure consists of one electrochemically active electrode (anode) metal such as Ag or Cu, with another electrode (cathode) made of an elec-trochemically inert metal, for example, Pt, W, Ni, etc., and a thin film of solid electrolyte (or a dielectric) sandwiched between the two electrodes [10]. The electrochemically active electrode serves as a source of metal ions, which after realization of the electrochemical process allows formation of a conductive bridge filament. Figure 1 illustrates the prin-ciple of operation of a redox conductive bridge cell [11] in conjunction with a current–voltage (IV) switching cycle using a quasi-static triangular voltage source with copper (Cu) as an oxidizable electrode and platinum (Pt) as an inert electrode. Depending on the bias applied to the device, the Cu bridge forms or dissolves between the two electrodes. These devices have impressive switching rate below 10−4 s at voltage of 1.2 volts [12], which is commensurable with the fastest ever reported phase change devices [13] switching for about 20 ns at much higher voltage.

It is obvious that stability of the bridge growth and its organization within the solid state matrix between the two electrodes is of key importance for CBRAM device

reliability. Since in the general case the soild state elecro-lyte or other material between the electrodes is amorphous, bridge formation becomes stochastic, resulting in three dimensional random growth with multiple branches which do not conduct during the ON state of the device. A model has been proposed to suggest the preferential path for ionic conduction [14]. It however shows the need for total organi-zation of the diffusion process and matrix in which it devel-ops in order to make it uniform and reliable. This is where the major challenge in improving the reliability of these devices lies. Lack of confinement of the filament connect-ing the two electrodes is the main source for occurrence of threshold voltage drift, lack of stability on the on/off states, and set voltage variation.

Choi et al. [15] suggested recently organizing channels for one dimensional confinement of conductive Ag fila-ments into dislocations in epitaxial SiGe and enhanced ion transport in the confined path via defect selective etching to open up the dislocation pipes. This is a very interest-ing idea, which the authors realized with sophisticated and high quality experimental work. However, their suggested solution suffers from several disadvantages regarding the application for CBRAM devices. First, it is not cost effec-tive. Second, the epitaxial growth requires high tempera-ture, which is incompatible with CMOS fabrication, and third, for now the reported devices characteristics are not confirmed for memristors down to nanoscale [16]. In addi-tion, the suggested devices have relatively high threshold voltage between 2 and 4 Volts and a quite small memory window with an on/off current ratio on the order of 1 × 102, which the authors try to increase through defect—selective etching. However, due to excessive dislocation widening instability in the on/off current states, and variations in the set voltage occur [17]. While there is expectation that these devices will demonstrate very good endurance and retention due to the filament confinement, this is not proved in the referenced works [15, 17] since more than 100 switching

Fig. 1 Operation principles of cation-based memory cells with a Cu oxidizable electrode and Pt inert electrode. a The initial/OFF state. b The oxidation of metallic Cu to Cu+ ions and the growth of a Cu

filament in the “program” or “set” operation. c The ON state. d The reverse bias removal of the filament in the “erase” or “reset” [11]

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cycles are never presented and the retention, as discussed by the authors in the supplementary material is poor [17].

Here we attempt a different strategy to overcome the fundamental challenges posed by the filament growth in CBRAM devices. We consider devices based on using a chalcogenide film as the medium between the two electrodes with a nano-tube structure [18] in which the growth of the bridge is confined between columns grown into the chal-cogenide glass film. Essential details about the growth of such structure and properties of deposited films are given in [18]. This nanotube structure is predicted to eliminate the stochastic character of the filament growth and organize it into well defined channels. The device structure is chracter-ized with electron and atomic force microscopy methods. Insights into the filament growth and Ag dendrites’ growth throughout the nanotubes are shown. Presented also are the switching characeristics, retention, and endurance of the fabricated devices under diffeent experimental conditions, which gives opprtunity for optimization of the fabrication process as a function of the nanotubes’ organization.

2 Experimental methods

The CBRAM devices were fabricated utilizing masks with multiple vias dimensions. The electrode materials were tung-sten and silver. The chalcogenide films were not photodif-fused with Ag since it is known that the columnar structure of chalcogenide glasses is very sensitive towards irradiation wih light [19, 20].

Scanning electron microsocopy (SEM) was used to verify the presence of nanotube type structures within the chalco-genide films in the devices. Devies were cut using a focused ion beam (FIB) and the structures studied with a Hitachi field emission SEM (FESEM) equipped with an electron backscatter detector and Quartz imaging capture software. The cross sectional area was coated with gold to avoid charg-ing of the highly resistive samples. Compositional analysis of the films was performed by energy dispersive spectros-copy (EDS). EDS results were acquired by averaging data over five points on each sample using a Hitachi S-3400N EDS system.

To illustrate Ag diffusion and filament formation with no multi-branching through the pathways provided by the chalcogenide nanotube structure, an experimental setup (Fig. 2) for imaging the cross sectional areas of the sam-ples (Fig. 3) via atomic force microscopy (AFM) was engi-neered. A Bruker Dimension Icon AFM was used in two proprietary characterization modes, Peak Force Tunneling AFM (PF-TUNA) and Peak Force Kelvin Probe AFM (PF-KPFM). Both AFM methods provided insight into the filament growth through the column structure by permit-ting nanoscale electrical characterization of the fabricated

devices. PF-TUNA was used to map sample conductivity on the nanoscale and record the Ag dendrites’ growth through the columnar structure, while PF-KPFM enabled imaging of the surface potential of the topological layers, allowing char-acterization of the Ag distribution within the chalcogenide nanotube structure. These nanoelectrical characterization techniques provided near atomic scale information on the fabricated devices, suggesting that these devices are scalable to a near atomic level.

PF-TUNA was used to develop a cross-sectional conduc-tivity map of the fabricated column structured active layered devices. PF-TUNA measurements were based on Bruker’s proprietary Peak Force (PF) tapping method, which is capa-ble of acquiring simultaneous nanoelectrical and mechanical measurements [21]. In PF tapping, the probe interacts with the sample intermittently (1 kHz here), thereby avoiding

W (100nm)SiO2 (250nm)

ChG (500nm to 1µm)

Ag Electrode(100nm)

Si SubstrateAFM tip

25nm

Sample Chuck

Ag paste

Fig. 2 Experimental setup for imaging the growth of the Ag nanowire conductive path through the chalcogenide columnar structure in the active layer of the CBRAM devices

Fig. 3 Optical image of the cleaved multilayer sample used for PF-TUNA and PF-KPFM imaging

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lateral forces during measurements and imaging, and the feedback loop controls the maximum tip-sample force for each cycle. The sequence of the periodically modulated probe interacting with the sample surface is illustrated in Fig. 4, wherein the Z position (top trace) shows the cantile-ver position throughout one PF cycle as a function of time. The force measured by the probe when approaching the sam-ple surface and during the withdrawal phase are represented in the middle trace of the figure, while the current passing through the sample due to application of proper voltage bias is represented as the bottom trace in Fig. 4. Prior to imag-ing, the samples were cleaved using the standard cleaving

method, with extra precaution taken to ensure the resulting surface was as smooth as possible (see Fig. 3).

Concurrent with the topographical and nanomechanical measurements, the sample conductivity was monitored as a function of applied sample bias (0 to − 2 V in 100 mV incre-ments). Biasing of the sample was accomplished by estab-lishing a direct electrical connection between the sample chuck and the tungsten electrode using silver paste—Fig. 2. To image the silver filament growth through the columnar structures, the chuck was biased to a lower potential relative to the tip.

The devices were tested in dual sweep mode with various voltage step sizes ranging from 2 to 10 mV and with differ-ent compliance current settings. Typically, the integration time was set to MEDIUM with a hold time of 3 s between subsequent measurements. The double sweep voltage covers the entire device operation characteristics from write opera-tion to erase operation. The IV measurements were carried out at room temperature, as well as higher temperatures (130 °C) to test the device stability. To protect devices, a compliance current was applied.

3 Results and discussion

3.1 Devices’ nanotube structure

SEM cross-sectional imaging of the devices confirmed their nanotube structure, confined by column grown through-out the film, as shown in Fig. 5 for a representative device based on a chalcogenide glass with the nominal composition Ge40Se60 (EDS results, Fig. 5b, confirmed the glass contains 40 ± 0.5 at.% Ge and 60 ± 0.5 at.% Se).

A

B

C

D

EForce

Z posion

Approach

withdraw

Current

Time

Fig. 4 Plots of probe (Z position), force, and current as a function of time during one PF-TUNA cycle. [21]

Fig. 5 Representative SEM image of a typical device cross section (a) and corresponding composition as determined via EDS (b)

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Figure 6 presents the growth of the Ag filament (dark brown color) through the nanotubes between the chalco-genide columns for the studied Ge20Se80, Ge30Se70, and Ge40Se60 devices with obliquely deposited active films (α corresponds to the deposition angle) under conditions of a -2 V bias applied to the sample relative to the AFM probe tip. A close observation of the films reveals the formation of the filament with no multi-branching evident within the filament. A significant increase in the current was observed

due to the conduction path available between the W and Ag electrodes as shown in Fig. 6a–c (ii–iv and vi–viii). Rela-tively large numbers of filaments are observed in the cross sectional image for all the compositions in Fig. 6. Since peak current is recorded when the tip is in contact with surface, it measured the highest current flowing through the devices, as shown in Fig. 6a–c (vii). In contrast, as the TUNA cur-rent measures the average current during one complete force curve cycle, including the idle period when the tip is not in

Fig. 6 PF-TUNA scans obtained with the stage/sample biased at − 0.5 V relative to the probe and a Peak Force setpoint of 10 nN for a Ge20Se80 with α = 70°, b Ge30Se70 with α = 45°, c Ge40Se60 with α = 30°, where (i–iv) show the top scan view and the filament growth

through the nanotubes in the columnar structure and (v) the top view image rotated by 90° with (vi–viii) the side scan view of the cross sectional area and filament growth through the voids in the columnar structure with corresponding current scale

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contact with the surface, it displays the least current reading as indicated on the current scale in Fig. 6a–c (vi).

Following formation of the intercalated silver nanowires in the nanotubes, reversal of the biasing should lead to dis-solution of the grown filament. To validate this, a potential of + 5 V was applied to the stage. The result of inverting the polarity on the sample conductivity is presented in Fig. 7 for a Ge30Se70 sample with a deposition angle of α = 45°. A close comparison of Figs. 6(vii) and 7 reveals that some silver is extracted back towards the Ag electrode. Even though the voltage bias is reversed, the current scale in Fig. 7(vi–viii) shows some current flowing through the device. However, the measured current when the device is reverse biased is less, compared to the current measured when the device is

forward biased, and there are fewer conductive filaments as evidenced by the relative lack of filaments similar in color to the conductive W electrode region. This incomplete dis-solution of the filaments is likely because the applied bias is effective only when the probe comes in contact with the Ag surface (i.e., the sample is no longer reverse biased once the silver layer is scanned), with a maximum contact time of 500 µs per PF cycle. Furthermore, when the probe is lifted off the sample, it is actually floating. Because of these reasons, the grown Ag filament is not completely dissolved. However, a decrease in the current by reverse biasing the sample, as illustrated in Fig. 7, suggests a reduction in the number of filaments or weakening of the conduction path by extracting Ag back towards the Ag source.

Fig. 7 PF-TUNA scans obtained with the stage/sample biased at + 5 V relative to the probe and a Peak Force setpoint of 10 nN for Ge30Se70 with α = 45° where (i–iv) are the top scan view and filament growth through the voids in the columnar structure, (v) is the top

view image rotated by 90°, and (vi–viii) are the side scan view of the cross sectional area and the filament growth through the nanotubes in the columnar structure with corresponding current scales

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PF-KPFM images acquired under unbiased and biased con-ditions of a Ge30Se70 film deposited at α = 45° are presented in Fig. 8. A clear difference in the potential of the Ge30Se70 film under the two conditions can be noted. Close inspection and comparison of the two images shows the formation of Ag fila-ments within the nanotube structure after the bias was applied.

3.2 I–V characteristics of the devices and memory window

Figure 9 presents the IV characteristics of the studied devices. Significant variation is observed in the switching voltage of the normally (α = 90°) deposited films. However, a substantial improvement in the devices’ performance is observed when fabricated with obliquely deposited (α < 90°) active films. This improvement is achieved by steering the filament growth formation through the columnar structure. It is important to reiterate that no photo diffusion step was performed for the angularly deposited films, thereby saving time, cost, and labor for reducing this processing step.

The memory window for CBRAM devices is defined as the resistance difference between the ON and OFF states of the device, i.e., between its high resistive state (HRS) and low resistive state (LRS). Mathematically, this can be expressed as:

Having a good memory window ensures a larger toler-ance value for the read out bit stored in the CBRAM cell, thus reducing the circuit complexity of the error correction

(1)MemoryWindow = ROFF − RON

bit. For reference, the so far reported resistive memory devices [22–24] have shown two to four orders of magnitude difference between the two stable states.

In the nanotube structured devices, no deterioration was observed in the memory window. The devices, with Ge-Se active layers, showed four to five orders of magnitude differ-ence between the HRS and LRS as illustrated in the resist-ance–voltage (R–V) plot in Fig. 10. The consistency in the switching voltage is also presented on the plot to highlight the improvement achieved in the devices by formation of such nanotube structures, compared to these deposited at a normal angle of incidence. The devices show a remark-able endurance of over 106 cycles as displayed in Fig. 10, meeting the requirements for good endurance of ReRAM devices [23, 25].

3.3 Threshold voltage control with oblique angle

A unique advantage of the application of obliquely depos-ited active films in the CBRAM cells is to have control over the turn ON voltage of the devices without involving any complex circuitry. Since the inclination of the growing structure is dependent on the incident vapor flux [18], by altering the source vapor angle the nanotube structure in the active layer of the device also changes. The change in inclination of the nanotubes provides different lengths for the growing filament, which in turn affects the switching voltage. The resulting switching voltage dependence of the Ge-Se system on the obliqueness of the incident vapor flux

Fig. 8 PF-KPFM scans (Peak Force = 10 nN) of a Ge30Se70 film deposited at α = 45° acquired under a unbiased and b biased conditions

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is presented in Fig. 11. There is a general trend of decrease in the threshold voltage with decreasing of the deposition angle observed, although there are some fluctuations. The variation in the threshold voltage can also be explained by an insight into the parameters affecting the formation of the conductive filament. The kinetics of the oxidation–reduction reaction between two substances A and B reacting with rate constants k can be expressed by Eq. (2), where kf corre-sponds to a reaction rate in the forward direction (oxidation) and kb represents the reaction rate in the backward direction (reduction):

The rate constants k (kf and kb) can be expressed in Arrhe-nius form as:

where EA is the activation energy, A is a constant, T is the temperature in Kelvin, and kB is the Boltzmann constant. The reaction rate kinetics can be explained with the help of Fig. 12, which presents the standard free energy change of the reacting

(2)Akf ,kb⟺ B

(3)k = A ⋅ e

−EA

/

kBT

species in going from the metal electrode to solid electrolyte. The reaction coordinates express the progress of the reaction along a forward path, i.e., the position of the species with respect to the interface. The inclined barrier energies corre-spond to the respective activation energies of the oxidation EAO and reduction EAR reactions. Varying the electrode potential can change the energy devolution and therefore the activation energy for the respective reaction, as indicated in Fig. 12. Due to voltage dependence, current density can be associated with this interface as described by the Butler–Volmer equation [26, 27], which applies the Arrhenius equation to the special case of electrochemical kinetics where the forward and backward reactions are oxidation and reduction, respectively, and the activation energy is affected by a variety of factors including the number of electrons involved in the reaction, the extent to which the experimental conditions deviate from equilibrium, and the shape of the potential energy barrier,

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106

0.0 0.2 0.4 0.6 0.8 1.0

0

10n

20n

30n

40n

50n

60n

110

102

103

104

105

106

)A(

tnerr

uC

Voltage (V)

0.0 0.2 0.4 0.6 0.8 1.0

0

10n

20n

30n

40n

50n110

102

103

104

105

106

)A(

tnerr

uC

Voltage (V)-0.2 0.0 0.2 0.4 0.6 0.8 1.0

0

10n

20n

30n

40n

50n110

102

103

104

105

106

)A(

tnerr

uC

Voltage (V)

Incident Vapor Angle = 90˚ Incident Vapor Angle = 80˚ Incident Vapor Angle = 70˚

Incident Vapor Angle = 60˚ Incident Vapor Angle = 45˚ Incident Vapor Angle = 30˚

(a) (b)

(c)

Fig. 9 IV curves for 106 cycles for a Ge20Se80, b Ge30Se70, and c Ge40Se60 having nanotube structure in the active films deposited at various inci-dent angles: (i) α = 90°, (ii) α = 80°, (iii) α = 70°, (iv) α = 60°, (v) α = 45°, and (vi) α = 30°

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2397Journal of Materials Science: Materials in Electronics (2019) 30:2389–2402

1 3

(a)

(b)

(c)

Fig. 10 RV plot for 106 cycles for a Ge20Se80, b Ge30Se70, c Ge40Se60 films having nanotube structure in the active films under various incident angles: (i) α = 90°, (ii) α = 80°, (iii) α = 70°, (iv) α = 60°, (v) α = 45°, (vi) α = 30°

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conditions, n is the number of electrons involved in the reac-tion, e is the elementary charge (i.e., the magnitude of charge carried by an electron), kB is the Boltzmann constant, T is the temperature in Kelvin, η is the potential deviation from the equilibrium voltage conditions, and α is the transfer coeffi-cient, which depends on the shape of the intersection region of the energy curve in Fig. 12. The exponential behavior of the rate constants k in Eq. (3) is reflected in the exponential behavior of the anodic and cathodic currents. To switch the CBRAM device in the SET state, a certain amount of Ag is required to form the conductive bridge. This amount of Ag is proportional to the charge Qo flowing through the device

during a programming (SET) operation. The quantity of sil-ver ions generated at the metal electrode/electrolyte inter-face is determined by the over potential η and Eq. (4). To determine the ion current, one has to take into account the effective area involved in the ion generation process, which can be expressed as:

In Eq. (5), j is the net current density and Aeff is the effec-tive area at the metal electrode/electrolyte interface taking part in the reaction. Since the entire electrode/electrolyte interface is not involved in the ion generation process, inho-mogeneity of current density occurs. With a rough surface, each time the effective area participating in the ion gen-eration process will vary, which will give rise to a different switching voltage, resulting in inconsistent switching during the SET process.

Another improvement achieved with the nanotube struc-tured devices, is the shift of programming threshold volt-age in some cases to relatively higher voltages compared to photodoped devices [28]. There are devices switching to the ON state for a voltage higher than 0.6V. Hence the prob-ability of devices embedded into analog integrated circuit falsely switching during an event of noise generation will be minimal. It can be inferred from the I-V curves of the stud-ied chalcogenide compositions (Fig. 9) that the obliquely deposited Ge20Se80 devices are best suited for logic appli-cations [29], since all the devices have a turn ON voltage greater than 1V.

(5)I = jAeff

Fig. 11 Dependence of switch-ing voltage on the incident vapor angle for a Ge20Se80, b Ge30Se70, and c Ge40Se60 com-positions based devices

Ge20Se80 Ge30Se70

Ge40Se60

102 103 104 105 106

1.0

1.5

2.0

2.5

3.0)V(

egatl

oV

gni

hctiw

SNo. of Cycles

8070

60 4530

102 103 104 105 106

0.5

1.0

1.5

2.0

2.5)V(

egatl

oV

gni

hctiw

S

No. of Cycles

8070

60 4530

102 103 104 105 1060.5

1.0

1.5

2.0

2.5)V(

egatl

oV

gni

hctiw

S

No. of Cycles

8070604530

(a) (b)

(c)

Oxidation

Reduction

EAO EAR

electrode electrolyte

potential increase

stan

dard

free

energy

reaction coordinate

Fig. 12 Standard free energy changes during an electrode reaction [26]

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3.4 I–V measurements at 130 °C

In addition to room temperature, the fabricated CBRAM devices were tested at 130 °C, which is well above the required specifications of developed memory technolo-gies [30–33]. The memory window for the Ge-Se nano-tube devices did not show any significant degradation in performance at this elevated temperature. However, a slight change was observed in the switching threshold voltage compared to room temperature, which is attributed to ther-mal activation of the electrochemical process for filament formation. Also, heating the sample to higher temperatures results in greater silver ion mobility during the conductive bridge formation. As a result, the filament does not grow in its usual directional manner; rather, the Ag filament forms by traversing through the nanotubes between the columnar structures, resulting in some variation between consequent sweeps, similarly to devices with an amorphous structure [34]. The switching voltage and memory window perfor-mance of the fabricated Ge-Se nanotube columnar structure devices for 500 cycles are presented in Fig. 13.

Except for the Ge20Se80 columnar device, Fig. 13a, all the devices successfully completed 500 cycles of testing at the elevated temperature. Among the studied compositions, Ge20Se80 has the lowest glass transition temperature (Tg ≈ 160 °C). Hence heating the Ge20Se80 devices close to their Tg may have altered the active layer of the film, resulting in device failure as seen in Fig. 13a. All other devices achieved the 500 testing cycles without failure. Close observation of the high resistive state reveals a slight decrease in the resist-ance relative to room temperature, which is in accordance with the expected behavior, i.e. increasing the temperature multiplies the number of charge carriers in a p-type semi-conductor, thus enhancing the Ge-Se conductivity and there-fore reducing the corresponding resistance.

Despite this reduction in the high resistive value, the memory window was still more than four orders of mag-nitude at the elevated temperature. Hence, no additional temperature sensing circuitry is required to reduce the read out error. On the basis of the presented data, reliable perfor-mance of CBRAM cells is expected in the temperature range that is standard for memory applications.

3.5 Retention testing

The stability of the memory states of the fabricated nanotube structure devices were analyzed through retention measure-ments. Since the high resistive state of the devices is above the resolution limit (1010 Ohms), the devices were tested for their retention property in the low resistive state only. The devices were programmed to the low resistive state by setting the compliance current to 10 µA with a step size of 10 mV in a single forward sweep direction. Once the devices

were programmed, the change in state of the device should occur only if the conductive filament deteriorates over time. The fabricated devices were tested for retention properties at 130 °C to predict the device lifetimes. The state of the programmed devices was detected by reading the state of the cell with the parameter analyzer at specific times with a read voltage ranging from 0.3 V to 0.5 V. The retention testing results are presented in Fig. 14. The experimental results reveal the estimated stability of the columnar structured devices in the low resistive state to be more than 10 years [35], according to the accelerated tests carried out. The accelerated testing of devices for retention properties can be extrapolated with Arrhenius theory to predict the actual lifetime of the devices.

where AF is the acceleration factor, Ea is the activation energy, kB is the Boltzmann constant, T1 is the application junction temperature in Kelvin and T2 is the accelerated stress junction temperature in Kelvin.

Depending on AF, a back calculation using the Arrhenius equation for any desired temperature leads to fairly accurate data retention time estimates. Prior to testing, the samples were subjected to high temperature for 96 h. The purpose of this was to directly determine data retention times at higher temperatures in order to calculate expected data retention lifetimes at 25 °C.

Using this AF information, back substitution gives the data retention in years at 25 °C.

The stable states achieved with the test results extrapo-lates to approximately 10 years of data retention. Thus the devices having the nanotube structure are well suited for use in non-volatile applications.

3.6 Multilevel switching capability

In the CBRAM device, multilevel switching can be achieved by controlling the write current (compliance current). The ON resistance, RON, of CBRAM devices decreases monotonically with increasing write current (ISet or ICC) [36]. The dependence of A

/

InSet

RON on ISet often follows the power law RON = A

/

InSet

where A is a constant with units of voltage and n is a dimensionless number typically close to one. The power law equation is gener-ally valid for currents less than 80 µA [37]. This relation-ship is reported for a variety of device sizes and materials

(6)AF = e−

Ea

kB

(

1

T2−

1

T1

)

(7)e−

0.67

8.617×10−5

(

1

(130+273)−

1

(25+273)

)

≈ 900

(8)Data Retention@25 =96 × 892

24 × 365≈ 10 years

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Fig. 13 RV plots for 500 cycles at 130 °C for a Ge20Se80, b Ge30Se70, c Ge40Se60 films having nano-columnar structure in the active films deposited at various incident angles

(a)

(b)

(c)

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including Ag/Ge–S/W [38], Ag/Ge–Se/Pt [38], and Cu/SiO2/W [39]. The same dependence has been reported for bilayer devices, e.g., Cu/Ge–Se/Ta2O5/W [39], which sug-gests the power law to be material independent. Similar behavior has also been observed with nanotube structure devices. RON ∝ 1∕ISet can be thought of as being a natural consequence of having a resistor in series with a CBRAM cell during the SET state. With the CBRAM cell in OFF state, it can be presumed to have resistance ROFF much larger than the series resistance, Rs, and the applied volt-age is dropped primarily across the CBRAM cell at the beginning of the SET operation. As the cell starts to go into the SET state, its resistance drops to a value compara-ble to Rs, and a large fraction of the applied voltage begins to fall across the series resistor.

To achieve multilevel switching in the fabricated nano-tube structured devices, the CBRAM cells were programmed with different write current levels. Since the voltage switch-ing is achieved in all the studied Ge-Se compositions under all the incident vapor angles, the same is achieved by setting multiple compliance current values to demonstrate multi-level switching [40]. All the fabricated devices were tested with compliance current values separated by five orders of magnitude difference. The multilevel switching performance of Ge30Se70 nano-structured devices fabricated at a vapor incident angle of 60° is demonstrated in Fig. 15.

4 Conclusions

In this work we completed complex characterization of CBRAM devices with nano-tube structure of the active films in which the conductive bridge is developing. This characterization includes proof of the nanotube structure within the active films via SEM, as well as nanoscale elec-trical characterization of the devices through PF-TUNA and PF-KPFM. The AFM-based nanoelectrical measurements illustrated the directional growth of the nano-ionic metallic filament through the engineered nanotube structures, with no evidence of multi-branching, which is the basis for the improved device performance.

Formation of columnar structures enhanced the per-formance of devices fabricated with active films from the Ge-Se system. Electrical testing of the devices revealed Write/Read voltages were dependent on deposition angle of the chalcogenide nanotubes. Due to the unique design of the devices, the switching voltage can be engineered by varying the deposition angle. These devices exhibited excel-lent uniformity in switching voltage with endurance well over 106 cycles, retention over 10 years at room tempera-ture (as extrapolated from data at an elevated temperature of 130 °C), and a good memory window. Finally, and most importantly from an application point of view, these devices demonstrated little higher threshold voltage which implies

100 101 102 103 104 105 10610k

100k

1G

10G

100G 90°C 130°C

Res

ista

nce

(Ω)

Time (sec)100 101 102 103 104 105 106

10k

100k

1G

10G

100G

1T 90°C 130°C

Res

ista

nce

(Ω)

Time (sec)100 101 102 103 104 105 106

10k

100k

1G

10G

100G

Res

ista

nce

(Ω)

Time (sec)

90°C 130°C

100 101 102 103 104 105 10610k

100k

10M

100M

1G

10G

Res

ista

nce

(Ω)

Time (sec)

90°C 130°C

100 101 102 103 104 105 10610k

100k

1G

10G

Res

ista

nce

( Ω)

Time (sec)

90°C 130°C

LRS

LRS LRS

HRS HRS HRS

HRS HRS

LRS LRS

(a) (b) (c)

(d) (e)

Fig. 14 Data retention of the low resistive state of the devices written at a compliance current value of 10 µA for a Ge20Se80 with α = 80°, b Ge30Se70 with α = 60°, c Ge40Se60 with α = 45°, d Ge20Se80 with

α = 30°, and e Ge50Se50 with α = 30° devices. The data for the written bit is read at a voltage ranging from 0.3V to 0.5V

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that they can be included in analog circuit solutions without additional circuitry for prevention of noise influence. This validates the exceptional value from an application perspec-tive of the findings reported in this work.

Acknowledgements This work was partially supported by funding through Idaho State Board of Education under Grant No. IF14-004. Authors acknowledge the participation in this work of Jason Nielsen, who conducted the AFM measurements.

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Fig. 15 a I–V curves obtained at varying compliance current values for Ge30Se70 column-structured devices with a deposition angle of α = 60°. b Dependence of low resistive state on the compliance current value at room temperature

(a) (b)


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