Symposia on VLSI Technology and Circuits

CBRAM® Macro Embedded in a Body Sensor Node

Nad Gilbert1, Yanqing Zhang2, John Dinh1, Benton Calhoun2,and Shane

Hollmer1

1 Adesto Technologies, Sunnyvale, CA2 University of Virginia, Charlottesville, VA

Outline• Introduction - Ultra Low Power (ULP)• CBRAM technology• CBRAM Macro Architecture• Energy Monitor• Sensing Circuit and Energy measurement Results• Write Circuit and Energy measurement Results• Body Sensor Node (BSN) concept and results• Die Photo• Comparison of macro to Prior work• Conclusion

Slide 2

Introduction

Slide 3

Typical Low Power Sensor

TI SoC - Microcontroller, 12 bit ADC, temperature sensor (Demonstrated in ULP system), 128KB embedded FLASH(The Missing ULP component)

Transceiver (Demonstrated in ULP system)

Non-volatile Serial Flash

The Missing ULP component

Image courtesy of University of Washington

CBRAM Technology – Introduction

Slide 4

Conductive Bridging RAM (CBRAM) isa subset of Resistive RAM

that is highly scalable

low power high performance

and can be integrated at Back-End-of-Line in a standard

CMOS processes.

< 20nm dimensions< 0.6V OperationMulti Level Cell

< 1A Write < 0.6V Write

1Transistor – 1 Resistor Cell (1T1R)DRAM Cost Structure

<50ns WriteLarge Read SignalVerify During Write

CBRAM Technology – Cross section

Slide 5

AnodeCathode

Transistor

TEM

Data is stored by modulating the resistance of the dielectric layer.

0.4

0.6

0.8

1

1.2

84 86 88 90 92

Cathode

Anode

0

0.2

0.4

0.6

0.8

0 5 10 15 20 25 30

Cathode

Anode

CBRAM Technology - Operation

Slide 6

1T1R Cell

Time (µs)

Cathode

Anode

0V

400nA

Tpg=14µs

Anode

Cathode

1.2V

200nATer=2µs

Program at 600mV and 400nAV

olta

ge (V

)V

olta

ge (V

)

Erase at 600mV and 200nA

CBRAM Macro Architecture

Slide 7

Array:32 cols256 rows

x8

8:1 8:1

RD RD

4:1

VWL

Lvl Conv

WL

BLAN BLS

x8

Din Write ctrl

Write drivers

x8

Array:32 cols256 rows

x8

8:18:1 8:18:1

RD RD

4:1

VWL

Lvl Conv

WL

BLAN BLS

x8

Din Write ctrl

Write drivers

x8

•Dual bit line•Maximum device isolation•Dual supply domains • VDD (read) VCC (write)•Maximum usage of VCC•Minimized series resistance•Variable Word Line voltage

Voltage Across Cell

Slide 8

0.6 V

0 VERASE

0.6 V0.6 V0.4V

0 VHALF SEL BL

0 V

0.4 V

0.6 VPROGRAM

0 V0.4V

~0.2VREAD

0 V

On Chip Energy Monitor

Slide 9

VCCANALOG

VREF

VMEAS

IBIAS IBIAS

VLOAD

ILOAD

Energy monitor for each supply: VCC, VDD, and VWL

M1

Id(M1)=ILOAD

•Dynamic Current monitor

Sensing Circuit

Slide 10

WL

BLAN BLS

VDD as low as 0.3V

Pull Up Strength

Read Strobe Data Out

Read Strobe

8:1

8:1

Read Strobe

SN

Programmable Pull up

Source follower Voltage limit

Measured results of Sense circuit

Slide 11

Energy Vs. Delay of Reading 1 Byte

0.01

0.1

1

10

0.1 1 10 100Energy (pJ)

Del

ay (u

s)

Strength=0

Strength=4

Strength=7

0.39 pJ/B

Write Circuit

Slide 12

WL

BLSBLAN

DinPROG

1

1

OFF

1

DinERASE

VWL

drivers

Minimized Series resistance write path

Data Dependent Erase

Data Dependent Program

VCC VCC

Complete Isolation when not selected

VCC as low as 0.6V

0.2

0.3

0.4

0.5

0 20 40 60 80 1000

40

80

120

160

200

Measured Results of Program Operation

Slide 13

Mea

s. T

ot. E

(pJ)

VM

EA

S (V

), α

I PR

OG

Time (μs)

VCC=0.6V, VWL=0.6V, VDD=0.4V

TPROG=10us

Measured Program from CBRAM Array

leakageCurrent

Program Energy vs. Supply

Slide 14

Ene

rgy

(pJ)

VCC (V)

Sim. Energy/bit to PROG time @ const Ron

0

1

2

3

4

5

6

0.4 0.6 0.8 1 1.2 1.4 1.6

Ron=62.1kRon=300k

Energy Minima at 1V

Energy Minima at 0.7V

Measured Results of Write Operation

Slide 15

0.2

0.3

0.4

0.5

0 10 20 30 40 50 60 70 800

2

4

6

8

10

12

Mea

s. T

ot. E

(pJ)

VM

EA

S (V

), α

I ER

AS

E

Time (μs)

VCC=0.6V, VWL=1V, VDD=0.4V

TERASE=23us

Measured Erase from CBRAM Array

leakageCurrent

Erase Energy vs. Supply

Slide 16

Ene

rgy

(pJ)

VCC (V)

Sim. Energy/bit to Erase time @ const Ron

0

10

20

30

40

50

60

70

80

0.4 0.6 0.8 1 1.2 1.4

Ron=62.5kRon=602k

High Ron, Low energy

Body Sensor Node (BSN)

Slide 17

IMEM DEBUG SCAN CHAIN

CBRAM IMEM

DIGITAL POWER

MANAGER

CLOCK GEN.

SCAN CHAIN OUT

DMEM CONFIG.

SCAN CHAIN

CBRAM DMEM

DMA

GPP RISC PROCESSOR

RR ACCEL.

AFIB ACCEL.

Bus

1[7:

0]B

us2[

7:0]

FIR ACCEL.

ENV DET ACCEL.

ClkConfigEnConfig

ConfigBits

ClkScanEnScan

ScanBits

SystemClkADC[7:0]

ScanOutBitsAccel. Clks

IMEM CONFIG.

SCAN CHAIN

CBRAM was integrated with the Digital Platform only

BSN Results

Slide 18

Enable[5:0]ClkGt[6:0]

Rst[6:0]Bus1_connect[12:0]

Bus2_connect[12:0]

RISC_out[7:0]

6’hxx 6’h3E 6’hxx 6’h3E

7’hxx 7’h01 7’hxx 7’h01

13’hxxxx 13’h17FE 13’hxxxx 13’h17FE

7’hxx 7’h01 7’hxx 7’h0113’hxxxx 13’h1F9F 13’hxxxx 13’h1F9F

8’hxx 8’h80 8’hxx 8’h80

Off/… On/10:45 AM On/5:55 PMOff/…Supply Status/Time

Measured scan chain outputs showing correct operation of RISC processor from

CBRAM, after power-down all day

BSN (digital) and CBRAM Die Photograph

Slide 19

64kbCBRAMIMEM

64kbCBRAMDMEM

Timing Blocks And Config. Scan Chains

DPMDMA

RISC μProc

ScanOut

ENVDET

CLKGEN

Prog. FIR

RR+AFib

Write Voltage (V)

Prog

ram

Ene

rgy

(pJ)

1

10

100

1000

This work

[5]

[6]

[3]

[4]

Slide 20

[3] 0.5V 4Mb embedded ReRAM

[4] Flash with self-aligned split-gate cell

[5] STT-MRAM

[6] 4Mb embedded phase-change memory

Comparison of Program Energy

Metric This work

[3] [4] [5] [6]

Technology CBRAM ReRAM FG Flash

MRAM PCM

CMOS Compatibility Yes Yes No Yes No

Read Core Voltage (V) 0.35 0.32 0.5 1.2 1.2

Write Core Voltage (V) 0.6 2.0 10 3.3 2.8

Program Energy/bit 1 pJ 2 nJ 100 pJ 10 pJ 250 pJ

Read Energy/bit 50 fJ 75 fJ 500 fJ 100 fJ 500 fJ

Charge pumps needed for <1 V SoC

No Yes Yes Yes Yes

Slide 21

Comparison of Technology

Conclusion• Device

– 2 CBRAM macros embedded in BSN

• Technology– 0.13 mm standard CMOS

• Array size– 64 kb

• Operating voltage– Integrated in BSN 0.5V– CBRAM macro 0.4 V read 0.6 V write

• Operating Frequency– 200 kHz

• Write energy– 8 pJ

Slide 22

Acknowledgements• Ralph Williams and Derric Lewis

– Digital test interface of the CBRAM macro• Altis Semiconductor

– Chip manufacturing• DARPA

– Partial funding through an SBIR award

Slide 23