CDA 3103 Fall 2011 Exam CDA 3103 Computer Organization Final Exam (Dec. 5th, 2011) Grades: 40% of the final grade. Name: USF ID: Problem Points Your Points 1 25 2 10 3 12 4 9 5 8 6 8 7 10 8 12 9 6 Total 100 Exam Rules • Use the back of the exam paper as necessary. But indicate clearly which problems that the answers on the back correspond to. • Make sure that your writing is legible; otherwise you grades may be adversely a↵ected. • Close book, notes and HW. Only the exam paper is allowed • All electronics must be turned o↵. • Show all work to get partial credits except yes/no problems. 1
• Use the back of the exam paper as necessary. But indicate clearly which problems thatthe answers on the back correspond to.
• Make sure that your writing is legible; otherwise you grades may be adversely a↵ected.
• Close book, notes and HW. Only the exam paper is allowed
• All electronics must be turned o↵.
• Show all work to get partial credits except yes/no problems.
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CDA 3103 Fall 2011 Exam
Problem 1 (25 pts total, 1 pt each): Answer T (true) or F (false) to each ofthe following questions.
1. T The output of a 2-input NOR gate is 1 when both inputs are 0.
2. T A maxterm of F (x, y, z) = x + y is (x + y + z).
3. T
In both signed-magnitude and 1’s complement encodings, there are two binarycodes for number 0.
4. F
Natural binary and binary coded decimal (BCD) representations of the number(88)10 are identical.
5. T The outputs of a SR flip-flop can remain unchanged when its inputs change.
6. F
An edge-triggered flip-flop changes its output only when the clock is high orlow.
7. F A data bus connects only two components: a sender and a receiver.
8. F Memory-mapped I/O operations require special instructions.
9. F The last element stored on a stack is the last to be read out.
10. T Not all 68K instructions modify the CCR.
11. F The memory address register always holds the address to the next instruction.
12. T Every instruction needs to be fetched before it can be executed.
13. F Microinstructions are just a di↵erent name for instructions.
14. F Static RAM (SRAM) needs to be refreshed to avoid loss of data.
15. T SRAM is faster than DRAM, but SRAM has lower capacity than DRAM.
16. F RAM and ROM both are non-volatile memory.
17. F A 68K stack is just another type of memory in the memory hierarchy.
18. F Stack is not necessary to handle interrupts.
19. F In open-loop protocol, data can always be received by the receiver correctly.
20. F A branch instruction generates an interrupt.
21. F
Direct memory access (DMA) makes the CPU sit idle, thus causing the wholecomputer to run slower.
22. F
The purpose of the memory hierarchy is to choose a single type of memory fora computer system for high performance and low cost.
23. F In operating systems, programs and processes refer to the same things.
24. T In a 68K CPU, only the operating system runs in the supervisor state.
25. F Both inkjet and laser printers use ink to print on paper.
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CDA 3103 Fall 2011 Exam
Problem 2 (10 pts total): Refer to the following figure.
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1. Complete the connection in the above figure between the computer and the peripheralfor the closed-loop data transfer protocol.
2. Show the timing diagram on signals of the connection illustrating how the closed-loopprotocol works when the computer needs to send two data D1 and D2 to the peripheral.
3. Is the timing diagram you draw for handshaking or fully inter-locked protocol?Justify your answer.
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CDA 3103 Fall 2011 Exam
Problem 3 (12 pts total) A circuit has four inputs, A, B, C, and D, and one outputF . Output F is 1 when the number represented by the inputs is NOT prime; otherwise, itis 0. A prime number is greater than 1, and is divisible only by itself and 1. Design thiscircuit by completing the following steps.
1. Complete the column under F in the truth table and the K-map in the above figure.
2. Find the minimized Boolean expression for output F by using the K-map method.
F = CD + BC + AD + ABC + BD
3. Implement the Boolean expression derived in the previous step as a combinationalcircuit using 2-input NOR gates only.
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CDA 3103 Fall 2011 Exam
Problem 4 (9 pts total): Refer to the following figure. Suppose all flip-flops areinitialized with values as follows:
Q1 = 1, Q2 = 1, Q3 = 1, Q4 = 0
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D Q
C
D
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D Q
C
D
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D Q
C
D
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D Q
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D Q
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Clock
1. What are the flip-flops in the above figure? Circle the correct answer.
level� sensitive or edge� triggered
2. Show the value of Q1, Q2, Q3, and Q4 at the end of each clock cycle from the beginningas indicated below. Note that the value of these signals at the beginning is defined asshown above.
Q1 Q2 Q3 Q4
Cycle 0 1 1 1 0
Cycle 1 1 1 1 1
Cycle 2 0 1 1 1
Cycle 3 0 0 1 1
Cycle 4 0 0 0 1
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CDA 3103 Fall 2011 Exam
Problem 5 (8 pts total): Interrupt handling
1. What are the main components that consist of the context of a process?
2. What the main steps the operating system takes when an interrupt occurs? List thesesteps, and describe each step with su�cient level of elaboration.
Problem 6 (8 pts total): Represent x = �22 and y = 99 using 8 bits. Calculatex + y by using
Natural binary arithmetic
01100011� 00010110
01001101
2’s complement arithmetic
01100011+ 111010101 01001101
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CDA 3103 Fall 2011 Exam
Problem 7 (10 pts total): Refer to the following assembly program.
MOVE.L #10, D0MOVEA.L #1000, A0
Again MOVE.B D0, (A0)ADDA.L #1, A0SUB.L #1, D0BNE Again
1. What the addressing modes are used in the above assembly program?
• Immediate
• Indirect
2. Use RTL to show the content of all memory locations and registers modified by thisprogram after it ends.
3. Refer to the above program, and write a new assembly program that swaps contentsstored in memory locations 1000 and 1009, 1001 and 1008, . . ., 1004 and 1005. Thatis, the content in memory location 1000 is swapped with that in 1009, and similarlyfor memory locations in 1001 and 1008, and so on.
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CDA 3103 Fall 2011 Exam
Problem 8 (12 pts total): The following figure shows the memory hierarchy discussedin the class with missing pieces.
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1. Associate the places labeled with the following numbers with proper memory type.
1. 2. 3.
4. 5. 6.
2. What appropriate words should be used to associate with the places labelled with thefollowing numbers to correctly reflect the characteristics of the memory hierarchy?
7. 8. 9. 10.
3. Based on the above memory hierarchy, what factors do you need to consider whendesigning a memory system for a typical main-stream computer? Show at least two ofthese factors with some concise elaboration.
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CDA 3103 Fall 2011 Exam
Problem 9 (6 pts total): Answer the following questions with concise descriptions.
1. Some key switches need to be debounced. Why?
2. What are pixels and frames in displays?
3. If a display has a resolution 1024⇥ 768 with a refresh rate of 60 Hz. How many pixelsneed to be scanned per second? Show the formula. You do NOT have to calculate thefinal number.
1024⇥ 768⇥ 60
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CDA 3103 Fall 2011 Exam
Theorems for your reference:
X + X · Y = X (1)
X + X · Y = X + Y (2)
X · Y + X · Z + Y · Z = X · Y + X · Z (3)X · (X + Y ) = X (4)
X · (X + Y ) = X · Y (5)X · Y + Z = (X + Z) · (Y + Z) (6)
SHOW ALL WORK TO GET PARTIAL CREDIT (except for True/False questions) Assembly Language references assume 68000 processor. Make reasonable assumptions.
68K Instruction Summary
Data Movement MOVE D3, D1 ����������� MOVE #4, D1 ������� MOVE.B D0, D1 ��������������������� MOVE.W ABC, D1 ������������ �� MOVE.L D0, (A0) �� ����������� MOVE (A0), D0 ��������� ��� Arithmetic ADD D0, D1 Add ������������������� ADC D0, D1 Add with Carry ���������������������� SUB D0, D1 Subtract ������������- [D0] SBC D0, D1 Subtract with Carry ������������- [D0] – C MULU D0, D1 Multiply (unsigned) ��������D1] x [D0] MULS D0, D1 Multiply (signed) ������������������� DIVU D0, D1 Divide (unsigned) ������������������� DIVS D0, D1 Divide (signed) ������������������� Logical AND D0, D1 Logical AND ������������������ OR D0, D1 Logical OR ������������������ EOR D0, D1 Logical EOR �������������[D0] NOT D1 Logical NOT ���������������� Bit BTST #4, D0 BCLR #4, D0 BSET #2, D0 Shift LSL #n, D0 Logical Left Shift Shift contents of D0 n places left logically LSR #n, D0 Logical Left Right Shift contents of D0 n places right logically ASL #n, D0 Arithmetic Left Shift Shift contents of D0 n places left arithmetically ASR #n, D0 Arithmetic Right Shift Shift contents of D0 n places right arithmetically ROL #n, D0 Rotate shift left Rotate contents of D0 n places left ROR #n, D0 Rotate shift right Rotate contents of D0 n places right
SHOW ALL WORK TO GET PARTIAL CREDIT (except for True/False questions) Assembly Language references assume 68000 processor. Make reasonable assumptions.
Compare (performs D2 – D1 and updates Status Flags) D2 D1 Operation Status Flags 10101010 10101010 CMP D1, D2 Z = 1, C = 0, N = 0, V = 0 10101010 00000000 CMP D1, D2 Z = 0, C = 0, N = 1, V = 0 10101010 11000001 CMP D1, D2 Z = 0, C = 1, N = 1, V = 0 Control - Unconditional Branch BRA 2000 Control transfers to address 2000 ����������� Control - Conditional Branch Mnemonic Condition Flags BEQ equal Z = 1 BNE not equal Z = 0 BCS carry set C= 1 BCC carry clear C= 0 BMI negative N = 1 BPL positive or zero N = 0 BGE greater than or equal (signed) N = V BLT less than (signed) ����� BGT greater than (signed) (Z = 0).(N = V) BLE less than or equal (signed) ����������������� Control – Subroutine BSR ABC Branch to subroutine at ABC �������� � RTS Return from subroutine ���������� Misc CLR D0 Clear a register �������� EXG A2, D3 Exchange contents of registers ������������������������� SWAP D4 Swap upper two bytes with [D4(31:16)] �[D4(15:0)] ;
lower two bytes [D4(15:0)] �[D4(31:16)] ;
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CDA 3103 Fall 2011 Exam
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