CDC7005_040

CDC7005 3.3-V High Performance Clock Synchronizer

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Preliminary Datasheet 0.40 10/1/02

1

• High Performance 1:5 PLL Clock Synchronizer

• Two Clock Inputs: VCXO_IN Clock is Synchronized to REF_IN Clock.

• Synchronizes Frequencies up to 650 MHz (VCXO_IN)

• Supports Five Differential LVPECL Outputs

• Each Output Frequency is Selectable by x1, /2, /4, /8, /16

• All Outputs are Synchronized

• Integrated Low Noise OPA for External Low Pass Filter

• Efficient Jitter Screening from Low PLL Loop Bandwidth

• Very Low Phase Noise Characteristic

• Characterized from – 40°°°°C to 85°°°°C

• 3.3V Power Supply

• Packaged in 64-pin BGA (0.8mm - GGV)

Terminal Assignments (top view)

CTRL_LE CTRL_CLK CTRL_DATA CP_OUT OPA_N OPA_P OPA_OUT STAUS_

LOCK

REF_IN GND GND GND GND GND GND GND

I_REF GND AVCC AVCC AVCC AVCC AVCC STATUS_REF

VCXO_IN GND GND GND GND GND VCC STATUS_VCXO

VCXO_IN_B GND VCC VCC VCC VCC VCC VCC

Y0 GND GND GND GND GND VCC Y4B

Y0B VCC VCC VCC VCC VCCVCC Y4

NPD Y1 Y1B Y2 Y2B Y3 Y3B NRESET

1 2 3 4 5 6 7 8

A

B

C

D

E

F

G

H

Description The CDC7005 is a high-performance, low phase noise and low-skew clock synchronizer that synchronizes the VCXO (Voltage Controlled Crystal Oscillator) frequency to the reference clock. The programmable pre-dividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (N*P)/M. VCXO_IN clock operates up to 650 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. Each of the five differential LVPECL outputs is programmable by SPI (serial programmable interface). SPI allows individually control of frequency and enable/disable state of each output. The device operates in 3.3V environment. The build in Latches ensures that all outputs are synchronized. The CDC7005 is characterized for operation from –40°C to +85°C.




2

Functional Block Diagram

/1

/2

/4

/8

/16

PECLLatch

PECLLatch

PECLLatch

PECLLatch

PECLLatch

PECL2 LVTTL

Progr. DividerN

Progr. DelayN

Progr. DelayM

PFD ChargePump

HOLD

OPA

SPI LOGIC

MUX_SEL

PECLINPUT

PECLMUX1

PECLMUX2

PECLMUX3

PECLMUX4

PECLOUTPUT

PECLOUTPUT

PECLOUTPUT

PECLOUTPUT

PECLOUTPUT

REF_IN

CTRL_LE

CTRL_DATA

CTRL_CLK

VCXO_IN

VCXO_INB

Y4B

Y4

Y3B

Y3

Y2B

Y2

Y1B

Y1

Y0B

Y0

CP_OUT

STATUS_LOCK

STATUS_VCXO

STATUS_REF

OPA_OUT

OPA_IN

OPA_IP

P Divider

Progr. DividerM

LVCMOSINPUT

VIReference

I_REF

PECLMUX0

NRESET

NPD




3

Terminal Functions

TERMINAL NAME NO. TYPE DESCRIPTION

Y[0:4] F1, H1, H4, H7, G8 O LVPECL LVPECL Output Y[0:4]_B G1, H2, H5, H7, F8 O LVPECL LVPECL Output

VCC

C2, C3, C4, E2, E3, E4, E5, E6, E7, E8, F7, G2, G3, G4, G5, G6, G7

Power 3.3V Supply

GND

B2, B3, B4, B8, D2, D3, D4, D5, D6, D7, F2, F3, F4, F5, F6, F7

Ground Ground

VCC_OPA B5, B6, B7, C7 Power 3.3V OPA Supply GND_OPA C5, C6 Ground OPA Ground

CTRL_LE A1 I LVTTL Control Load Enable for Serial Programm-able Interface (SPI)

CTRL_CLK A2 I LVTTL Serial Control Clock Input for SPI CTRL_DATA A3 I LVTTL Serial Control Data Input for SPI

NPD H3 I LVTTL

Asynchronous PD (Power Down) Signal Active on Low. Switches all current sources off, resets the Dividers and 3States all outputs

NRESET H6 I LVTTL Asynchronous Reset Signal Active on Low. RESET all Flip Flops in the Dividers

VCXO_IN D1 I LVPECL VCXO Input VCXO_IN_B E1 I LVPECL Complementary VXCO Input REF_IN B1 I LVCMOS System Clock Input

I_REF C1 O Current Path for Reference Resistor (TBD kOhm)

OPA_IN A5 I Inverting Input of the op-amp OPA_OUT A6 O Output of the op-amp OPA_IP A7 I Non-Inverting Input of the op amp CP_OUT A4 O Charge Pump Output

STATUS_REF C8 O LVTTL Provides the Status of the Reference Input (Frequencies above 10 MHz are interpreted as valid clock)

STATUS_VCXO D8 O LVTTL Provides the Status of the VCXO Input (Frequencies above 10 MHz are interpreted as valid clock)

STATUS_LOCK A8 O LVTTL Provides the Information if the PLL is locked (need to be defined)




4

SPI Control Interface The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device. It consists of three control lines “CTRL_CLK”, “CTRL_DATA” and “CTRL_LE”. There are four 30 bits wide registers, which can be addressed by the two LSB of a transferred word. Every transmitted word must have 32 bits, starting with MSB first. The transfer is initiated with the falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE low data can be written. The data has to be applied at CTRL_DATA and has to be stable TBDns before the rising edge of CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. Figure 1: Timing Diagram SPI Control Interface

CTRL_CLK

DB2DB22DB23(MSB)

CTRL_LE

CTRL_DATA DB1 DB0

t1 t2

t4t3

t5

t6




5

Word 0: Bit Bit

Name Description / Function Type Power Up

Condition Pin Affected

0 C0 Register Selection W 0 1 C1 Register Selection W 0 2 M0 Reference Counter M Bit 0 W 1 3 M1 Reference Counter M Bit 1 W 0 4 M2 Reference Counter M Bit 2 W 1 5 M3 Reference Counter M Bit 3 W 1 6 M4 Reference Counter M Bit 4 W 1 7 M5 Reference Counter M Bit 5 W 1 8 M6 Reference Counter M Bit 6 W 1 9 M7 Reference Counter M Bit 7 W 0 10 M8 Reference Counter M Bit 8 W 0 11 M9

Ref

eren

ce C

ount

er M

Reference Counter M Bit 9 W 0 12 MD0 Reference Delay MD Bit0 W 0 13 MD1 Reference Delay MD Bit1 W 0 14 MD2

Ref

. D

elay

Reference Delay MD Bit2 W 0 15 PFD0 PFD Pulse Width PFD Bit 0 W 0 A4 16 PFD1 PFD Pulse Width PFD Bit 1 W 0 A4 17 PFD2 PF

D

Puls

e W

idt h

PFD Pulse Width PFD Bit 2 W 0 A4 18 CP0 CP Current Setting Bit 0 W 0 A4 19 CP1 CP Current Setting Bit 0 W 0 A4 20 CP2

CP

Cur

rent

CP Current Setting Bit 0 W 1 A4 21 Y03St Y0 N3State W 1 F1, G1 22 Y13St Y1 N3State W 1 H1, H2 23 Y23St Y2 N3State W 1 H4, H5 24 Y33St Y3 N3State W 1 H7, H8 25 Y43St Y4 N3State W 1 G8, F8 26 CP3St CP N3State W 1 A4 27 OP3St

Out

put 3

Stat

e

OPA N3State & Disable W 1 A6 28 MUXS0 MUXSEL Select Bit 0 W 1 29 MUXS1 MUXSEL Select Bit 1 W 0 C1 30 MUXS2 MUXSEL Select Bit 2 W 1 31 RES0 RESERVED0 W 0




6

Word 1: Bit Bit



0 C0 Register Selection W 1 1 C1 Register Selection W 0 2 N0 VCXO Counter N Bit 0 W 1 3 N1 VCXO Counter N Bit 1 W 0 4 N2 VCXO Counter N Bit 2 W 1 5 N3 VCXO Counter N Bit 3 W 1 6 N4 VCXO Counter N Bit 4 W 1 7 N5 VCXO Counter N Bit 5 W 1 8 N6 VCXO Counter N Bit 6 W 1 9 N7 VCXO Counter N Bit 7 W 0 10 N8 VCXO Counter N Bit 8 W 0 11 N9

VCXO

Cou

nter

N

VCXO Counter N Bit 9 W 0 12 ND0 VCXO Delay ND Bit0 W 0 13 ND1 VCXO Delay ND Bit1 W 0 14 ND2 VC

XO

Del

ay

VCXO Delay ND Bit2 W 0 15 MUX00 MUX0 Select Bit 0 W 0 F1, G1 16 MUX01 MUX0 Select Bit 1 W 0 F1, G1 17 MUX02 M

UX

0

MUX0 Select Bit 2 W 0 F1, G1 18 MUX10 MUX1 Select Bit 0 W 1 H1, H2 19 MUX11 MUX1 Select Bit 1 W 0 H1, H2 20 MUX12 M

UX

1

MUX1 Select Bit 2 W 0 H1, H2 21 MUX20 MUX2 Select Bit 0 W 0 H4, H5 22 MUX21 MUX2 Select Bit 1 W 1 H4, H5 23 MUX22 M

UX

2

MUX2 Select Bit 2 W 0 H4, H5 24 MUX30 MUX3 Select Bit 0 W 1 H7, H8 25 MUX31 MUX3 Select Bit 1 W 1 H7, H8 26 MUX32 M

UX

3

MUX3 Select Bit 2 W 0 H7, H8 27 MUX40 MUX4 Select Bit 0 W 1 G8, F8 28 MUX41 MUX4 Select Bit 1 W 1 G8, F8 29 MUX42 M

UX

4

MUX4 Select Bit 2 W 0 G8, F8 30 RES1 RESERVED1 W 0 31 RES2 RESERVED2 W 0




7

Word 2: Bit Bit



0 C0 Register Selection W 1 1 C1 Register Selection W 0 2 HOLD Enables Hold Functionality, High Active W 1 A4 3 ENBG Enable Bandgap W 0 4 REXT Enable External Reference Resistor W 0 C1

5 NPD PD, current Sources, dividers and 3States all outputs W 1

6 NRESET RESET all Dividers, Low Active W 1

7 CLK_SEL Determines in which direction CP should

regulate, if REF_CLK is faster than VCXO_CLK and vice versa.

W 0

8 CP_ON

Switches both the current source and the current sink in the Charge Pump on, to test the current matching (Test purposes only)

W 0

9 RES RESERVED W 0 10 RES RESERVED W 0 11 RES RESERVED W 0 12 RES RESERVED W 0 13 RES RESERVED W 0 14 RES RESERVED W 0 15 RES RESERVED W 0 16 RES RESERVED W 0 17 RES RESERVED W 0 18 RES RESERVED W 0 19 RES RESERVED W 0 20 RES RESERVED W 0 21 RES RESERVED W 0 22 RES RESERVED W 0 23 RES RESERVED W 0 24 RES RESERVED W 0 25 RES RESERVED W 0 26 RES RESERVED W 0 27 RES RESERVED W 0 28 RES RESERVED W 0 29 RES RESERVED W 0 30 RES RESERVED W 0 31 RES RESERVED W 0




8

Functional Description of the Logic Reference Divider M and VCXO Divider N M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Div by Default 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 1 1 4

• • •

0 0 0 1 1 1 1 1 1 1 128 yes

• • •

1 1 1 1 1 1 1 1 0 1 1022 1 1 1 1 1 1 1 1 1 0 1023 1 1 1 1 1 1 1 1 1 1 1024

Reference Delay MD and VCXO Delay ND

MD2 / ND2 MD1 / ND1

MD0 / ND0 Delay by Default

0 0 0 0ps yes 0 0 1 + 100ps 0 1 0 + 200ps 0 1 1 + 300ps 1 0 0 + 400ps 1 0 1 + 500ps 1 1 0 + 1ns 1 1 1 + 2ns

PFD Pulse Width Delay

PFD2 PFD1 PFD0 Additional Pulse Width by

max. PFD Frequency Default

0 0 0 0ps TBD yes 0 0 1 + 100ps TBD 0 1 0 + 200ps TBD 0 1 1 + 300ps TBD 1 0 0 + 400ps TBD 1 0 1 + 500ps TBD 1 1 0 + 600ps TBD 1 1 1 + 800ps TBD




9

Charge Pump Current

CP2 CP1 CP0 nominal Charge Pump Current ♣ Default

0 0 0 0.5 mA 0 0 1 1 mA 0 1 0 2.5 mA 0 1 1 4 mA 1 0 0 5 mA yes 1 0 1 6 mA 1 1 0 7.5 mA 1 1 1 10 mA

♣ with internal Reference Resistor (TBD kΩ) in use MUXSEL Selection

MUXS2 MUXS1 MUXS0 Selected VCXO Signal for the Phase Discriminator Default

0 0 0 from Y0 0 0 1 from Y1 0 1 0 from Y2 0 1 1 from Y3 yes 1 0 0 from Y4 1 0 1 from Y4 1 1 0 from Y4 1 1 1 from Y4

MUX0, MUX1, MUX2, MUX3, MUX4 Selection

MUXx2 MUXx1 MUXx0 Selected Divided VCXO Signal Default

0 0 0 from Div by 1 for Y0 0 0 1 from Div by 2 for Y1 0 1 0 from Div by 4 for Y2 0 1 1 from Div by 8 for Y3 1 0 0 from Div by 16 for Y4 1 0 1 from Div by 8 1 1 0 from Div by 8 1 1 1 from Div by 8




10

State Machine Description Hold Functionality Power Up / Reset 10 Cycles 5 Cycles Lock Detect of VCXO in Hold of CP Ref Frequency REF_CLK missing

STATE 1: PRE LOCK Normal Operation VCXO_ CLK

sync’s with REF_CLK

STATE 2: HOLD CTRL REF_CLK is sensed by

VCXO_CLK

STATE 3: HOLD OPERATION CP is in 3-State




11

Absolute Maximum Ratings over Operating Free Air Temperature (unless otherwise noted)†

Supply voltage range, VDD……………………………………………………........ -0.5 V to 4.6 V Input voltage range, VI (see Notes 1 and 2) ……………………………….......… -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) ………………………........-0.5 V to VDD +0.5 V Input clamp current, IIK (VI < 0) ………………………………………………...………..… -50 mA Output clamp current, IOK (VO < 0) …………………………………………………....….. -50 mA Continuous total output current, IO (VO = 0 to VDD) ………………………………....…. ±50 mA Package thermal impedance, θJA (see Note 3): GGV package ………………...…....… 75K/W Storage temperature range Tstg ……………………………………………...…... -65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input

and output clamp–current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

Recommended Operating Conditions MIN NOM MAX Unit VDD Supply voltage 3.0 3.3 3.6 V TA Operating free-air temperature -40 85 °C VIL Low level input voltage LVTTL 0.8 V VIH High level input voltage LVTTL 2 V VI Input voltage range LVTTL 0 3.6 V

VIL Low level input voltage LVPECL VDD-1.81 VDD-

1.475 V

VIH High level input voltage LVPECL VDD-1.165 VDD-

0.88 V




12

Timing Requirements over Recommended Ranges of Supply Voltage, Load and Operating Free Air Temperature MIN NOM MAX Unit

REF_IN Requirements fREF LVTTL REF Clock Frequency 3.50 100 MHz tr / tf Rise & Fall Time REF_IN Signal from 20% to 80%

of VDD 4.0 ns

dutyREF Duty Cycle Ref Clock @ VDD / 2 40 60 % VCXO_IN, VCXO_IN_B Requirements

fVCXO LVPECL VCXO Clock Frequency 10 650 MHz tr / tf Rise & Fall Time VCXO_IN – VCXO_IN_B 20% to

80% of Vpp @ 80MHz to 650MHz‡

3.0 ns

dutyVCXO Duty Cycle Ref Clock @ VPP / 2 40 60 % SPI / Control Requirements

fCTRL_CLK CTRL_CLK Frequency 20 MHz t1 CTRL_DATA to CTRL_CLK Setup Time # 10 ns t2 CTRL_DATA to CTRL_CLK Hold Time # 10 ns t3 CLRL_CLK High Duration # 25 ns t4 CTRL_CLK Low Duration # 25 ns t5 CTRL_CLK to CTRL_LE Setup Time # 10 ns t6 CTRL_LE Pulsewidth # 20 ns tr / tf Rise & Fall Time CTRL_DATA CTRL_CLK,

CTRL_LE from 20% to 80% of VDD @f<100MHz # 5 ns

‡ Use a square wave for lower frequencies

# Please see Figure 1: Timing Diagram SPI




13

Device Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP‡ MAX Unit

Overall Parameter

IDD Supply Current fVCXO=245 MHz, fREF_IN = 30 MHz, VDD = 3.6V; fPFD = 240 kHz, ICP = 5mA

TBD mA

IDDPD† Power down current fIN = 0MHz,Vdd=3.6V 20 µA

VPUC Supply Voltage Level for Power Up Control*

2.3 V

tpho Phase offset (REF_IN to selected Yx Output) ∞

± 250 ps

LVTTL Parameter VIK LVTTL Input voltage VDD = 3 V; II = –18 mA -1.2 V II LVTTL Input current VI = 0 V or VDD ± 5 µA

VOH LVTTL High-level output voltage

IOH = TBD TBD V

VOL LVTTL Low-level output voltage

IOL = TBD TBD V

CI Input capacitance at REF_IN

VI = 0 V or VDD 4.0 pF

CI Input capacitance at CTRL_LE, CTRL_CLOCK, CTRL_DATA

VI = 0 V or VDD 2.5 pF

LVPECL Parameter VPP Input Amplitude LVPECL see Figure TBD 0.5 1.3 V

VCMR Input Common Mode Voltage LVPECL see Figure TBD 1 VDD-

0.3 V

VIK LVPECL Input voltage -1.2 V II LVPECL Input current VI = 0 V or VDD 150 µA IOZ LVPECL Output 3-state ±5 µA

CI Input capacitance at VCXO_IN, VCXO_IP

2.0 pF

VOH LVPECL High-level output voltage

IOH = -30mA VDD-1.085

VDD-0.88

V

VOL LVPECL Low-level output voltage

IOL = -5mA VDD-1.83

VDD-1.62

V

VOUTpp Differential output Swing 500 mV tsk(p) LVPECL Pulse Skew TBD ns tsk(o) LVPECL Output Skew ≈ 200 ps tr / tf Rise & Fall Time 20% to 80% of Vpp TBD TBD ns

Phase Detector Parameter

fCPmax Maximum Charge Pump Frequency

TBD MHz




14

Charge Pump Parameter

ICP Charge Pump Sink / Source Current

± 0.5 ± 5 ± 10 mA

ICP3St Charge Pump 3 State Current

TBD µA

ICP Absolute Accuracy 20 %

Sink / Source Current Matching

TBD %

ICP vs VCP Matching 0.5V < VCP < VDD-0.5V TBD % Operational Amplifier Parameter

IS Supply Current Conditions? 10 mA Voff Input Offset Voltage 5 mV IB Input Bias Current 200 nA IOS Input Offset Current 70 nA RI Input Resistance 10 MΩ

VCM Common Mode Voltage Input Range

1 VDD V

KOL Open Loop Gain 5 V/mVGBW Gain Band Width 4 MHz SR Slew Rate 1 V/µs

@ RL=10kΩ 0 VDD V VO Output Voltage Swing @ RL=2kΩ 0 VDD V

RO Output Resistance 60 Ω ISC Output Short Circuit Current mA

CMRR Common Mode Rejection Ratio

70 dB

PSRR Power Supply Rejection Ratio

80 dB

en Input Referred Voltage Noise

1kHz 40 nV/ √Hz

in Input Referred Current Noise

1kHz 1 pA/ √Hz

‡ All typical values are at respective nominal VDD † For IDD over frequency see figure 5. ∞ Can be selected by SPI Controller * Below the VPUC Voltage Level the circuit is in RESET Mode. This means all outputs are in 3State, the dividers are reseted and the current sources are powered down. ≈ The tsk(o) specification is only valid for equal loading of all outputs.




15

Application Section – Phase Noise Reference Circuit

PECL_OUT_B

PECL_OUT

V_CTRL

SPI

R10510

R???1k

C51n

R810k

R910k

VCC

R1127k

C60.1u

R71k

C3100nF

CP_OUT

OPA_IP

OPA_IN

OPA_OUT

VCXO_IN

VCXO_IN_B

CTRL_LECTRL_DATACTRL_CLK

REF_IN

Yx_B

Yx

VCC

GND

VCC

NC

STATUS_LOCK

STATUS_VCXO

STATUS_REF

R466

R366

C11nF

C21nF

R750

R5270

R6270

R2200

R1200

C447n

Application Specific Device Characteristics over Recommended Operating Free-Air Temperature Range (unless otherwise noted) PARAMETER VCXO Phase Noise

@245.76MHz MIN TYP‡ MAX Unit

Overall Parameter phn10 Phase Noise @ 10 Hz# -55 dBc/Hz -70 dBc/Hz phn100 Phase Noise @ 100 Hz# -83 dBc/Hz -95 dBc/Hz phn1k Phase Noise @ 1 kHz# -105 dBc/Hz -120 dBc/Hz phn10k Phase Noise @ 10 kHz# -125 dBc/Hz -140 dBc/Hz phn100k Phase Noise @ 100 kHz# -135 dBc/Hz -148 dBc/Hz phn240k Phase Noise @ 240 kHz# -140 dBc/Hz -155 dBc/Hz tstabi PLL Stabilization Time TBD us

# Yx running @ 30.72 MHz




16

Mechanical Data




17

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. This is a preliminary datasheet and the parametric data should be considered as design targets. This data may be subject to change based on device characterization results.

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CDC7005_040

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