CDRS_Stojanovic_Harvard05_slides.pdf

7/25/2019 CDRS_Stojanovic_Harvard05_slides.pdf

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Integrated Systems Group

Massachusetts Institute of Technology

Design of High-Speed Links:A look at Modern VLSI Design

Vladimir Stojanovi


2/59

Integrated Systems Group 2

Chip design is changing

Best systems trade-off circuits, architecture

and system issues

Becoming constrained by power

Not so much by area/density

Pentium 4125M transistors850mW/mm2

90nm tech103W

3.4GHz

Pentium3M transistors30mW/mm2

0.6um tech4W

0.1GHz


3/59


Power-performance system optimization

Complex, many levels of hierarchy and variables


4/59




V. Stojanovi, V.G. Oklobdzija "Comparative Analysis of MS Latches and Flip-Flops

for High-Performance and Low-Power Systems," IEEE Journal Solid-State Circuits, April 1999.

Individual components

Flops & latches(power and timing critical)

D Q

Clk

Logic

D Q

Clk


5/59




Individual components

Flops & latches(power and timing critical)

D Q

Clk

Logic

D Q

Clk

V. Stojanovic, D. Markovic, B. Nikolic, M. A. Horowitz and R. W. Brodersen

"Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization,"

European Solid-State Circuits Conference, September 2002

Vdd1, Vth1

Vdd2,

Vth2

Vdd3,

Vth3

Vdd4,Vth4

Vdd5,

Vth5

System level,VLSI blocks and circuits

-Physical (Vdd,Vth,Sizing)

-Logic-uArchitecture(parallelism, pipelining)

D Q

Clk

Logic A

D Q

Clk

Logic B

D Q

Clk

D Q

Clk

Logic A

D Q

Clk

Logic A

Logic B

Logic B


6/59


Seems pretty simple:

Challenging multi-disciplinary area

Circuits Communications

Optimization

Look at system-level problem: links

Transmitter

Channel

Receiver


7/59


What makes it challenging

Now, the bandwidth limit is in wires

High speed

link chip

> 2 GHz signals


8/59


New link design

Dealing with bandwidth limited channels

This is an old research area Textbooks on digital communications

Think modems, DSL

But cant directly apply their solutions Standard approach requires high-speed A/Ds and digital

signal processing

20Gs/s A/Ds are expensive

(Un)fortunately need to rethink issues


9/59


Outline

Show system level optimization for links Create a framework to evaluate trade-offs

Background on high-speed links

High-speed link modeling

System level optimization

Practical implementation issues

Current / future work


10/59


Backplane environment

Line attenuation

Reflections from stubs (vias)

Back plane connector

Line card trace

Package

On-chip parasitic(termination resistance anddevice loading capacitance)

Line card

via

Back plane trace

Backplane via

Packagevia

Back plane connector

Line card trace

Package

On-chip parasitic(termination resistance anddevice loading capacitance)

Line card

via

Back plane trace

Backplane via

Packagevia


11/59


Backplane channel

Loss is variable Same backplane

Different lengths Different stubs

Top vs. Bot

Attenuation is large >30dB @ 3GHz

But is that bad?

Required signal amplitudeset by noise0 2 4 6 8 10

-60

-50

-40

-30

-20

-10

0

frequency [GHz]

Attenuatio

n[dB]

9" FR4,via stub

26" FR4,via stub

26" FR4

9" FR4


12/59


Inter-symbol interference (ISI)

Channel is low pass

Our nice short pulse gets spread out

0 1 2 3

0

0.2

0.4

0.6

0.8

1

ns

puseresponse

Tsymbol=160ps

Dispersion

short latency

(skin-effect,

dielectric loss)

Reflections

long latency

(impedance mismatches

connectors, via stubs,

device parasitics,package)


13/59


ISI

Middle sample is corrupted by 0.2 trailing ISI (from the previoussymbol), and 0.1 leading ISI (from the next symbol) resulting in0.3 total ISI

As a result middle symbol is detected in error

0 2 4 6 8 10 12 14 16 18

0

0.2

0.4

0.6

0.8

1

Symbol time

Amplitude

Error!


14/59


Prior state of high-speed links

Channel

serializer

PLL

dataIn

ref Clk

Driver/

Equalizer Data Slicer

deserializer

dataOut

Clock, data

recovery

Links components well developed Fast multiplexed transmitters and receivers

Precise timing generation and data recovery

Starting to use equalization (1 2 taps)

Few taps set manually at the transmitter


15/59


Barriers to improving link performance

No good link system and noise models

Cannot predict the right architecture for a givenset of channels

Need to make performance/power tradeoff

Maximum achievable data rates unknown Limited link communication system design

Peak power constraint in the transmitter

No solution for optimal transmit equalization

No solution for automatic equalization


16/59


Previous system models

Mostly non-existent

Borrowed from computer systems Worst case analysis

Can be too pessimistic in links

Borrowed from data communications

Gaussian distributions Works well near mean

Often way off at tails

ISI distribution is bounded

Need accurate models

To relate the power/complexity to performance


17/59


How bad is Gaussian model?

0 25 50 75 100

-10

-8

-6

-4

-2

0

residual ISI [m V ]80 100 120 140 160 180

-10

-8

-6

-4

-2

0

40mV error @ 10-10

25% of eye height

4% Tsymbol

error @ 10-1 0

9% Tsymbol

log10

pro

ba

bility

[cdf]

log10

Stea

dy-S

tatePhase

Pro

bability

phase count

Cumulative ISI distribution Impact on CDR phase

Gaussian model only good down to 10-3 probability

Way pessimistic for much lower probabilities


18/59


A new model

Use direct noise and interference statistics

Main system impairments

Interference

Voltage noise (thermal, supply, offsets, quantization)

Timing noise always looked at separately

Key to integrate with voltage noise sources

Need to map from time to voltage


19/59


Effect of timing noise

Idealsampling

Jitteredsampling

Voltage noiseVoltage noise

when receiver

clock is off

The effect depends on the size of the jitter, theinput sequence, and the channel

Need effective voltage noise distribution


20/59


kb

kT

TX

k

Tk )1( +

TX

k 1+ kT

TX

k

Tk )1( +

TX

k 1+

+

kb

kb

kb

1

2

TXkkb

TX

kkb

1+

Example: Effect of transmitter jitter

Decompose output into ideal and noise

Noise are pulses at front and end of symbol

Width of pulse is equal to jitter

Approximate with deltas on bandlimited channels

ideal

noise

V. Stojanovi, M. Horowitz, Modeling and Analysis of High-Speed Links,

IEEE Custom Integrated Circuits Conference, September 2003. (invited)


21/59


Jitter effect on voltage noise

Transmitter jitter High frequency (cycle-cycle) jitter is bad

Changes the energy (area) of the symbol

No correlation of noise sources that sum

Low frequency jitter is less bad Effectively shifts waveform

Correlated noise give partial cancellation

Receive jitter Modeled by shift of transmit sequence Same as low frequency transmitter jitter

Bandwidth of the jitter is critical It sets the magnitude of the noise created

kRx

kRx


22/59


Jitter source from PLL clocks

Noise sources

Reference clock phase noise

VCO supply noise Clock buffer supply noise

M. Mansuri, C-K.K. Yang, "Jitter optimization based on phase-locked loop design parameters,"

IEEE Journal Solid-State Circuits, Nov. 2002

RefClkPhase

detectorKpd

Icp

Icp R

C

VCO

Kvco/s

Clock

buffer

N

+

105

106

107

108

109

1010

-30

-20

-10

0

10

frequency [Hz]

No

ise

tran

sfer

func

tions

[dB]

fromVCO supply

from

input clockfrom

clock buffer supply

E. Alon, V. Stojanovic, M. Horowitz Circuits and Techniques for High-Resolution Measurement

of On-Chip Power Supply Noise, IEEE Symposium on VLSI Circuits, June 2004.


23/59


Slicer

PD

deserializer

PLL

dataOut

ref Clk

Phase

control

Phase

mixeredge Clk

data Clk

2x Oversampled bang-bang CDR

Generate early/late from dn,dn-1,en Simple 1st order loop, cancels receiver setup time

Now need jitter on data Clk, not PLL output

Base linear PLL jitter

Add non-linear phase selector noise from CDR

dn-1

dn

en (late)

dnen


24/59


0 50 100 150 200 250

-15

-10

-5

0

Phase Count

log10

Stead

y-S

tatePro

bability

Bang-bang CDR model

Gives the probability distribution of phase

Which is the CDR jitter distribution

Model CDR loop as a state machine Markov chain

i

1i

1+i

iholdp ,

iupp ,

idnp ,

A.E. Payzin, "Analysis of a Digital Bit Synchronizer," IEEE Transactions on Communications , April 1983.


25/59


Outline





Limits What is the capacity of these links?

Improving todays baseband signaling




26/59


Baseline channels

Legacy (FR4) - lots of reflections

Microwave engineered (NELCO)

0 5 10 15 20

-100

-80

-60

-40

-20

0

Attenu

ation

[dB]

frequency [GHz

26" FR4,via stub

26" NELCO,no stub

(b)


27/59


Capacity with link-specific noise

Effective noise from phase noise Proportional to signal energy

Decreases expected gains

Still, capacity much higher than data rates in todays links

NELCO FR4

-25 -20 -15 -10 -5 00

20

40

60

80

100

120

140

Capacity

[Gb/s]

log10(Clipping probability)

thermal noise

thermal noise and

LC PLL phase noise

thermal noise and

ring PLL phase noise

-25 -20 -15 -10 -5 00

20

40

60

80

100

120

140

Capacity

[Gb/s]

log10(Clipping probability)

therm al noise

thermal noise and LC PLL

phase noise

thermal noise and ring PLL phase noise


28/59


Removing ISI

Transmit and Receive Equalization

Changes signal to correct for ISI

Often easier to work at transmitter

DACs easier than ADCs

Linear transmit equalizer

Decision-feedback equalizer

SampledData

Deadband Feedback taps

TapSelLogic

TxData

Causaltaps

Anticausal taps

Channel

J. Zerbe et al, "Design, Equalization and Clock Recovery for a 2.5-10Gb/s 2-PAM/4-PAM Backplane

Transceiver Cell," IEEE Journal Solid-State Circuits, Dec. 2003.

0eqI

d

outN

outP

d

5050


29/59


Transmit equalization headroom constraint

Transmit DAC has limited voltage headroom

Unknown target signal levels Hard to formulate error or objective function

Need to tune the equalizer and receive comparator levels

0 0.5 1 1.5 2 2.5-25

-20

-15

-10

-5

0

frequency [GHz]

Atten

uation

[dB]

equalized

unequalized

Amplitude of equalized signal

depends on the channel

TxData

Causaltaps

Anticausal taps

Channel

Peak power constraint

O ti i ti l


30/59


Optimization example:

Power constrained linear precoding

Add variable gain to amplify to known target level

Formulate the objective function from error

SINR is not concave in w in general

Change objective to quasiconcave

w P

pow er constraint

precoder channelpulse response

g

noise

ka

ka

ka

ke

222121),( gwwgwgEgwMSE TTT

a ++= PPP

2

2

)11)(11()1()(

+=

wwEwEwSINR

TTTTT

a

T

aunbiased

PIIPP

unbiasedSINR

V. Stojanovi, A. Amirkhany, M. Horowitz, Optimal Linear Precoding with Theoretical

and Practical Data Rates in High-Speed Serial-Link Backplane Communication,

IEEE International Conference on Communications, June 2004


31/59


Optimal linear precoding

Minimize BER

Residual dispersion into peak distortion Reflections into mean distortion

Includes all link-specific noise sources

( )

1..

)11)(11(

15.0maximize

1

2/12

1min

+

=

wts

wwE

offsetwVwd

w TTPD

T

PD

TT

a

PDpeak

T

PIIIIP

PIP

2=wTS0TXw+wTS

0RXw+2

thermal

Still, does this objective really relate to link performance?

Need to look at noise and interference distributions


32/59


Including feedback equalization

Feedback equalization (DFE)

Subtracts error from input

No attenuation

Problem with DFE

Need to know interfering bits

ISI must be causal

Problem - latency in the decision circuit

Receive latency + DAC settling < bit time

Can increase allowable time by loop unrolling

Receive next bit before the previous is resolved

0 2 4 6 8 10 12 14 16 18

0

0.2

0.4

0.6

0.8

1

Symbol time

Amp

litude

Feedback

equalization


33/59


One-tap DFE with loop unrolling

+1

-1

0

1

Pulse response


34/59



+1

-1

0

+1+

-1+

+

1


35/59



+1

-1

0

+1+

-1+

++1-

-1-

-

1


36/59



+1+

-1+

++1-

-1-

-

Instead of subtracting the error Move the slicer level to include the noise Slice for each possible level, since previous value unknownK.K. Parhi, "High-Speed architectures for algorithms with quantizer loops,"IEEE International Symposium on Circuits and Systems, May 1990

D Q1nd

dClk

1| 1 =nn dd

0| 1 =nn dd

dClknx

+

-


37/59


0 20 40 60 80 100 120 140 160-150

-100

-50

0

50

100

150

time [ps]

m

argin[mV]

-30

-25

-20

-15

-10

-5

BER contours

Voltage margin

Min. distance between the receiver threshold and contours

with same BER

0 20 40 60 80 100 120 140 160-150

-100

-50

0

50

100

150

time [ps]

margin[mV]

-30

-25

-20

-15

-10

-5

5 tap Tx Eq 5 tap Tx Eq + 1 tap DFE


38/59


Pulse amplitude modulation

Binary (NRZ)

1 bit / symbol Symbol rate = bit rate

PAM4

2 bits / symbol Symbol rate = bit rate/2

10

11

01

00

1

0


39/59


Multi-level: Offset and jitter are crucial

thermal noise +

offset

thermal noise +

offset+

jitter

To make better use of available bandwidth, need bettercircuits

PAM2/PAM4 robust candidate for next generation links

0 2 4 6 8 10 12 14 16 18 200

5

10

15

20

25

30

Da

tara

te[Gb/s]

Symbol rate [Gs/s]

PAM16

PAM8

PAM4

PAM2

0 2 4 6 8 10 12 14 16 18 200

5

10

15

20

25

30

Symbol rate [Gs/s]

Da

tara

te[Gb/s]

PAM2

PAM4

PAM8

0 2 4 6 8 10 12 14 16 18 200

5

10

15

20

25

30

35

40

45

Da

tara

te[Gb/s]

PAM4

PAM16

PAM8

PAM2

Symbol rate [Gs/s]

thermal noise


40/59


Full ISI compensation too costly

0 2 4 6 8 10 12 14 160

2

4

68

10

12

14

16

18

20

aarae

s

Symbol rate [Gs/s]

PAM16PAM4

PAM2PAM8

0 2 4 6 8 10 12 14 160

2

4

68

10

12

14

16

18

20

Symbol rate [Gs/s]

Da

tara

te[Gb/s]

PAM8

PAM4

PAM2

0 2 4 6 8 10 12 14 160

2

4

68

10

12

14

16

18

20

Symbol rate [Gs/s]

atara

te

s

PAM2

PAM4

PAM8

thermal noise

thermal noise

+ offset

thermal noise

+ offset+ jitter

Todays links cannot afford to compensate all ISI Limits todays maximum achievable data rates


41/59


Outline






Low-cost adaptation

Dual-mode link (hardware re-use)



42/59


Fully adaptive dual-mode link

Reconfigurable dual-mode PAM2/PAM4 link Adaptive equalization

Transmit and receive equalization

DFE with loop unrolling

PAM2/PAM4

2-10Gb/s 0.13m

40mW/Gb/s

V. Stojanovi et al. Adaptive Equalization and Data Recovery in Dual-Mode (PAM2/4)

Serial Link Transceiver, IEEE Symposium on VLSI Circuits, June 2004.

Config Registers

PhaseMixers

CDRLogic PLL

TransmitterReflection

Canceller

Receiver

Backchannel RX

Backchannel TX


43/59


Adaptation with minimum overhead

Adaptive sampler Generates the error signal at reference level

Monitors the link Adjustable voltage and time reference

On-chip sampling scope

Can replace any other sampler - calibration

Tx Data

Channel

tap

updates

dLev

adaptive

sampler

error

Rx data

Adaptive

macro

tap updates

thresholds

CDRedge

aClk dClk eClk

aClk

dClk

eClk


44/59


Equalizer loop

Scale the equalizer - output Tx constraint

Dual-loop adaptive algorithm

Data level reference loop

)()(1 nnwnn xsignesignstepww +=+

0),(1 >=+ nndataLevnn xesignstepdLevdLev

dLevinitdLevmid

dLevend

Initial eye Mid-way equalized Equalized

errorinitp-p

nx

)( nxSign

)( neSign


45/59


Dual loop convergence 4 tap example

Hard to estimate analytically

Experimental results show Both loops are stable within wide range 0.1 10x of relative

speeds

0 50 100 150 200-400

-200

0

200

400

600

800

1000

number of updates

tapwe

ight[mV

]main tap

post1

pre1

post2

0 50 100 150 2000

20

40

60

80

100

number of updates

dLev

[mV]

PAM2, 5Gb/s, 4taps Tx Equalization


46/59


Hardware re-use: Dual-mode receiver

PAM4

thresh(+)

thresh(-)

0

D QD Q

D Q

D Q

D Q

thresh (+)

thresh (-)

in

0

lsb(+)

lsb(-)

msb

prDFE enable

D Q

dClk

dClk

dClk

prDFE enable

prDFE enable

D Q

D Q

D Q

D Q1

0

0

1

0

1

0

1


47/59


D QD Q

D Q

D Q

D Q

thresh (+)

thresh (-)

in

0

lsb(+)

lsb(-)

msb

prDFE enable

D Q

dClk

dClk

dClk

prDFE enable

prDFE enable

D Q

D Q

D Q

D Q1

0

0

1

0

1

0

1

inP

inN

clkthreshII +2 threshII

2

inP

outN

outP

clkclk

outP outN

Q

Q

pre-amp with offset comparator

PAM4

thresh(+)

thresh(-)

0


H d D l d i


48/59


0

PAM2

D QD Q

D Q

D Q

D Q

thresh (+)

thresh (-)

in

0

lsb(+)

lsb(-)

msb

prDFE enable

D Q

dClk

dClk

dClk

prDFE enable

prDFE enable

D Q

D Q

D Q

D Q1

0

0

1

0

1

0

1


H d D l d i


49/59


PAM2 with loop-unrolled DFE tap

D QD Q

D Q

D Q

D Q

thresh (+)

thresh (-)

in

0

lsb(+)

lsb(-)

msb

prDFE enable

D Q

dClk

dClk

dClk

prDFE enable

prDFE enable

D Q

D Q

D Q

D Q1

0

0

1

0

1

0

1


H d D l d i


50/59


PAM2 with loop-unrolled DFE tap Leverage multi-level properties of signals in loop-unrolling

Re-use PAM4 receiver hardware (slicers and CDR)

thresh(+)

thresh(-)

D QD Q

D Q

D Q

D Q

thresh (+)

thresh (-)

in

0

lsb(+)

lsb(-)

msb

prDFE enable

D Q

dClk

dClk

dClk

prDFE enable

prDFE enable

D Q

D Q

D Q

D Q1

0

0

1

0

1

0

1


Improvements with loop unrolling


51/59


Improvements with loop-unrolling

Signal as seen by thereceiver (on-chip scope)

0 50 100 150 200

-100

-50

0

50

100

150

200

[ps]

[mV]

-5

-4.5

-4

-3.5

-3

log10

(voltageprobabilitydistribution)

0 1000 2000 3000 4000

0

0.05

0.1

0.15

0.2

0.25[V]

[ps]

transmit equalized

with one tap DFE

fully transmit equalized

0 1000 2000 3000 4000

0

0.1

0.2

0.3

0.4[V]

[ps]

unequalized

Model and measurements


52/59


Model and measurements

-80-60-40-20020406080

-14

-12

-10

-8

-6

-4

-2

0

log

10(BER)

Voltage Margin [mV]

PAM4, 3taps of transmit equalization, 5Gb/s,

26 FR4 channel

Outline


53/59


Outline







Bridging the gap to link capacity

Other similar system optimizations

Bridging the gap: Multi tone link


54/59


Bridging the gap: Multi-tone link

A. Amirkhany, V. Stojanovic, M.A. Horowitz, Multi-tone Signaling for High-speed Backplane

Electrical Links, IEEE Global Telecommunications Conference, November 2004.

0 2 4 6 8 10 120

2

4

6

8

Nelco 64 Gb/s

bits

/dimens

ion

Multi-tone data rates with thermal noise

FR4 38 Gb/s

GHz



55/59



f

#levels

data0

data1

dataN

Challenge balancing the inter-symbol andinter-channel interference Microwave filter techniques

Custom signal processing

LPF

BPF

BPF

BPF

LPF

ejw1t ejw1t

ejwNt

data0

data1

LPF

BPF

ejwNt

LPF

dataN

LPF

LPF

0 2 4 6 8 10 120

2

4

6

8

Nelco 64 Gb/s

bits

/dimens

ion

Multi-tone data rates with thermal noise

FR4 38 Gb/s

GHz

The Problem ith M lti Mode Fiber


56/59


The Problem with Multi-Mode Fiber

Source - Corning

0 1 2 3 40

0.2

0.4

0.6

0.8

1

0 5 10 15 20 250

0.2

0.4

0.6

0.8

1

0 1 2 3 40

0.2

0.4

0.6

0.8

1

Multi-modal dispersion

Modal dispersion limits the data rates to ~ 3Gb/s/km

Example Fiber Modes


57/59


Example Fiber Modes

-50

5

x 10-5

-5

0

5

x 10-5

-2000

0

2000

-50

5

x 10-5

-5

0

5

x 10-5

0

500

1000

-50

5

x 10-5

-5

0

5

x 10-5

-2000

0

2000

-50

5

x 10-5

-5

0

5

x 10-5

-2000

0

2000

SLMs for Equalization


58/59


MEMS

Spatial Light Modulator

-

-50

5

x 10-5

-5

0

5

x 10-5

0

500

1000

SLM s for Equalization

Optimize to reduce modal dispersion Objective is intensity makes optimization challenging

Shape the E-field projected on the fiber

Lens performs Fourier Transform

SLMs adjust the spatial frequency of the light

dmin

E. Alon, V. Stojanovic, J. M. Kahn, S. Boyd, M. Horowitz

Equalization of Modal Dispersion in Multimode Fiber using Spatial Light Modulators,IEEE Global Telecommunications Conference, November 2004.

Conclusions


59/59


Conclusions

Interfaces are challenging system designs

Good space to explore system level optimization

Optimization leads to novel approaches

Baseband links PAM4 and simple DFE reduce effect of ISI

Low cost adaptive, self calibrating link

Still, far from the capacity of these links Looking into multi-tone to bridge the gap

Multimode fiber optics Leverage multiple propagation modes rather than being

limited

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