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CE01000-3 Operating Systems
Lecture 2Low level hardware support for
operating systems
Overview of lecture
In this lecture we will be looking at low level hardware facilities that are needed to support operating systems
In particular we will look at:
1. How computer system operation requires interrupts and how interrupts are handled
2. How CPU dual mode operation can control which programs can execute which instructions
3. The need to provide mechanisms to protect the CPU, memory and I/O from being used to corrupt the proper operation of the system
4. Direct Memory Access & the memory hierarchy
Computer-System operation is interrupt driven
I/O devices and the CPU can execute concurrently.
So we need a mechanism for the running program to begin I/O and for I/O devices to signal that it has completed whatever I/O has been requested
Each type of I/O device has a piece of hardware called a device controller which controls the operation of the I/O devices.
Each device controller has a local buffer. CPU moves data from main memory to the
local buffer and vice versa. Actual I/O occurs between the device and the
local buffer of controller. Device controller informs CPU that it has
finished its operation by causing an interrupt.
These are the devices that make
up a typical system.
Any of these devices can cause
an electrical interrupt that grabs the attention of the
CPU.
Operating system is interrupt driven
I/O processing High level view of I/O interrupt processing
Interrupt Handling An interrupt is a signal that stops execution of currently
executing program because some other code needs to use the CPU to deal with the request for service
This interrupt may be signal from Hardware
From I/O device – signaling I/O completion From any hardware signaling some fault or problem that needs
dealing with e.g. power low on a laptop Running program itself (software interrupt) – will be
discussed more later
Interrupt Handling (Cont.) The operating system saves the state of the
CPU by saving various working registers and the program counter.
The OS then determines which type of interrupt has occurred by either: Polling Using vectored interrupts
Interrupt Handling (Cont.) Polling involves checking device controller
status registers to see if device needs service and if service required invoking appropriate code
Vectored interrupt system - uses a table of addresses (called vectors) of interrupt service routines (ISRs) - interrupt passes to OS a number which is an index into the table - thus identifies which ISR needs to be executed
Interrupt Handling (Cont.)
Interrupt Service Routine (ISR) - part of OS - carries out appropriate action for each type of interrupt
when ISR has finished the OS either restores the state of CPU (restores saved register
values of program that was interrupted into correct registers in CPU) or
invokes scheduler to determine whether a different program should run next
Interrupt Handling (Cont.) Incoming interrupts are disabled while another
interrupt is being processed to prevent a lost interrupt
However, you can organise interrupts into priority levels, so that interrupts of a higher priority can interrupt interrupts of a lower priority level
Interrupt Handling (Cont.) A trap is a software-generated interrupt caused
either by
1. an instruction executed as part of the running program – it is the means by which the running program can signal the operating system that it needs the operating system to do something for it - how system calls (see later) are ultimately implemented OR
2. a software error (e.g. attempt to divide by zero)
CPU Dual-Mode Operation - the need for it
Why does user program need to ask OS to do things for it?
User programs do not run in isolation but run on system with other programs
System resources need to be shared between these programs and this requires operating system to ensure that one program cannot cause other programs to execute incorrectly. Programs must not interfere with each other
Thus a normal user program must not be allowed to use instructions that could corrupt the proper execution of other programs.
CPU Dual-Mode Operation - what it is
To prevent user programs from executing instructions that might corrupt another user’s programs dual-mode operation was introduced.
CPU needs at least 2 modes of operation:1. User mode – when executing user programs - CPU
only permits execution of subset of its instruction set.
2. Supervisor mode (also called monitor or system mode) – when executing operating system - can execute all instructions.
CPU Dual-Mode - how it works
CPU Dual-Mode - how it works Mode bit added to computer hardware to indicate
the current mode: supervisor (0) or user (1). When an interrupt or fault occurs hardware
switches to supervisor mode - when OS restarts user program it switches it to user mode
instructions that can only be used in supervisor mode are called Privileged instructions.
Only OS runs in supervisor mode
Must ensure that a user program never gains control of the computer in supervisor mode
At system start only OS is running - in supervisor mode just before running a user program OS switches CPU to
user mode user program then runs - in user mode Of course changing mode bit needs to be a privileged
instruction
Only OS runs in supervisor mode
CPU goes into supervisor mode only when an interrupt occurs
When interrupt occurs, user program is halted temporarily and control of CPU is passed to ISR for the interrupt – but ISR is part of OS
Thus only OS runs in supervisor mode
Dual-mode operation implies need for memory protection
BUT what if user program stores the address of part of its own code in an interrupt vector - it can gain control of CPU in supervisor mode.
Thus system memory needs some form of protection
Memory Protection
Must provide memory protection for the interrupt vector and the interrupt service routines - but also user programs and data
One simple mechanism to provide memory protection - add two registers that determine the range of legal addresses a program may access: base register – holds the smallest legal physical
memory address. limit register – contains the size of the range.
Attempt to access memory outside range causes an error interrupt to OS to deal with problem
Example Memory Protection
Memory protection using base/limit registers
Memory protection using base/limit registers
When executing in supervisor mode, the operating system has unrestricted access to all of memory – memory of OS itself and each users’ memory.
The load instructions for the base and limit registers need to be privileged instructions.
CPU Protection
What if a user program goes into an infinite loop? We need something that will enable OS to gain
control of CPU so it can stop running program and start other programs.
Timer – interrupts computer after specified time has elapsed to ensure operating system can maintain control. Timer is decremented every clock tick. When timer reaches 0, an interrupt occurs.
Timer commonly used to implement time sharing.
Timer also used to compute the current time. Loading the timer needs to be a privileged
instruction.
I/O structure a) synchronous I/O b) asynchronous I/O
I/O Structure
Synchronous I/O - after I/O starts, control returns to user program only when I/O completed. CPU waits by executing an instruction that makes
it go idle until next interrupt or goes into a busy loop repeatedly polling device to see if I/O completed.
at most one I/O request is outstanding at a time; no simultaneous I/O processing.
Asynchronous I/O - after I/O starts, control returns to user program without waiting for I/O to complete. This needs a device-status table to contain entries for
each I/O device indicating its type, address, and state Multiple requests for particular I/O can then be queued
(linked list) on the device OS indexes into device table to determine device status
Device status table
I/O Protection
To prevent one user program from interfering with the output or input of data that belongs to another user program all I/O instructions are privileged instructions.
System calls
Given that I/O instructions are privileged, how does the user program perform I/O?
System call – this is the method used by a running program to request action by the operating system. Usually takes the form of a trap (software
interrupt) – we met these earlier
The trap (software interrupt) will provide an interrupt vector to identify the interrupt service routine (ISR) required, the mode bit will then be set to supervisor mode and ISR begins execution.
The running program passes information to OS about the exact service it requires via parameters to system call
OS verifies that this information (parameters) are correct and legal, executes the request, and returns control to the instruction following the system call.
System call sequence
Direct Memory Access (DMA)
Direct Memory Access (DMA) Direct Memory Access is used for high-speed
I/O devices able to transmit information at close to memory speeds.
Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention - uses cycle stealing
Only one interrupt is generated per block of data, rather than the one interrupt per byte.
Memory Structure
Main memory – only large data area that the CPU can access directly - but volatile not large enough to hold all data/programs
Secondary memory – extension of main memory that provides large nonvolatile storage capacity
Memory Hierarchy
Storage systems organized in hierarchy: higher levels give more speed, but at greater cost
and with greater volatility
Storage-Device Hierarchy
Caching principle Caching principle – maintaining a copy of some
of the information from a slower storage medium on a faster medium; information held in cache is that currently being used.
main memory can be viewed as a fast cache for secondary memory problem - to provide mapping between copy and
original information and maintain consistency between them both
References Operating System Concepts. Chapter 1.