CEDARCounter-Estimation Decoupling for

Approximate Rates

Erez Tsidon

Joint work with Iddo Hanniel and Isaac KeslassyTechnion, Israel

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Network Flow Counters Usage

Network management applications require per-flow counters, for example: Congestion Control Detection of Denial of Service Attacks Detection of Traffic Anomalies

Counter types: Packet counting Byte counting Rate measurement

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Switch Example

DRAM is too slow, SRAM is too expensive

3

106 flows

Total Packet CountTotal Byte CountPacket RateCount event ACount event B

per-flow counters

64-bit width

High Speed Link Rate 10Gbps

Time frame of each packet is too short for DRAM access

Too much data to store on SRAM

Suggested Solutions

Hybrid SRAM-DRAM counters [Shah, Iyer, Prabhakar and McKeown ’02] Cannot support fast reading

Counter Braids – compress counters into small SRAM [Y. Lu et al ’08] Cannot decompress in real time

Heavy Hitters – store only high counters [Estan and Varghese ’03] No records of small counter values

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Counter Estimation Solutions

Probabilistic way to estimate counters Less bits per counter, but estimation error cost

Intuitively we want counters to be as precise as possible, unbiased whenever possible, and scalable

SAC – R. Stanojevic, “Small Active Counters”, 2007 Exponent-Magnitude representation ScalableRestricted to specific representation that

prevents error optimization DISCO – C. Hu et al, “DISCO: Memory Efficient and Accurate Flow

Statistics for Network Measurement”, 2010 Convex conversion function that reduces increment valuesRestricted to a close function representation. No

scaling

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Our Contributions

New CEDAR architecture: decoupling counters from estimators

Optimal estimators for the min-max relative error

Dynamic up-scale algorithm

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CEDAR Architecture:Counter-Estimators Decoupling

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995,784

1.2

1,000,000

1.2

Counter estimates

FN-1

FN-2

F1

F0

1,000,000

995,784

1.2

0

p(L-2)

p(1)

p(L-1)

p(1)

AL-1

AL-2

A1

A0

3.7 A2

Flow pointers

Shared estimators

FN-1

FN-2

F1

F0

01

4 4

CEDAR Increment Algorithm

941

A3

A2

A1

0A0

21113254.711

A7

A6

A5

A4

9410

21113254.711

9410

21113254.711

9410

21113254.711

time

p=1

p=1/3p=1/5

t=0 t=1 t=2 t=3

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Upon packet arrival: with probability1j jF F 1

1

j jF F

pA A

Performance Measures

Traffic Amount : random variable that represents the number of real counter increments until we hit estimator

Relative error:

Known as “Coefficient of Variation” E.g. we may want a relative error of 1%

( )T a

X̂ a

9

2

( ) ( )( )

( ) ( )Var T a T a

T aE T a E T a

Min-Max Relative Error

Problem: given AL-1=M, find an estimation array that minimizes the maximal relative error δ such that:

Equivalently: δ is given maximize M Solution – equal relative error:

, ( )ll T A

10 , ( )ll T A

1

21

01 2

1 2

1

l

i ii

l l

A AA A

Equal Relative Error Example

11Estimation Values

Relative Error

δ

δ

A1 A2 A3

A1 A2 A3

δ

A1 A2 A3

Capacity Region of Static CEDAR

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Example:• 12-bit counters• Max value 10^6min-max relative error 3%

4.5

1

Up-Scale Procedure

3

1

A3

A2

A1

0A0

211

132

54

11

A7

A6

A5

A4

24

5

2

0

517

314

156

93

54

11

p=0.5 0

p=0.43=(54-24)/(93-24)

93

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A’ A’’

Up-scalethreshold

Initial relative error δ0

Increase the relative error

δ0+ δstep

CEDAR Unbiasedness

14Based on a real Internet trace. δ0 = 1%, δstep = 0.5%

CEDAR Equal Error

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CEDAR Vs. SAC & DISCO 12-bit

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4096 estima

tors

CEDAR Vs. SAC & DISCO 8-bit

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256estima

tors

CEDAR Error Adjustment 12-bit

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CEDAR Implementation on FPGA

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5.4 Gbps

12K gates

CEDAR Summary

Decoupling flexible estimators Scalable estimation Attains the min-max relative error FPGA supports link rate of 5.4Gbps and may

increase to tens of Gbps on ASIC

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Thank you.

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