Ch7_Sequential1

8/10/2019 Ch7_Sequential1

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Chapter 7

Sequential Circuits

Boonchuay Supmonchai

Integrated Design Application Research (IDAR) Laboratory

August 20, 2004; Revised - July 4, 2005


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2102-545 Digital ICs Sequential Logic 2

Goals of This Chapter

Implementation techniques for Register: latches and flipflops

Schmitt Triggers

Oscillator, pulse generators

Static versus Dynamic Realization

Clocking Strategies


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Storage Mechanisms

Positive Feedback Charge-Based

COMBINATIONAL

LOGIC

Inputs Outputs

Next stateCurrent State

Q D

State

Register

CLOCK

Sequential Logic

STATIC DYNAMIC


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Static vs Dynamic Storage

Static storage preserve state as long as the power is on

have positive feedback (regeneration) with an internal

connection between the output and the input

useful when updates are infrequent (clock gating)

Dynamic storage

store state on parasitic capacitors

only hold state for short periods of time (milliseconds)

require periodic refresh

usually simpler, so higher speed and lower power


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Latches versus F lipflops

Latches (with Clock) level sensiti vecircuit that passes inputs to Q when the clock is

high (or low) - transparent mode

input sampled on the falling edge of the clock is held stable

when clock is low (or high) - hold mode

Flipflops (edge-triggered)

edge sensiti vecircuits that sample the inputs on a clock

transition

positive edge-triggered: 01

negative edge-triggered: 10

built using latches (e.g., master-slave flipflops)


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Vi2 Vo2Vo1Vi1

Cascaded Inverters

A

Vi1 = Vo2

B

C

Review: The Regenerative Property

Small deviation frombias point C(e.g., fromnoise) is amplified andregenerated around the

circuit loop until eitherpoint Aor Bis reached

If the gain in thetransient region is larger

than 1, only Aand Barestable operation points.Cis a metastableoperation point.


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Review: Bistable Circuits

The cross-coupling of twoinverters results in abistable circui t(a circuitwith two stable states)

Have to be able to changethe stored value by making A

(or B) temporarily unstable by increasing the loop gain

to a value larger than 1

done by applying a trigger pulse at Vi1or Vi2

the width of the trigger pulse need be only a little larger than

the total propagation delay around the loop circuit (twice the

delay of an inverter)

Vi1

Vi2


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Review: SR Latch

S R Q !Q Action

0 0 Q !Q memory

1 0 1 0 set

0 1 0 1 reset

1 1 0 0 disal lowed

S

RQ

!Q


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Review: Clocked D Latch

clock

QD

clock

D

Q

!Q

clock

t ransparentmode

holdmode

In our courseAll latches mean

clocked latches


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D

Clk

Q D

Clk

Q

Flipflopstores data when

clock r ises (fal ls)

Clk

D

Q

Clk

D

Q

Latches versus F lipf lops I I

Latchstores data when

clock is low (h igh)


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Positive and Negative Latches

In

Out

Clk

Out

StableOut

Follow In

Out

Stable

Out

Follow In

D Q

G

I n Out

Clk

Positive Latch

In

Out

Clk

Out

Stable

Out

Follow In

Out

StableOut

Follow In

D Q

G

I n Out

Clk

Negative Latch


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N latch is transparentwhen = 0

P latch is transparentwhen = 1

Latch-Based Design

N

Latch

P

LatchLogic

Logic


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clock

Out outputstable

output

stable

time

clock

In datastable

time

time

tsu thold

tc-q

Timing Metrics


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Timing Defini tions

Setup time, tsetupis the time that the data inputs(D) must be valid before the clock transition

0 to 1 transition for a positive edge-triggered device

1 to 0 transition for a negative edge-triggered device

Hold time, tholdis the time that the data inputsmust remain valid after the clock edge

Propagation Delay, tc-qis the worst casepropagation delay (with reference to the clockedge)

time to copy D to Q


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T tc-q+ tplogic+ tsutcdreg+ tcdlogicthold

T (clock period)

System Timing Constraints

COMBINATIONAL

LOGIC

Inputs Outputs

Next stateCurrent State

Q D

State

Register

CLOCK

tcd: contamination delay = minimum delay


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Notes on System Timing Constraints

It is important to minimize the values of the timingparameters associated with the register.

In modern high-performance systems, the register

propagation delay and set-up times account for a

signi f icant portionof the clock period.

DEC Alpha EV6 has a maximum logic depth of 12 gates and

the register overhead accounts for about 15% of the clock

period.

Hold time becomes an issue when there is little logic

between registers or when the clocks at different

registers are somewhat out of phase due to clock skew.


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Bui lding A (Static) Latch

CLK

CLK

CLK

D

Q

Cutt ing the feedback loop

(Mux -based latch)

Overpowering the feedback loo p

(as in Static RAM)

For a latch, use the clock as a decoupling signal, thatdistinguishes between the transparent and opaque states

D

CLK

CLK

D

can implement as NMOS-only


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Q = !clk & Q | clk & DQ = clk & Q | !c lk & D

Negative Latch

Q

D

clk

0

1

feedback

t ransparentwhen the

clock is low

Change the stored value by cutting the feedback loop

MUX Based Latches

Posit ive Latch

Q

D

clk

1

0

feedback

t ransparentwhen the

clock is high


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!clk

clk

input sampled

(t ransparentmode)

feedback

(ho ldmode)

TG MUX Based Latch Implementation

Q

D

clk

clk

!clk

Posi t ive Latch

c lkload is twotransistors (and twofor !c lk) = clock load of 4

Having to generate both c lkand !clk

(nonoverlapping clocks)


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QD

clk !Q

!clk

Reduced clock load, bu tthreshold drop at output of

pass trans is tors so reduced

noise margins and per formance

PT MUX Based Latch Implementation

!clk

clk

input sampled

(t ransparentmode)

feedback

(ho ldmode)


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clk

T tc -q+ tplog ic+ tsu

Thigh tc-q+ tcd log ic

clk

B BB

Which value of B is stored?

Latch Race Problem

Two-sidedclock constraint


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clk

QM

Q

D

clk

QD

clk = 0 transparent hold

clk = 1 hold transparent

0

1 Q1

0

D

clk

Q

clk

SlaveMaster

QM

Master Slave Based ET F lipf lop


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T1

T2 Q

D

clk

QM

I1

I2 I3

I4

I5 I6

T3

T4

MasterSlave

!clk

clk

master t ransparentslave hold

master holdslave t ransparent

20 Transistors*

8 clock loads* Ignore clk b uffer

MS ET Implementation


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Assume propagation delays are tpd_invand tpd_tx, that thecontamination delay is 0, and that the inverter delay to

derive !clkis 0

Set-up time- time before rising edge of clkthat Dmust

be valid

Propagation delay- time for QMto reach Q

Hold time- time Dmust be stable after rising edge of clk

MS ET Timing Properties

tsu= 3 * tpd_inv+ tpd_tx

tpd= tpd_inv+ tpd_tx

thold= 0


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Notes on MS ET Timing Properties

Set-up time

How long before the rising edge does D have to be stable suchthat QMsamples the value reliably?

D has to propagate through I1, T1, I3 and I2 before the risingedge to ensure that the node voltages on both terminals of T2

are the same value.

Propagation delay time

Since the delay of I2 is included in the set-up time, the outputof I4 is valid beforethe rising edge of clk, so the delay is

simply the delay through T3 and I6

Hold time

since T1 turns off when the clock goes high, any changes in Dafter clk goes high are not seen, so hold time is 0


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Set-up Time Simulation

D clk

QM

I2out

tsetup= 0.21 ns

works correct ly

Vo

lts

Time (ns )

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Q


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Set-up Time Simulation I I

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1

Vo

lts

Time (ns )

D clk

QM

I2out

tsetup= 0.20 ns

Q

the clock is enabled before the nodes on both sides

of the transmission gate T2 settle to the same valueFails!


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Propagation Delay Simulation

tc-q (LH)= 160 psec tc-q (HL)= 180 psec

-0.5

0

0.5

1

1.5

2

2.5

3

0 0.5 1 1.5 2 2.5

Volts

Time (ns )

tc-q(LH) tc -q(HL)

prop agation delay is measured from the 50% point

of the clk edge to the 50% point of th e Q output

DClk Q


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Reduced Load MS ET FF

!clkclk

QD

!clk clk

I1

I2I4

I3

QM T2

T1

Clock load per register is important since it directly

impacts the power dissipation of the clock network.

Can reduce the clock load (at the cost of robustness) by

making the circuit ratioed

to switch the state of the master, T1must be sized to overpowerI2 to avoid reverse conduction, I4must be weakerthan I1

reverse conduct ion

12 Transistors4 clock loads


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Non-I deal Clocks

!clk

clk

Ideal clocks

!clk

clk

Non-Ideal clocks

1-1 Overlap 0-0 Overlap

Clkand !clkare never perfect inversions of one another

We must generate !clkand route both signals

Variations can exist in the wires used to route the two clocksignals and load capacitances may vary

Non-ideal clocks create skewresulting in clock overlap


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!QD

clkX

!clk

!clk Q

clk

B

AP1

P2

P3

P4

I1 I2I3 I4

Race conditiondirect path from D to Q during the short time

when both clk and !clk are high (1-1 ov erlap)

Undefined stateboth B and D are driving A when clk and !clk

are both high

Dynamic storagewhen clk and !clk are both low (0-0 ov erlap)

Race

Example of Clock Skew Problems


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clk1

clk2

mastert ransparent

slaveho ld

master hold

slave t ransparent

dynamic

storage

tnon_overlap

Pseudostatic Two-Phase ET FF

!QD

clk1X

clk2

clk2 Q

clk1

B

AP1

P2

P3

P4

I1 I2I3 I4


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Two Phase Clock Generator

clk

clk1

clk2

A

B

clk

A

B

clk1

clk2


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!clk

clk

Power PC F lipf lop

mastert ransparent

slavehold masterho ld

slavet ransparent

1

1 0

1 1

D Q

clk

!clk

!clk

clk

0 0 0

1

16 Transistors

8 clock loads


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S

Q

Q

Cross-coupled NANDs

This is no t used in datapaths any m ore,

but is a basic bui ld ing block for m emory cel l

Overpower ing The Feedback Loop

Clocked SR Latch

SR

clkclk

!Q

Q

M1

M2

M3

M4

M5

M6

M7

M8


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10

onoff

off ->onoff ->on

0

1

on

on

off

off

1

0

on

off

off

onS

R

clkclk

!Q

Q

M1

M2

M3

M4

M5

M6

M7

M8 0101

Ratioed CMOS Clocked SR Latch

8 Transistors

2 Clock loads** sized

No static power consumption, but a ratioeddevicewhere sizing is critical to ensure proper functionality

M7, M8 must overcome M4 to bring Q low, so must M5, M6over M2


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Sizing I ssues

0

0.5

1

1.5

2

2 2.5 3 3.5 4

(W/L)5 and 6

!Q(

Vo

lts)

(W/L)2 and 4 = 1.5m/0.25 m(W/L)1 and 3 = 0.5m/0.25 m

so (W/L )5 and 6> 3

Output vo l tage depends on pul l -down trans is tor width


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Transient Response

S

0

1

2

3

0 0.4 0.8 1.2 1.6 2

!Q(

Volts)

Time (ns)

W=1 mW=0.9 m

W=0.8 m

!Q

W=0.5 m

W=0.6 mW=0.7 m

Individual device ratio for M5 or M6 must be largerthan approx. 6.

Analysis results give 2.26 (instead of 3) since it doesnt take into account

channel length modulat ionand DIBL (drain ind uced b arr ier loading).

B S h i


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clkclk

SR

M1

M2

M3

M4

M5

M6 S

R

clk

!Q

Q

clk

6 Transistor CMOS SR Latch

6 Transistors

2 Clock loads

Problems with noisemarginsand staticpower consumptiondue to threshold dropacross pass transistors

Once again, sizing isimportant - especiallyM5 and M6

B S h i


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Review: Storage Mechanisms

D

CLK

CLK

Q

Dynamic(charge-based)

CLK

CLK

CLK

D

Q

Static(Positive Feedback)

Useful when update is infrequent Simpler, Faster, and Lower Power

B S h i


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!clk clk

T1 T2I1 I2 Q

QMD

C

1

C

2clk !clk

!clk

clk

mastert ransparent

slavehold

masterhold

slavet ransparent

master slave

tsu=

thold=

tc -q

=

tpd_txzero2 t

pd_inv+ t

pd_tx

Dynamic ET F lipf lop

8 Transistors

4 Clock loads

B S h i


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0-0 overlaprace condition

toverlap0-0< tT1+ tI1+ tT2

1-1 overlaprace condition

toverlap1-1 < thold

Dynamic ET FF Race Conditions

!clk clk

T1 T2I1 I2 Q

QM

D

C

1

C

2clk !clk

!clk

clk

B Supmonchai


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clk2

clk1 tnon_overlap

master t ransparent

slave hold

master hold

slave t ransparent

Dynamic Two-Phase ET FF

clk1 clk2

T1 T2I1 I2 Q

QM

D

C

1

C

2!clk1 !clk2

B Supmonchai


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Pseudostatic Dynamic Latch

Robustness considerations limit the use of dynamic FFs

Coupling between signal nets and internal storage nodes caninject significant noise and destroy the FF state

Leakage currents cause state to leak away with time

Internal dynamic nodes dont track fluctuations in VDD that

reduces noise margins

A simple fix is to make the circuit pseudostatic

clk

T1D

!clk

Slight in crease in delay

(adds to the capacit iveload) and power

consump t ion, but i t

improv es noise immuni ty

signi f icant ly

B Supmonchai


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clk

!clk

!clk

clk

QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

Master Slave


master hold

slave t ransparent

on

on

off

off

on

onoff

off

C2MOS (Clocked CMOS) ET F lipf lop

!clk

clk

8 Transistors

4 Clock loads

Insens i t ive to cloc k

over lap as long as the

r ise and fall t imes of

the clock edges are

suff ic ient ly smal l

B Supmonchai


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C2MOS FF 0-0 Over lap Case

0 0QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

!clk

clk

!clk

clk

B Supmonchai


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Notes on C2MOS FF 0-0 Overlap Case

Does any new data sampled during the overlap window

propagate to Q (race)?

New data is sampled on QM, but cannotpropagate to Q sinceM7 is off (slave is in hold).

Any new data sampled on the falling clock edge is not seen at Q

For clocking on the left: at the end of the overlap period!clk= 1 and both M7 and M8 turn off, putting the slavein the hold mode

For the clocking on the r ight: at the end of the overlapperiod clk= 1 and both M3 and M4 turn off, putting themaster in the hold mode (affects setup time as well)

The result: the FF is slower(slower tc-qtime)

B Supmonchai


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!clk

clk

!clk

clk

1-1 overlapconstraint: toverlap1-1 < thold

11

QM

C1 C2

QD

M1

M3

M4

M2 M6

M8

M7

M5

C2MOS FF 1-1 Over lap Case

B Supmonchai


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Notes on C2MOS FF 1-1 Overlap Case

New data is sampled on QM, but cannot propagate to Q

since M8 is off (slave is in hold).

A bit more problematic than 0-0 overlap.

It must enforce a hold timeon D, so that changing D whichreaches QM is not copied to Q when overlap time is over -

f irst clocking condition.

By imposing a hold time on D - that D must be stable duringclock overlap - overcome this problem as well

However, possible race can occur if the rise/fall times ofthe clock are sufficiently slow.

Works correctly as long as the clock rise/fall times is smallerthan approximately five timesthe propagation delay of theflipflop.

B.Supmonchai


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C2MOS Transient Response

Q(3)

Q(0.1)

-0.5

0

0.5

1

1.5

2

2.5

3

0 2 4 6 8

Time (nsec)

clk(0.1 ns)

QM(3)

clk(3 ns)

For slow clocks, potent ial for a race condi t ion exists

B.Supmonchai


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clk clkIn

Q

Positive LatchNegative Latch

t ransparentwhen clk = 1

ho ldwhen clk = 0

clk clkIn Q

ho ldwhen clk = 1

t ransparentwhen clk = 0

True Single Phase Clocked (TSPC) Latches

Uses only a single clock

No clock over lap (skew)to worry about ; reduced clock load

B.Supmonchai


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p


clk clkIn

Q

PUN

PDN

clk clk

A

Q

B

BA

Embedding Logic in TSPC Latch

Logic can be embedded into latch (or FF)

Reduce delay overhead associated wi th the latch

A AND B

B.Supmonchai


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p


Notes on Embedding Logic in TSPC Latch

Set-up time increased, but overall performanceimproved

The increase in the set-up time is typically smallerthan the

delay of an AND gate.

For example, using minimum size devices set-up of ANDlatch is 140 psec.

Using the conventional approach of AND gate followed by

latch has an effective set-up time of 600 psec.

Technique used extensively in the design of the EV4DEC Alpha microprocessor and many other high

performance processors.

B.Supmonchai


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p


master hold

slave t ransparent


ononoffoff

on on

off

off

clk clkD

Master Slave

clk clkQQM

clk

12 Transistors

4 Clock loads

TSPC ET FF

Vir tual ly al l constraints remo ved - no cloc ks to over lap, no race

B.Supmonchai


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Notes on TSPC ET FF

Warning!- similar to C2

MOS, TSPC flipflopsmalfunction when the slope of the clock is not

suff iciently steep.

Slow clock cause both the NMOS and PMOS

clocked transistors to be ON simultaneously,

resulting in undefined values of the states and race

conditions.

Clock slopes thus must be carefully engineered. Ifnecessary, local buffers must be introduced to ensure

the quality of the clock signal

B.Supmonchai


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clkD clkQ

clk

clk

X

Y

M1

M2

M3 M6

M5

M4 M7

M8

M9

I1 I2 I3

Simpli f ied TSPC ET FF

I1 hold

I2 evaluate

I3 samp le (transp arent)

I1 sample (transparent)

I2 precharged

I3 hold

onoff

on

off

D

D

clk

on

on

off

off

1

!D

9 Transistors*

4 Clock loads

*(11 if Q is needed)

B.Supmonchai


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Notes on TSPC ET FF

On the positive edge of the clock, note that the node Xtransitions to a low if D is high. Therefore, the input

must be kept stable until the value on node X before the

rising edge of the clock propagates to Y

Hold time of the register (less than 1 inverter delay since ittakes 1 inverter delay for the input to affect node X).

Propagation delay is essentially three inverters since

the value on node X must propagate to output Q

Set-up time is the time for node X to be validone

inverter delay

B.Supmonchai


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Sizing Issues in Simplif ied TSPC ET FF

0

1

2

3

0 0.2 0.4 0.6 0.8 1

Time (nsec)

clk

!Qorig

Qorig

!Qmod

Qmod

Transistor sizing

Original width

M4, M5= 0.5m

M7, M8= 2m

Modified width

M4, M5= 1m

M7, M8= 1m

Sizing is cr i t ical w ith improper s izing gl i tches may occu r due

to race condi t ion w hen the clock trans i t ions from low to h igh

B.Supmonchai


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Positive Latch Negative Latch

t ransparentwhen clk = 1holdwhen clk = 0

holdwhen clk = 1t ransparentwhen clk = 0

clk

In

Q

A

clkIn Q

A

When In= 0, A= VDD- VTn When In= 1, A= | VTp |

Spli t-Output TSPC Latches

B.Supmonchai


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Spli t-Output TSPC ET FF

8 Transistors*

2 Clock loads*(10 if Q is needed)

Which edge-triggered?

Downside is not all node voltages in the latch experiencefull logic swing due to threshold drop.

E.g., for positive latch when D=0 and clk=1, A=Vdd-Vth (Also

limits the amount of Vddscaling possible with this latch).

clkDQ

clkQM

A

B.Supmonchai


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Master-Slave Flipflop Pulse-Triggered Flipf lop

D

Clk

Q D

Clk

Q

Clk

Data

L1 L2

Pulse-Tr iggered F lipf lops

Another approach to design an edge-triggeredflipflop is to use pulse-triggered.

LData

D

Clk

Q

Clk

B.Supmonchai


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0 ONVdd

OFF OFF

11 0 ON

Xclk

D

Q

M1

M2

M3

M4

M5

M6

P1

P2

P3

!clkd

1/0ON/

OFF

0/Vdd ON/OFF

1/0

0OFF

1

1

OFF

ONON

ON

Pulsed FF (AMD-K6)

Pulse registers - a short pulse (glitch clock) is generatedlocally from the rising (or falling) edge of the system

clock and is used as the clock input to the flipflop

B.Supmonchai


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Notes on Pulsed FF

Race conditions are avoided by keeping the transparentmode time very short(during the pulse only)

Reduce clock load but substantially increase complexityin verification

The transparency period determines the hold time. The window must be wide enoughfor the input data to

propagate to Q.

The set-up time can be NEGATIVE(if the transparency

window is longer than the delay from input to output). This is attractive, as data can arrive at the register even after

the clock goes high, meaning that time can be borrowed fromthe previous cycle.

B.Supmonchai


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0

0

1

1

1

1

1

0

1

0

1

Sense Amp FF (StrongArm SA100)

Sense amplif ieris a circuit that accept small swing inputsignals and amplify them to full rail-to-rail signals

clk

D

Q

!Q

M1

M2

M3

M5

M6

M4

M9

M7

M8

M10

!S

!R

X

Y

B.Supmonchai


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Notes on Sensed Amp FF

The key is transistor M4(in the middle of Sensed amp);

it delays signals that pass through to the other side of itsterminal, making the change on the other side slower

When D = 1, Y changes after X due to the delay of M4. By thetime M6 reacts to the change at its terminal, it is already

turned off by the terminal voltage at M4 (a 0). Thus, M6holds a 1.

M4 also provides DC-leakage path to ground for eithernode X or Y in case that the inputs change their valueafter the positive edge of CLKarrives.

Advantages are reduced clock loadand that it can beused as a receiver for reduced swing differential buses

Where does the differential signal enter?

B.Supmonchai


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F lipf lop Compar ison Chart

Name Type #clk ld #tr tset-up thold tpFF

Mux Static 8(clk-!clk) 20 3tpinv+tp tx 0 tpinv+tp tx

PowerPC Static 8 (clk-!clk) 16

2-phase Ps-Static 8(clk1-clk2) 16

T-gate Dynamic 4(clk-!clk) 8 tp tx to1-1 2tpinv+tp tx

C2MOS Dynamic 4(clk-!clk) 8

TSPC Dynamic 4(clk) 11 tp inv tp inv 3tp inv

S-O TSPC Dynamic 2(clk) 10

AMD K6 Dynamic 5(clk) 19

SA 100 SenseAmp 3(clk) 20

B.Supmonchai


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Choosing a Clocking Strategy

Choosing the right clocking scheme affects the

functionality, speed, and powerof a circuit

Two-phase designs

+ robust and conceptually simple

- need to generate and route two clock signals

- have to design to accommodate possible skew between thetwo clock signals

Single phase designs

+ only need to generate and route one clock signal + supported by most automated design methodologies

+ dont have to worry about skew between the two clocks

- have to have guaranteed slopes on the clock edges

B.Supmonchai


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Non-Bistable Sequential Circuits

Previously, we have defined a circuit having twostable states a bi-stable circuit

Other regenerative circuits, which are non-bistable:

Monostable

Only one stable state -> Pulse generators, One-shot circuits

Astable

No stable states -> Oscillator, On-chip clock generator

Schmi tt Tr igger

A special regenerative circuit exhibiting hysteresisin VTC.

B.Supmonchai


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In Out

Schmitt Tr igger

Non-Bis table Sequential Circui ts

Vin

Vout

VOH

VOL

VM

VM+

2 important properties

Hysteresis

Fast Trans it ion Time

at the output

B.Supmonchai


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Noise Suppression using Schmitt Tr igger

VIN

t0 t

VM+

VM-

VOUT

tt0+ tp

Example: Switch Debouncer

B.Supmonchai


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CMOS Schmitt Tr igger

M1

M4M2

M3

VIN VOUTX

VDDMoves switchingthreshold of the

first inverter

Adapting the rat io between PMOS and NMOS, depending upo n the

direct ion of the trans i t ion resul ts in a shi f t in swi tch ing threshold

Low-to-High

ref f= kM1/(kM2+ kM4)

High-to-Low

ref f= (kM1+ kM3)/kM2

B.Supmonchai


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Schmitt Tr igger Simulated VTC

2.5

VM2

VM1

Vin

(V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

Vout(

V)

2.5

k= 2k= 3

k= 4

k= 1

Vin

(V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

Vout(

V)

Effect of varying the ratio of the

PMOS device M4

Voltage Transfer Characteristics

with hysteresis

M1 = 1 m/0.25 m, M2 = 3 m/0.25 m, M3 = 0.5 m/0.25 m

M4 = 1.5 m/0.25 m M4 = kx 0.5 m/0.25 m

B.Supmonchai


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CMOS Schmitt Tr igger (2)

How does the gate operate?

M2

VIN VOUT

X

M1

M5

M6

M3

M4

Sketch VTC and find expression for VM-and VM+

B.Supmonchai

O


74/78


Review: Ring Oscil lator

0.0

0.0

0.5

1.0

1.5

2.0

2.5V1 V3 V5

3.0

20.50.5

time (ns)

1.0 1.5

Period: T= 2 x tpx N

tp

Different Clock Duty-Cyclesand ph ases can be der ived

using simp le logic operat ions

B.Supmonchai

V l C l l O il l (VCO)


75/78


In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr

Current starved inverter

Iref

Iref

Schmitt Trigger

restores signal slopes

Voltage Control ler Osci l lator (VCO)

Oscillation frequency of a VCO is a function (typicallynonlinear) of a control voltage

Delay of a current starved inverter depends on th e current

l imit avai lable to d ischarge the load c apacitance of th e gate

B.Supmonchai

C t St d I t Si l ti


76/78


Current-Starved I nverter Simulation

0.5 1.5 2.5Vcont r (V)

0.0

2

4

6

Vct r l(V)

tpHL

(nse

c)

The device is in the

subthreshold region

when Vctrlis smaller

than VT, resulting in

large variations of tp

as the drive current

is exponentially

dependent on the

drive voltage

Delay sensitive to

noise and variation

in Vctrl

B.Supmonchai

Diff ti l D l El t d VCO


77/78


Differential Delay Element and VCO

two stage VCO

v1

v2

v3

v4

- InvertingInputs/Outputs+ Non-InvertingInputs/Outputs

Oscillator with even numberof stages can be implemented

in2

Vctrl

Vo2 Vo1

in1

delay cell

+

+

-

-

Differential-type VCO has better immuni ty to common mode

noise (e.g., supply noise) but consume more power

B.Supmonchai

2 St VCO Si l ti


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2-Stage VCO Simulation

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2 0.5 1.5

V1

V2

V3

V4

time (ns)

2.5 3.5

The In-Phase and Quadrature Phase are prod uced simultaneously

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