CH8 DAC ADC Fundamrntal

DAC & ADC Testing Fundamental

2009/6/2MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin

2

Outline

Specifications of DACSpecifications of ADCTest methodology

Static specificationHistogram methodTransfer (and compare) method

Dynamic specificationFFTPolynomial Fitting


3

Resolution and Accuracy

Resolution is a design parameter rather than a performance specification. It only indicates what the theoretical accuracy can be, it does not imply accuracy to a given levelAccuracy is used to describe how close a converter comes to meeting its theoretical resolutionAccuracy in a converter is limited by

Theoretical quantization noiseNon-linearity in the transfer functionAdditional sources of noise in the converter circuitry

Digital codesinput

Analog signaloutput

D/AAnalog signalinput

Digital codesoutput

A/D


4

Introduction of DAC

Characteristic curve

7 Δ6 Δ5 Δ4 Δ3 Δ2 Δ1 Δ0

000 001 010 011 100 101 110 111

Analog Output

Digital Code

∑=

⎟⎠⎞

⎜⎝⎛×=

n

iii

SFoutDVA

1.. 2 , where Di is input code


5

FSR and LSB SizeFSR (Full Scale Range)

The maximum extremes of output signal for a DACCurrent or voltageDevices whose output does not cross through 0 are called unipolar, while those with “±” output polarities are bipolar

LSB (Least Significant Bit) sizeIdeal LSB is calculated from the specified FSRWhen testing, an LSB is an expected average value based on the actual length of the transfer curve

] [ ] [ .

ScaleZeroOutputMeasureScaleFullOutputMeasureFSRActualSpecsbySpecifiedFSRIdeal

−==


6

General Specifications of DACStatic specifications

Offset errorGain errorDifferential non-linearity (DNL)Integral non-linearity (INL)Monotonicity

Dynamic specificationsSettling timeMaximum conversion rateRising/Falling TimeClock FeedthroughPower Supply Rejection Ratio (PSRR)


7

Specifications of Special DAC

For current output DACCompliance test

For video DACGlitch Impulse test

For high resolution DACSNR/THD/SFDR test

For multi-DACsCrosstalk/Match test


8

Offset Error

Difference between the ideal and actual DAC output values when the zero or null level digital input code is presented to the device

Caused by comparator input offset voltage or currentExpressed in %FS or in fractional LSB

OutputScaleZeroIdealOutputScaleZeroMeasuredErrorOffset −=

7 Δ6 Δ5 Δ4 Δ3 Δ2 Δ1 Δ0

000 001 010 011 100 101 110 111

Analog Output

Digital Code

OffsetError


9

Gain Error

Difference between the measured output when full scale input code is presented and the ideal full scale output

Caused by errors in reference voltage, ladder resistor values, or amplifier gain, …

FSRIdealErrorOffsetOutputull Scale Measured FGain Error −−=

7 Δ6 Δ5 Δ4 Δ3 Δ2 Δ1 Δ0

000 001 010 011 100 101 110 111

Analog Output

Digital Code

Scale Factor Error


10

Differential Non-Linearity (DNL)

DNL is defined as the difference in the output voltage at a specific input as compared to the output at the previous input minus 1 device LSB

( ) ( )[ ] 12011−=−

−= nrealreal

i , iLSB

i - ViVDNL K

7 6543210

000 001 010 011 100 101 110 111

Analog Output (LSB)

Digital Code

DNL1 = 1LSB

DNL5 = -0.5LSB

( ) ( ) 120 −== nii , iDNLMaxDNLSignDNL K


11

Integral Non-Linearity (INL)

The deviation of the actual converter output from a straight line drawn between the end points of the converter’s input-output transfer function

7 6543210

000 001 010 011 100 101 110 111

Analog Output (LSB)

Digital Code

INL1 = 1LSB

INL6 = -1LSB

( ) ( )[ ] ( ) 120 −=−== nrealidealreali i, i

LSBiV

LSBi - ViVINL K

( ) ( ) 120 −== nii , iINLMaxINLSignINL K


12

Monotonic

A monotonic curve has no change in sign of the slope

LSBDNLmonotonicNonMonotonicLSBDNL

1 1

−<⇒−

⇒≤

7 6543210

000 001 010 011 100 101 110 111

Analog Output (LSB)

Digital Code

Non-monotonic


13

Settling Time (I)

Input code from 0 to full scale (dependent on devices)Output settles to within settling band, e.g. ± 0.5 LSBSettling time = T2 - T1DAC speed = (Settling time)-1

FullScale

50%

0

Analog Output

Time

Settling Band

Settling Time

T1 T2


14

Settling Time (II)

If slew rate not list in specificationSettling time = Delay time + Slew time + Ring time

Else Settling time = Ring time

[Alternative definition]


15

Maximum Conversion Rate

Ramp code (0 to 2n-1 to 0) test with maximun DAC operating frequency, e.g. 135MHz DACMost likely the inverse of time required to change from zero scale to full scale output

settletRateConversionMaximum 1 =

FullScale

0

0

Analog Output

Digital Code2n-1 0


16

Rise/Fall Time

Input code from 0 to full scale,Rising time = T2 - T1

Input code from full scale to 0,Falling time = T4 - T3

FullScale90%

10%0

Analog Output

Time

Settling Value

Rising Time

T1 T2

Falling Time

T3T4


17

Clock Feedthrough

A measurement of clock transition affects output valueInput code = Full ScaleClock feedthrough = peak-to-peak value of Vout, e.g., 2mVpp

or

FullScale

Analog Output

Time

Vpp_out

30dB- e.g. ,dBin log20_

_

outFS

outpp

VV


18

PSRR Test

A measurement of immunity of IC to power noise

VDD Vout: Full Scale1::1

Input code

ex. 100mVpp, 20KHz sine wave

ex. 5mVpp, like noise

DAC

DD

Vpp

outFS

outpp

VVVV

PSRRDD_

_

_

=


19

Compliance Voltage Test

Caused by the increasing of output voltage

Test setup

Load

Vout

DAC

Vout

IoutF.S.

Current0.5 LSB

Compliance Voltagex

VoltageSource,V

Vout

DAC

+-

CodeFull Scale

CurrentMeter, I


20

Glitch

Caused by asynchronous switching

I2I4I8I

Code 1000

Load

Vout

I2I4I8I

Code 0111

Load

Vout

-8 Δ

-7 Δ

Time

Vout


21

Glitch Test

Input code:

Glitch impulse =Summation is used in DSP-based ATE

0 100 1 110 KK ⇔

8 mv

4mv2mv

0

-5mvTime

Vout

Settling value

+ 1 LSB

- 1 LSB

2ns 2ns 1.5ns

Area1

Area2

Area3

( )( ) ( )( ) ( )( ) sec5.225.12132

2162

21

−=+− pVmVnsmVnsmVns


22

Frequency Domain Analysis

(a) SFDR (spurious-free dynamic rang)(b) SNR (Signal to noise ratio)(c) SNDR (signal to noise and distortion ratio)(d) Dynamic range(e) Average noise level

Digitizer

Vout: sine wave

digitized sine wave

FFT

Am

plitu

de(d

B)

Frequency

(a) (b) (c) (d) (e)

Fundamental

HarmonicNoise


23

THD and THD+NTHD (Total Harmonic Distortion)

A ratio of the sum of the amplitude at all harmonic frequencies to the one at the fundamental frequencyIn practice the sum is limited to seven or nine harmonic termsA negative quantity

THD+N (Total Harmonic Distortion plus Noise)Combine the power of noise and the harmonic frequencies


24

Dynamic Range

A measure of the capability of detecting small input signal

For an audio DAC, it indicates the ability to reproduce low level signalsIt is calculated by inverting the polarity of the THD+N (-60dB input) and adding 60dB

dB):(unit

⎟⎠⎞

⎜⎝⎛=

PowerDetectableMinimumPowerSignalMaximumgeDynamicRan


25

SNR and SNDR

SNDR (signal to noise and distortion ratio) A ratio of the amplitude at the fundamental frequency to the sum of the ones components at all other frequenciesInclude noise and distortion

SNR (Signal to noise ratio)A subset of SNDR, in which the components for harmonic distortion are not includedFor an audio DAC, it can be measured with all input data set to zero (no fundamental and harmonic frequencies) (ref: EIAJ CD-DA Std.)


26

SNR/THD/SFDR Test

Input code: digitized sine wave code

11…1

10…0

00…0

……

Vout: sine wave

Full Scale

DAC

Digitized and FFT


27

Inter Modulation Distortion (IMD)A test for non-harmonic product terms that appear in a device signal due to undesired modulation of two frequency components of a signalThe test is performed by putting a summed two sinusoid tone into a device and looking for frequency components in the sum and difference frequency

Second IMD product terms are found at (f1±f2)


28

Crosstalk

V1out: Full ScaleCrosstalk=

V1out

V2out

orDAC1

DAC2

dBin log20_

_

outFS

outpp

VV


29

Match

V1out = V2out = Full Scale

Match=

V1out

V2out

DAC1

DAC2

22121

__

__

outFSoutFS

outFSoutFS

VVVV

+−


30

Introduction of ADCCharacteristic curve

111110101100011010001000

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8

output code

input level(1lsb) (2lsb) (3lsb) (4lsb) (5lsb) (6lsb) (7lsb)

F.S.(full scale)

offset

n

iii

SFin VDVA +⎟⎠⎞

⎜⎝⎛×= ∑

=1.. 2 , where Di is output code


31

FSR and LSB Size

FSR (Full Scale Range)The maximum extremes of output signal for a ADCCurrent or voltageDevices whose output does not cross through 0 are called unipolar while those with ±output polarities are bipolar

LSB (Least Significant Bit) size( ) ( )

22 :1 Def.

−−

= Nin ZSTVFSTVinLSB

N

FSRLSB2

:2 Def. =

Vin(FST) is the full scale transition pointVin(ZST) is the zero scale transition point


32

Static Specifications of ADC

Offset errorGain errorDifferential non-linearity (DNL)Integral non-linearity (INL)Missing codesStatic noiseHystersis error


33

Offset Error

The difference between the ideal zero point value and the calculated zero point value

Usually expressed as LSBs, volts or percentage of full-scale range (%FSR)

( ) ( )( ) 0ntOffset Poi if Ideal LSBZSTVin

PointOffsetIdealVinScaleZeroVinErrorOffset

Device =×−=−=

5.0


34

Gain Error

It is dominated by errors in the converter’s reference voltage

idealDevice FSRFSRErrorGain −=

idealreal

111110101100011010001000

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8

output code

input level

F.S.(full scale)


35

Differential Non-Linearity (DNL)

DNL is the difference between adjacent transition points in an actual ADC and an ideal one

idealreal

111110101100011010001000

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8

output code

input level

F.S.(full scale)

real width

idealwidth

DNL i

( ) ( ) 120 −== nii , iDNLMaxDNLSignDNL K

120,1 −=−=−

= n

i

i

i

iii i

hideal widtreal width

hideal widt hideal widtreal widthDNL K


36

Integral Non-Linearity (INL)

A measure of maximum deviation of the actual transition points in an A/D’s transfer function from the ideal curve

111110101100011010001000

0 1/8 2/8 3/8 4/8 5/8 6/8 7/8

output code

input level

F.S.(full scale)align

INL 1

INL 2

INL 3

INL 4

INL 5

INL 6

( ) ( ) 120 −== nii , iINLMaxINLSignINL K

120,1

1 −==+= ∑=

−n

i

jiiii iDNLDNLINLINL K


37

Histogram test for DNL and INLUses a linearly increasing or decreasing signal as the input to the ADC under test

A 14 bit ADCramp histogram


38

Missing Code Test

Test Steps: 1. Count the number of each code: ni

2. Check ni > nth

111110101100011010001000

output code

Clock Timing

Input Signal: Ramp

Full Scale


39

Static Noise

Definition

Little concern in high-speed applications

Output

h ± ΔL

Input

k

Sampling

A/D


40

Hysteresis ErrorHysteresis Error in an ADC causes the voltage at which a code transition occurs to be dependent upon the direction from which the transition is approachedIt is usually caused by hysteresis in the comparator


41

Dynamic Specifications of ADC

SNR and SNDRTotal harmonic distortion (THD)Inter-modulation distortion (IMD) Spurious-free dynamic range (SFDR)Effective number of bits (ENOB)Dynamic Deviation


42

SNR and SINAD

SNR is a ratio of the signal amplitude to the noise levelWhen the harmonics are included, the S/N specification is referred to as the Signal-to-(Noise + Distortion) or SINADBoth signal-to-noise specifications exclude any DC offset from the noise component

resolutionofbitsofnumbernwheredBnSNR

,)( 76.102.6

=+=


43

Total Harmonic Distortion (THD)

THD relates the RMS sum of the amplitudes of the signal's harmonics to the amplitude of the signal

ADCs produce harmonics of an input signal because an ADC is an inherently nonlinear deviceThe THD will decrease if the transfer curve of the ADC more closely resembles a straight line

2/1

21

23

22

⎟⎟⎠

⎞⎜⎜⎝

⎛ ++=

f

ff

VVV

THDL where Vf1 is the amplitude of the fundamental

and Vfi is the amplitude of the i-th harmonic

( ) ( ) ( ) L++++= 33

2210 inininOUT VaVaVaaV ( )

22cos1cos 2 tt ωω +

=

If the output of an ADC is fed to a perfect DAC


44

Inter-Modulation Distortion (IMD)IMD results when two frequency components in a signal interact through the non-linearities in the ADC to produce signals at additional frequencies

An input signal with frequency components at 600Hz and 1kHz (left)suffers severe IMD after A/D conversion (right)


45

Dynamic Range and Spurious-Free Dynamic Range (SFDR)

Dynamic range is defined as the ratio (usually in dB) of the maximum signal size to the minimum signal size

For an ideal ADC, it is 20log(2bits-1)SFDR is the ratio of signal amplitude to amplitude of the highest harmonic or spurious noise component


46

Effective Number of Bits (ENOB)

ENOB is a specification that is closely related to the SNR

The ENOB specification combines the effects of many of the other dynamic specifications

Errors resulting from dynamic differential and integral non-linearitymissing codestotal harmonic distortionaperture jitter

02.676.1−

=SNRENOB

•Some manufacturers define the ENOBusing the SINAD instead of the SNR•ENOB generally decreases at high frequencies


47

Dynamic Deviation

Definition

Be used to evaluate dynamic performance of ADC

Output

h ± ΔL

Input

k

Sampling

A/D


48

Histogram TestA statistical number of samples of the input sinusoid are taken and stored as a record

The frequency of code occurrence in the record is plotted as a function of code

For an ideal ADC, the shape of the plot would be the PDF of a sine wave

22

1)(VA

VP−

=π

The PDF of a sine wave is given by

A is the sine wave amplitudeV is the input voltage


49

Histogram Test -- DNLDifferential non-linearity

The ideal probability of occurrence

1) (

( −=−codenthPideal

nth code)PactualLinearityNonalDifferenti

actual P(nth code) is the measured probability of occurrence andideal P(nth code) is the ideal probability of occurrence for code bin n

( ) ( )⎥⎦

⎤⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛×−−

−⎟⎟⎠

⎞⎜⎜⎝

⎛×−

=−

−−

−N

N

N

N

AnB

AnBnP

221sin

22sin1)(

11

11

π

n is the code bin numberB is the full-scale range of the ADCA is sine wave amplitudeN is the number of ADC bits


50

Histogram Test -- Input Frequency and Example

The input and sample frequencies must be relatively independentIn realistic, using an input frequency that has a large common divisor with the sample frequency, Ideally, the period of the greatest common divisor should be as long as the record lengthExample

A 100,000-sample histogramfor a 9.85MHz sine wave inputAll discontinuities are less than1LSB


51

Histogram Test -- Examples

Large differential non-linearities and numerous missed codes are apparent


52

Histogram Test -- Input Waveform

Sinusoidal waveform is easier to generate accurately and stably with most signal generator

t

CodeBin

255

01

CodeBin

255

01 t

t

CodeBin

255

127

CodeBin

255

t127

Code

Number ofOccurence

Number ofOccurence

Code0 255

0 255


53

FFT Test -- SetupBasic principle

Evaluation system


54

FFT Test -- Spectrum Interpretation

Fundamental

Non-linear Distortionfrom A/D C

Quantization Errorform A/D C or digitizer

Random Noise

Uncertainty:Timing JitterPhase NoiseAperature Error

FFT Spectrum obtainedfrom A/D C output


55

FFT Test -- ExampleFFT plots for 0.85MHz data quantized by perfect (a) 10-bit and (b) 6-bit ADCsSNR = 6.02n + 1.76

(a) (b)


56

FFT Test -- Example (cont.)

Distortion increases with increasing frequencyFFT plots for the input frequencies of (a) 9.85MHz and (b) 0.95MHz

(a) (b)


57

Case Study

3.3V 8bit 135MHz Video D/A C

HI5741-14bit DAC


58

Test Circuit

Vcca

Gnda

Out

Out

D 7...D 0

Vddd

Gndd

Clk

Vref

Vcomp

DPS2_GNDDPS1_GND

10 μ

PMU2

0.1μ

DPS1_P(3.3V)

0.1μ 10μ

DPS1_GND(0V)

MEASURE1_1

VHFMEAS1_1 DigitalPin

DPS2_GND(0V)

DPS2_P(3.3V)

3.3V 135MHz 8bit D/A C

?Ω ?Ω

?Ω

1

2

3

DigitalPins


59

Linearity TestD/A C output for digital ramp code input

DNL = -0.172 lsb INL = -1.228 lsb


60

Timing Test

Settling, Rising, Falling time

Rising time = 2.5nsFalling time = 3 ns

Settling time = 20 nswith ±1lsb settling band


61

Clock Feed Through Test

Impedance unmatching

Clock feed through Vp-p = 25mVClock feed through = -31.66 dB


62

Glitch Impulse Test

Glitch impulse= 0.51 pVsec.

Since this is aSegment D/A C

± 0.25 lsb


63

PSRR Test

Vp-p = 7.33 mVVout = 718mV

PSRR = 0.337 %/%ΔVddPower supply modulated by20KHz, 100mVp-p sine wave


64

SNR/THD/SFDR Test

Input code: digitized sine wave code

FFT

SFDR: 62.11dBSNR: 49.45 dBTHD: -58.38 dB

Fin = Data rate x cycles / #pointsFin/Fs = M cycles / 2n


65



18.43

18.44

18.45

18.46

18.47

18.48

18.49

18.50

18.51

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60

Output Voltage

Out

put

Cur

rent

(m

A) Full_I = 18.5 mA

Compliance Voltage=1.7 V


66

Case Study

3.3V 10bit 30MHz A/D C

AD9240-14bit ADC


67

Test Circuit

AGND

DRVDD

D0

::

D9 (MSB)

DRGND

DGND

CLK

AVDD

VIN

VRLS

VRLF

VRHF

VRHS

DVDD

10 μ

DPS1_GND

DigitalPins

0.1μ

DPS1(3V)DPS2(3V)

Source 1-1

DPS1(3V)Digital Pin

PMU2(2V)

PMU1(0V)

10 μ0.1μ

Source 3-1

DPS2_GNDDPS1_GND

10 μ0.1μ

3.3V 10bit 30MHz A/D C


68

Linearity Test

A/D C output for Triangle wave inputOverflow

Underflow


69

DNL Test

Statistic Analysis

#148

DNL


70

INL Test

INL


71

SNR/THD/ENOB Test

1MHz sine wave (with socket)

FFT

SNR :57.98583THD :65.46822SINAD :54.92447ENOB :8.831307

#cycle = 69, #point = 2048


72

SNR/THD/ENOB Test (cont’d)

4.43MHz sine wave (with socket)

FFT


#cycle = 303, #point = 2048

….


73

SNR/THD/ENOB Test(cont’d)

10MHz sine wave (with socket)

FFT


#cycle = 683, #point = 2048

….


74

Reference (1/2)

“Specifying A/D and D/A Converters,” National Semiconductor Corp. Application Note (AN-156), February 1976Scott Wayne, “Getting the Most from High Resolution D/A Converter,” Analog Devices Inc. Appliction Note (AN-313), 1983“The Fundamentals of Mixed Signal Testing,” Soft Test Inc.Larry Gaddy and Hajima Kawai, “Dynamic Performance Testing of Digital Audio D/A Converters,” Burr-Brown Corp. Application Bulletin (AB-104), May 1997Jim Williams, “Component and Measurement Advances Ensure 16-Bit DAC Settling Time,” Linear Technology Corp. Application Note 74, July 1998“Using the Analog to Digital Converter,” Microchip Technology Inc. Application Note (AN-546), 1994Larry Gaddy, “Selecting an A/D Converter,” Burr-Brown Corp. Application Bulletin (AB-098), April 1995Mark Sauerwald, “Designing with High-Speed Analog-to-Digital Converter,” National Semiconductor Corp. Application Note (AD-01), May 1988Leon G. Melkonian, “Dynamic Specifications for Sampling A/D Converters,” National Semiconductor Corp. Application Note (AN-769), May 1991“IEEE Standard for Performance Measurements of A/D and D/A Converters for PCM Television Video Circuits,” ANSI/IEEE Standard 746-1984


75

Reference (2/2)

“Dynamic Tests for A/D Converter Performance,” Burr-Brown Corp. Application Bulletin (AB-072)Walt Kester, James Bryant, “Grounding in High Speed Systems,” Analog Devices Inc.William C. Rempfer, “The Care and Feeding of High Performance ADCs: Get All the Bits You Paid For,” Linear Technology Corp. Application Note (AN-71), July 1997Bill Travis, “EDN Hands-On Project: Demystifying ADCs,” EDN, pp.26, March 27, 1997Bill Travis, “Remystifying ADCs” EDN, October 9, 1997David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” John Wiely & Sons, Inc. 1997R. W. Stewart and E. Pfann, “Oversampling and Sigma-Delta Strategies for Data Conversion,” Electronics & Communication Engineering Journal, February 1998Brian Black, “Analog-to-Digital Converter Architectures and Choices for System Design,”Analog Devices Inc. Analog Dialogue 33-8, 1999

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CH8 DAC ADC Fundamrntal

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