Challenges and Solutions for 32nm Node Ultra-Shallow Junctions
S.B. Felch*1, T. Hoffmann, T. Noda#, C. Ortolland, E. Rosseel, R. Schreutelkamp*, P. Absil and W. Vandervorst
IMEC, * Applied Materials, 1 Now at Spansion, # Matsushita
West Coast Junction Technology Group, San Francisco, CAJuly 17, 2008
T. Hoffmann imec 2008 2
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealingsecond annealing
• Summary
T. Hoffmann imec 2008 3
IIT’08 – Monterey, CA
time
L=35nm
SiGe
L=35nmL=35nm
SiGe
NiSi
25 nm
NiSi
25 nm
FUSIFUSI
strainstrain
metal gatemetal gate
USJUSJ
silicidesilicide
>=13090-65-45
45-32
32-22-16
Strain,
F,C,… co-implant
High-k, Metal Gate
(lower Dt process ?)
Performance
Device level : Scaling ���� SCE control !!!
?
Si planar (
bulk) CMOS
FinFETFinFET
Active Area
Gate FieldSpacers
Active Area
Gate FieldSpacers
Active Area
Gate FieldSpacers
GeGe/IIIV/IIIV
Multi-gate, III-V, CNT
T. Hoffmann imec 2008 4
IIT’08 – Monterey, CA
Why Multi-gate for 22nm & beyond ?
Ioff
Ion
Gate
S D
Gate
S D
Ioff
Ion
• Double gate structure much better gate-to-channel control
• � better short channel effect immunity
• � Lower leakageand higher mobility(no channel doping)
• In all looks nice & simple, BUT …
T. Hoffmann imec 2008 5
IIT’08 – Monterey, CA
USJ challenges for FinFETFIN amorphization /recristalization
• FinFET has new set of challenges for junction formation (conformality, defectivity, etc …) !!
FIN implanted with As + annealed� Poor re-crystallization
Duffy, APL, 90, 2007Van Dal, VLSI 2007
T. Hoffmann imec 2008 6
IIT’08 – Monterey, CA
ITRS Scaling of Lg and Xj
Junctions are becoming extremely shallow and difficult to form
T. Hoffmann imec 2008 7
IIT’08 – Monterey, CA
HKMG
USJ roadmap (IMEC view)
… assuming Planar architecture
22nm32nm45nm
40nm55nm70nm
LogicLogic
DRAMDRAM
65nm
85nm
Spike-RTA
Flash orLaser
Spike-RTA
Flash orLaser
C,F co-implant
C,F co-implant
Logic HP
DRAM/Logic LP
T. Hoffmann imec 2008 8
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealingsecond annealing
• Summary
T. Hoffmann imec 2008 9
IIT’08 – Monterey, CA
{113}s
5 nm
a
b
( )
( )
Si interstitialflux from EORto the surface
Boronprofile
Ato
m c
on
cen
trat
ion
Depth
End-Of-RangeDefects
Si interstitialflux from EORto the surface
End-Of-RangeDefects
Non-dopantimpurity
to suppress [Si ]i
Boronprofile
Ato
m c
on
cen
trat
ion
Depth
Concept of coConcept of co--implantsimplants
Co-implantation suppresses diffusionof Si interstitials from End-Of-Range
T. Hoffmann imec 2008 10
IIT’08 – Monterey, CA
0 10 20 30 40 5010
18
1019
1020
1021
B implanted
B
oro
n c
on
cen
trati
on
(at.
/cm
3)
Depth (nm)
1D : Carbon co1D : Carbon co--implanted pimplanted p--type junctiontype junction
0 10 20 30 40 5010
18
1019
1020
1021
B+RTAB implanted
B
oro
n c
on
cen
trati
on
(at.
/cm
3)
Depth (nm)0 10 20 30 40 50
1018
1019
1020
1021
B+RTA
Si+B+RTA
B implanted
B
oro
n c
on
cen
trati
on
(at.
/cm
3)
Depth (nm)0 10 20 30 40 50
1018
1019
1020
1021
B+RTA
Si+B+RTA
Si+C+B+RTA
B implanted
B
oro
n c
on
cen
trati
on
(at.
/cm
3)
Depth (nm)
The most shallow and abruptjunction is with amorphization and C
T. Hoffmann imec 2008 11
IIT’08 – Monterey, CA
2D electrical profiling of 2D electrical profiling of pMOSFETpMOSFETSSRM (Scanning Spreading Resistance Microscopy)SSRM (Scanning Spreading Resistance Microscopy)
F co-implant
Co-implantationwith Carbon:
• Reduces extensionoverlap
• Suppresses HDDdiffusion towardsgate edge
Courtesy: P. Eyben [IMEC]
T. Hoffmann imec 2008 12
IIT’08 – Monterey, CA
2008 VLSI-TSA Symposium
2D electrical profiling of 2D electrical profiling of pMOSFETpMOSFETSSRM (Scanning Spreading Resistance Microscopy)SSRM (Scanning Spreading Resistance Microscopy)
C without pre-amorphization does not reduce junction overlap
T. Hoffmann imec 2008 13
IIT’08 – Monterey, CA
Carbon coCarbon co--implantimplantTransistor performanceTransistor performance
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
10 100 1000
Lg [nm]
VT
lin [
V]
F+B ext
BF2 ext
Ge+C+B ext
-50mV
F co-implantC co-implant (w/ PAI)
pMOS
• Improved SCE with no performance loss demonstrated with PAI+C (specially for pMOS)
T. Hoffmann imec 2008 14
IIT’08 – Monterey, CA
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
10 100 1000Lg [nm]
VT
sat
[V]
Carbon for junction thermal stability
• Junction thermal stability is critical for some application (e.g., DRAM periphery)
• Carbon can improve significantly the junction thermal stability
0 10 20 30 40 50
1018
1019
1020
1021
1022
No C co-implant
Without DRAM anneal
With DRAM anneal
B c
on
ce
ntr
atio
n (
ato
ms/c
m3)
Si Depth (nm)
With C co-implant
After spike annealing at 1030oC
DRAM anneal (DA) = 750C-30min
+DA
+DA
With C co-implant
no C co-implant
T. Hoffmann imec 2008 15
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Impact on junction leakage (residual defects)
– Compatibility with HKMG stacks
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
T. Hoffmann imec 2008 16
IIT’08 – Monterey, CA
Thermal Budget
Rapid ThermalAnnealing
(Spike RTA)
Rapid ThermalAnnealing
(Spike RTA)
~1s
T= 1000-1100C
Solid PhaseEpitaxial Regrowth
(SPER)
Solid PhaseEpitaxial Regrowth
(SPER)
~1min
T= 550-700C
FlashAnnealing
FlashAnnealing
~1ms
T= 1100-1300C
LaserThermal
Annealing
LaserThermal
Annealing
~0.2ms
T= 1100-1300C
time
Temperature
MSA
17
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
32nm specifications32nm specificationsN-Type P-Type
0
200
400
600
800
1000
1200
1400
0 10 20 30 40Xj @5e18cm-3 [nm]
Sh
eet
resi
stan
ce [
Oh
m/s
q.]
5e19 (n)
1e20 (n)
As w/ spike only
As w/ spike + laser
Ph w/ laser only
As w/ laser only
0
200
400
600
800
1000
1200
1400
0 10 20 30 40Xj @5e18cm-3 [nm]
Sh
eet
resi
stan
ce [
Oh
m/s
q.]
1e20 (p)
5e19 (p)
B+F w/ spike + laser
B+F w/ spike only
B+F+Ge
w/ LA only
B+F
+Ge
w/ LA only
Laser anneal only enables to meet 32nm specs.
32nm
T. Hoffmann imec 2008 18
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Compatibility with HKMG stacks
– Impact on junction leakage (residual defects)
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
T. Hoffmann imec 2008 19
IIT’08 – Monterey, CA
MSA in addition to SpikePerformance ‘booster’
• Laser anneals improves:– Poly-gate doping
– Junctions activation
Xj@5E18 (nm)
Shee
t re
sist
ance
(O
hm
/sq.)
0 10 20 30 400
400
800
1000
1200
1600
1400
600
200
Xj@5E18 (nm)
Shee
t re
sist
ance
(O
hm
/sq.)
0 10 20 30 400 10 20 30 400
400
800
1000
1200
1600
1400
600
200
0
400
800
1000
1200
1600
1400
600
200
5E20 1E20 5E19
As (no Laser)
As (+Laser 1300 ºC)
B (no Laser)
B (+Laser 1300 ºC)
Reduced
Poly-depletion
Reduced
Serie resistance
Bidau [ST], RTP’07
T. Hoffmann imec 2008 20
IIT’08 – Monterey, CA
Spike-Laser sequence impactpMOS
AL
LaserLaser
Spike RTA
ALSpike RTA
AL
Laser
Spike RTA
A B C
• Up to 9% performance improvement demonstrated with additional Laser anneal with “Spike-last” sequence.
• KMC simulation confirmed it is due to less B-I clusters formed during Spike with a pre-Laser anneal
280
290
300
310
320
330
340
350
360
Spike Spike +Laser-1200C
Spike +Laser-1350C
Idsa
t @ io
ff=6
0nA
/um
[uA
/um
]
Flow A
Flow B
Flow C
-10%
+9%
Ref.
- improved Bo activation- reduced dose loss- reduced mobility loss
22
Bo dose loss (extension & poly-gate)
1
1
Hoffmann [IMEC], IWJT’07
T. Hoffmann imec 2008 21
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Compatibility with HKMG stacks
– Impact on junction leakage (residual defects)
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
T. Hoffmann imec 2008 22
IIT’08 – Monterey, CA
USJ opportunities with advanced gate stacks
• Aggressive USJ requires low Thermal budget, BUT :
1. Leakage from remaining EOR
2. Poly gate doping/activation
as-implantedExtension + HDD
Spike-RTA
diffusedprofiles
COMPATIBLE with MSA
� SOLUTION : remove PAI (eg, Cluster I/I)
� SOLUTION : Metal Gate
T. Hoffmann imec 2008 23
IIT’08 – Monterey, CA
Laser-only junctions designMethodology
• Use of SSRM and TCAD for successful device targeting:– nMOS � As (3keV) need to be tilted (> 7D)
– pMOS � B (0.5keV) : OK with tilt = 0o
14-16
16-18
33-37 20-25
39-4140-42
27-29
8-11
Laser - 0.5keV Laser - 1keV
14-16
16-18
33-37 20-25
39-4140-42
27-29
8-11
Laser - 0.5keV Laser - 1keV
pMOS(implant tilt = 0D)
nMOSAs 3keV
UNDERLAP
MARGINAL
UNDERLAP
OVERLAP
24
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
0
100
200
300
400
500
0 0.05 0.1Physical Lg [µm]
DIB
L [
mV
/V]
0
100
200
300
400
500
0 0.05 0.1Physical Lg [µm]
DIB
L [
mV
/V]
Extensions redesign with MSAExtensions redesign with MSA
NMOS (As) PMOS (B)1KeV T0 0.5KeV T0
3KeV T15 1KeV T0
5KeV T15 1.5KeV T05KeV T30 1KeV T15
Spike reference
nMOS pMOS
Proper placement of dopants (Tilt, energy) is even more critical with diffusion less approach
25
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Device scaling with LaserDevice scaling with Laser
0
150
300
450
600
750
900
0 10 20 30 40 50 60 70 80Lg min [nm]
Ion
[µA
/µm
]
Spike only
Laser only
nMOS
pMOS
32n
m s
pec
.B 0.5KeV T0
As 3KeV T15
32nm requirement has been achieved
@Ioff=100nA/µm
26
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
0 200 400 600Ion [µA/µm]
Ioff
[A
/µm
]
pMOS
FUSI
Laser Power Increase
Laser PowerLaser Power
Laser 1100°C Laser 1200°C
Laser 1350°C
Laser power optimization is
very important to achieve high performance
Spike
27
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
CoCo--implantation with MSAimplantation with MSA
30
35
40
45
50
55
60
Ph
ysic
al L
g m
in @
Ioff
fix
ed
Ge F Ge/F
Increase F dose
Increase Ge energy
Co-implantation still mandatory to avoid channeling and Boron TED
T. Hoffmann imec 2008 28
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Compatibility with HKMG stacks
– Impact on junction leakage (residual defects)
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
29
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Advanced gate stack optionAdvanced gate stack option
FUSI RPG MIPSGate last Gate last Gate first
@ L
DD
& H
alo
imp
lan
t ste
p
@ e
nd
of
pro
ce
ss
poly
ALD - Metal
Metal footing
30
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
FUSI caseFUSI case
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0.01 0.1 1Physical gate length [µm]
Vth
sat
[V
] Spike only
Laser only
nMOS
pMOS
FUSI
As 3KeV T15
B 0.5KeV T0
Excellent scaling has been
observed on FUSI
(Gate last process)
31
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
-0.4-0.3-0.2-0.1
00.1
0.20.30.40.50.6
0.01 0.1 1
Physical gate length [µm]
VT
sat
[V]
Spike only
Laser only
nMOS
pMOS
As 3KeV T15
B 1KeV T0
Metal Insert PolyMetal Insert Poly--Silicon caseSilicon case
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
0 500 1000Ion [µA/µm]
Ioff
[A
/µm
]
Spike only
Laser only w/o opt.
Laser only w/ opt.
As 3KeV T15
Laser onlyafter optimization
Junctionre-optimization
Junction design can be highly sensitive to the gate stack chosen
32
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Typical gate profileTypical gate profileStraightFootingUndercut
• Poor overlap between gate and junction
• USJ re-targetting would allow good overlap
• Overlaps depends if the taper is electrically part of the electrode
• USJ re-targetting would allow good overlap
• Good USJ alignment with gate edge
?
Dopant implantation and placement are very sensitive to gate profile with diffusion less anneal
33
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0.01 0.1 1Physical Gate Length [µm]
Vth
Sat
[V
]
Laser
Spike
nMOS
pMOS
MIPS with straight gate profileMIPS with straight gate profile
B 0.5KeV T0
As 3KeV T15
Scalability with Laser anneal on MIPS
required straight gate profile
T. Hoffmann imec 2008 34
IIT’08 – Monterey, CA
Use of capping for low-VT MIPSHigh-K doping
• High-K ‘doping’ with capping (eg, LaO, AlO) shifts eWF to band-edge � low nMOS & pMOS Vt’s
• Thermal budget impacts capping “efficiency”
Mixed Layer of HfSiON & AlO
S. Kubicek et al., IEDM 2007
T. Hoffmann imec 2008 35
IIT’08 – Monterey, CA
Controlled capping mixing with Laser
-0.6-0.5-0.4-0.3-0.2-0.1
00.10.20.30.40.50.60.7
VT
lin [V
]
LLP MLP HLP
no cap with cap
Spike Spike
with cap
nMOS
pMOS -0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
13 14 15 16 17 18 19
EOT (Å)
VT
lin (
V)
capped, Laser-anneal
uncapped (Spike-RTA)
capped (Spike-RTA)
+ AlO cap
Spike ���� Laser
LLP
MLP
HLP
LaO
AlO
• Beside known potential for Lg scaling, Laser anneal has :– Benefit in EOT regrowth containment
– Controlled capping mixing with High-K and/or IL
Intermixing ����with higher
Thermal budget
S. Kubicek et al., IEDM 2007
T. Hoffmann imec 2008 36
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Compatibility with HKMG stacks
– Impact on junction leakage (residual defects)
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
37
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Diode leakageDiode leakage
• High Ge energy increase dramatically the diode leakage
• Large leakage reduction for high power laser
• Similar leakage as spike could easily be achieved
1.E-13
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
P+/
Nw
ell d
iod
e le
akag
e [A
/µm
2 ]
Median
12KeV
20KeV
30KeV
Ge
20
Ke
V
Increase laser power
Spike Laser only
38
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Defects positionDefects position
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
-40 -20 0 20 40Defects position: Xj - EOR [nm]
Lea
kag
e cu
rren
t d
ensi
ty [
A/c
m2]
SPE data byBorland, MRS'02
X X X X X X X X X
Ge
12KeV
Defects
X X X X X X X X X
Ge
20KeV
Defects
X X X X X X X X X
Ge
30KeV
Defects
X X X X X X X X X
Defects
Defect position as function of junction depth is very important to contain the leakage
T. Hoffmann imec 2008 39
IIT’08 – Monterey, CA
Junction leakage ‘pragmatic’ containmentHalo dose reduction
• Spike � Laser : 10x penalty in junction leakage
• Diffusion-less � halo strength can be dramatically reducedwithout SCE control loss
• Huge reduction in Band-To-Band tunneling leakage
pMOS
Halo dose: 0% ���� As 3.5e13 cm-2
1.E-14
1.E-13
1.E-12
1.E-11
1.E-10
10 20 30 40 50 60
Physical Lg min @Ioff=100nA/µm [nm]
Gat
e E
dg
e Ju
nct
ion
Lea
kag
e [A
/µm
]
LaserSpike
@ same halodose
Halo-15%
Halo-30%
Halo0%
T. Hoffmann imec 2008 40
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Compatibility with HKMG stacks
– Impact on junction leakage (residual defects)
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
T. Hoffmann imec 2008 41
IIT’08 – Monterey, CA
Impact of MSA peak Temperature on SiGe
1191C
1217C
1269C
1243C
800
900
1000
1100
1200
1300
1400
1500
0 0.2 0.4 0.6 0.8 1
Tem
per
ature
[oC
]
Ge content
Liquidus
SolidusS
S+L
L
1412 oC
937 oC
Stohr, H., W. Klemm, Z. Anorg. Allgem. Chem. 241 , 1954, 305.
Nom
ars
ky
images
(SiG
e~25%
Ge)
Window of application
E. Rosseel [IMEC], RTP’07
T. Hoffmann imec 2008 42
IIT’08 – Monterey, CA
Effect of Dwell Time and Ge % on Temperature Onset of Line Defects
E. Rosseel et al., IMEC/AMAT: IEEE RTP2007 Conference.
T. Hoffmann imec 2008 43
IIT’08 – Monterey, CA
Impact of MSA peak Temperature on SiGe
• Large junction leakage increase after Laser-anneal �alternative integration flow required to alleviate the problem
-9
-8
-7
-6
-5
-4
No LA 1100 LA1200 LA1300 LA
Log
(IB
OF
F)
[A/u
m]
Junction leakage
C. Cheirigh et al., MIT, ECS Trans.,3(2), 2006
E. Rosseel [IMEC], RTP’07
SiGe (25%)
T. Hoffmann imec 2008 44
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealing (MSA)second annealing (MSA)– Fundamental advantage of milli-second anneal
– Milli-second annealing entry point : combination with Spike
– Aggressive junctions design with MSA-only
– Compatibility with HKMG stacks
– Impact on junction leakage (residual defects)
– Compatibility with strain boosters
– Process control & manufacturability
• Summary
45
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Stitching on devices?Stitching on devices?
Sca
n d
irection
Scan step
~3.65mm
0 4 8 12 Stitching
X position [mm]
1st scan
Laser width
~11mm
3rd scan
2nd scan
4th scan…
X position
43 identical modules / die
1 die
With the help of the Through Field module we have developed a
methodology to quantify the electrical impact of the stitching
46
Honolulu VLSI Technology June 19th 2008 : 19-1 C. Ortolland
Impact on devicesImpact on devices
-290
-285
-280
-275
-270
-265
-260
-255
0 10 20 30 40 50X position [mm]
Vth
lin
[m
V]
Spike only
Laser onlyStitching
0
5
10
15
20
long channeldevice
short channeldevice
Vth
lin
var
iati
on
[m
V]
Spike only
Laser only
1 2
Source of spread:1) Other process steps2) Laser w/o absorbing layer
• Laser signature is clearly visible in long channel• Impact is negligible in short channel compared to other
sources of spread
10x10µm2
T. Hoffmann imec 2008 47
IIT’08 – Monterey, CA
Outline
• Different paths for scaling & implications for USJ
• From low dopant diffusion with coco--implantationimplantation …
• … to diffusion-less with millimilli--second annealingsecond annealing– Fundamental advantage of milli-second anneal
– Aggressive junctions design (with or without additional Spike-RTA)
– Impact on junction leakage (residual defects)
– Compatibility with HKMG stacks
– Compatibility with strain boosters
– Compatibility with alternative doping techniques
– Process control & manufacturability
• Summary
T. Hoffmann imec 2008 48
IIT’08 – Monterey, CA
Non-melt MSA : Process window is function of device architecture !
• MSA has many challenges/opportunities in advanced devices• Overall Process Window is not unique = f(application, perf. boosters)
Poly-depletion PW c-SiMelt
High-K cap Mixing PW
eSiGerelaxation PW
Dit PW(reliability, mobility)
Dopant activation PW
PeakT1000C 1100C 1200C 1300C 1400C
EOR dissolutionPW