Changes in input values are reflected immediately (subject to the speed of light and electrical delays) on the outputs

Each gate has an associated “electrical delay”

Delays are often ignored for the purpose of the logic design (but not for the real implementation!)

As soon as inputs change, the outputs change – no memory of what happened before (at least conceptually)

Combinational Logic

Latches & Flip-Flops

Example Needing Bit Storage

Flight attendant call button Press call: light turns on

Stays on after button released

Press cancel: light turns off Logic gate circuit to

implement this?

QCall

Cancel

Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0Need some form of “feedback” in the

circuit

a

a

Bit

Storage

Blue lightCall

buttonCancel

button

1. Call button pressed – light turns on

Bit

Storage

Blue lightCall

buttonCancel

button

2. Call button released – light stays on

Bit

Storage

Blue lightCall

buttonCancel

button

3. Cancel button pressed – light turns off

First attempt at Bit Storage

We need some sort of feedback Does circuit on the right do what we want?

No: Once Q becomes 1 (when S=1), Q stays 1 forever – no value of S can bring Q back to 0

QS

t

0t

0 QS0

10

10

10

Q

t

S

0t

1 QS0

0t

1 QS1

1t

1 QS1

1t

0 QS1

Basic NOR (SR) Latch

When Set = 0, Reset = 1 Q = 0 When Set = 1, Reset = 0 Q = 1 When Set = Reset = 0 Q = memory When Set = Reset = 1 Q = 0

Reset

Set Q

Basic NOR Latch Redrawn

Q

Q

R

S

S R Q Q

0 0 0/1 1/0

0 1 0 1

1 0 1 0

1 1 0 0

memory state

Timing Analysis of Basic Latch

What happens at t10?? S and R both go from 1 to 0 simultaneously If gate delays are exactly the same oscillation!!!

1

0

1

0

1

0

1

0

R

S

Q

Q

?

?

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

Q

Q

R

S

Gated SR Latch

To get better control of the state changes, we must limit when the input signals affect the outputs

Outputs change only when Clk = 1 Clk acts as an Enable signal

Q

Q

R

S

Clk

Clk S R Q(t+1)

0 x x Q(t)

1 0 0 Q(t)

1 0 1 0

1 1 0 1

1 1 1 x

undefined since we don't know which stable state will result

Comments on Latches

Need to avoid the unstable state Note that all other states have “correct” Q and Q

Can use the cross-coupled NOR approach, or can use the cross-coupled NAND approach All gates are the same type

S

R

Clk

Q

Q S Q

Q

Clk

R

Gated D Latch

Provide only a single control signal D (for Data) More common than SR latch, and simpler

Q

S

R

Clk

D (Data)

Q

Clk D Q(t+1)

0 x Q(t)

1 0 0

1 1 1

D Q

Q Clk

D Latch Timing Diagram

Output Q changes only when Clk = 1 Q tracks D when Clk = 1

This latch is level-sensitive since the output is sensitive to the level of the clock

t 1 t 2 t 3 t 4

Time

Clk

D

Q

Master-Slave D Flip-Flop Desire to remove the level-sensitive nature

Want changes in Q only on the transition of the Clk signal from 1 0 (or from 0 1)

When Clock = 1, master D latch tracks D; slave D latch remains unchanged (Q remains fixed)

When Clock = 0, master D latch is unchanged; slave D latch tracks Qm

D Q

Q

Master Slave

D

Clock

Q

Q

D Q

Q

Q

Clk Clk

D Q

Q

negative edge-triggered flip-flop

Timing of Master-Slave D Flip-Flop Changes to Q occur only on the negative edge of the Clock

D Q

Q

Master Slave

D

Clock

Q

Q

D Q

Q

Q m Q s

Clk Clk

D

Clock

Q m

Q Q s =

Terms, Reviewed

Latch Two NANDs (or NORs) used to store one bit

Gated latch Latch with an control enable, called Clk Two basic types: SR and D, both level sensitive

Master-slave flip-flop State changes only on clock edge; made from two gated D

latches

Registers

A flip-flop stores one bit of information

When you want to store n bits register n flip-flops used Clock is shared by all so action is synchronous with clock edge

Some common register types Simple register Shift register Parallel access shift register Lots of counters: up counter, down counter, BCD counter, ring

counter, Johnson counter

Simple 4-bit Register A standard 4 bit register using D flip flops

Q 3 Q 2 Q 1 Q 0

Clock

Parallel input

Parallel output

D Q

Q

D Q

Q

D Q

Q

D Q

Q

4-bit Register with Load Control Controlling the load capability

Q 3 Q 2 Q 1 Q 0

Clock

Parallel input

Parallel output

D Q

Q

D Q

Q

D Q

Q

D Q

Q

Load