Arbitrary Bit Generation and CorrectionTechnique for Encoding QC-LDPC Codes with Dual-Diagonal Parity Structure

Chanho Yoon, Eunyoung Choi, Minho Cheong and Sok-kyu Lee

IEEE Communications Society subject matter experts for publication in the WCNC 2007 proceedings.

Outline

Introduction Encoding Procedures for QC-LDPC Code Proposed Arbitrary Bit Generation and

Correction Encoding Complexity Comparison Simulation Results Conclusion Comment

Introduction

weak points in LDPC codes are encoding complexity is generally higher

QC-LDPC were employed to resolve complexity issues while performance is almost the same as general LDPC codes.

The proposed encoding method is directly applicable to usual dual-diagonal based QC LDPC codes if little modification is allowed in parity part of the mother matrix H.

Dual-Diagonal Parity Structure

LDPC codes whose parity-check matrices have dual diagonal structure with a single weight-3 column, also presented in standards such as IEEE 802.11n and IEEE 802.16e.

In IEEE 802.16e, three sub-block sizes are suggested, as Z=27, Z=54, Z=81.

matrix Hp can be further decomposed into two sub matrices as

Vector-like sub-matrix hp is composed of weight-3 columns(e.g. hp = [1,−, ..., 0,−, ..., 1]T ), while h0 denotes thecyclic shift at 1st row. Consequently, matrix Hp becomes adual-diagonal structure.

Encoding Procedures for QC-LDPC Code

Conventional Efficient Encoding Scheme by Richardson

Note that −ET−1B+D = I since addition of all sub-block matrices at weight-3 part of matrix Hp suggested in standards such as [1] results simply Z×Z identity matrix I.

1st parity vector p0 is obtained through accumulation of input bits. 2nd parity vector p1 is obtained through block accumulation operation plugging p0 to Eq.(8), exploiting dual-diagonal lower triangular matrix T.

Proposed scheme In order to describe the encoding process with standard H

matrices, modification of parity-check matrix is required. parity portion of weight-3 column is set to all zero cyclic shift.

Main phases to our approach of encoding: (1) the arbitrary parity-bit generation (p0)

(2) sequential process to find remaining parity-bits

exploiting dual-diagonal structure

(3) correction process for parity-bits.

Parity part of matrix H is partitioned into two parts as Q and U. The boundary line is placed between second and third sub-block where three identity matrices are placed in a row.

Why do we have to modify the matrix?

first and second shift value in weight-3 column are the same

=>guarantee 1st parity vector in U is correct. parity bit region Q for bit-flipping operation . parity bit region U for non bit-flipping.

Complexity Comparison We analyze the number of modulo 2 additions required

during encoding process. compare complexity of our proposed scheme with the

Richardson’s scheme [5].

Simulation Results

we present performance of LDPC codes by comparing simulation results on the effect of H matrix modification to cycle optimized standard H matrix in [1].

We apply AWGN channel model the modulation is fixed to BPSK. The iterative min-sum algorithm, and the

maximum number of iteration is set to 50.

As code rate increases or codeword length decreases, error floor due to deviation from cycle optimization design is apparent.

H matrix required by proposed encoding scheme does not induce any noticeable performance degradation in practical point of view.

Conclusion

This paper proposed a new low-complexity encoding method for QC-LDPC codes.

We have demonstrated that overall encoding computational complexity is smaller than conventional efficient encoding scheme.

the proposed LDPC encoding scheme is directly applicable to current WLAN and WiMAX standards which have dual-diagonal structure with one weight-3 parity column

Comment

Number of additions not necessarily less than Richardson’s Scheme if we use Memory.

But the encoding time is less Richardson’s Scheme

Another scheme without modification of parity-check

matrix