*Department of Telecommunication Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand
E-mail: [email protected] †Department of Electronic and Telecommunication Engineering, Faculty of Engineering,
National University of Laos, Laos PDR.
Abstract— An implementation of chaotic encoder-decoder on FPGA will be proposed in this paper. Overflow non-linearity by using 2’s complement number in digital filter causes the phenomenon called “Chaos” in digital filter. An IIR filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. Filter coefficients of both encoder and decoder can be compared to the secret key in private-key crypto system. However, if filter coefficients of chaotic decoder are not same as filter coefficients of chaotic encoder, ciphertext cannot decrypt to get original plaintext. Both chaotic encoder and decoder will be implemented on FPGA to demonstrate the hardware prototype of chaotic crypto system.
I. INTRODUCTION
Chaos theory [1] describes the behavior of dynamic systems (time-variant systems). The systems are called chaotic systems which look like random or stochastic. In fact, chaotic systems are deterministic. In physics and mathematics, they define the systems as nonlinear systems that highly sensitive dependence on initial conditions. Today chaos phenomenon has been discovered and analyzed in numerous of experiments such as chaos in digital filter [2]-[4]. Therefore, this paper will be applied the application of chaos in digital filter in chaotic encoder-decoder [7]-[8] for security of the data. The encoder-decoder based on overflow non-linearlity [1], [5], [7] and [9] which is important for digital filter to generate chaotic signals [5]-[6].
This paper will be proposed encoder-decoder based on chaos in digital filter. An IIR filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. In section II presents design of encoder-decoder based on chaos in digital filter. In section III presents implementation of chaotic encoder-decoder on FPGA. In section IV presents result of simulation and experimental hardware.
II. DESIGN OF ENCODER – DECODER BASED ON CHAOS IN DIGITAL FILTER
In this section presents principle and design of chaotic encoder-decoder which is applied from chaos in digital filter for security of the data using second order digital filter structure [5].
A. Design of encoder using IIR 2nd order digital filter IIR 2nd order digital filter structure is shown in figure 1.
( )x k ( )f i ( )y k
1z−
1z−
1c
2c
Fig. 1 IIR 2nd order digital filter structure.
If ( )f i is not consider, difference equation can be show in recursive form in (1) and transfer function is shown in (2).
( ) ( ) ( ) ( )1 21 2y k x k c y k c y k= + − + − (1)
( ) ( )( ) ( )1 2
1 2
11
Y zH z
X z c z c z− −= =
− − (2)
To be unstable systems, at least one coefficient of digital
filter have to out boundary of the triangular region that is shown in Fig. 2.
1c
2c
Fig. 2 Triangular stable region.
An implementation of this system is necessary to determine the length of word with finite word-length because overflow
will be occurred when fixed-point is defined. So, simulation has to use ( )f i which is overflow characteristic function as shown in (3). Characteristic of ( )f i is shown in Fig. 3. Therefore, difference equation of Fig. 1 can be shown in (4).
( ) ( )1 mod 2 1f x x= + −⎡ ⎤⎣ ⎦ (3)
( ) ( ) ( ) ( )1 2{ 1 2 }y k f x k c y k c y k= + − + − (4)
( )f x
x
Fig. 3 Characteristic of ( )f i
B. Design of decoder using FIR 2nd order digital filter FIR 2nd order digital filter structure is shown in Fig. 4.
( )f i ( )z k
1z−
ˆ( )y k
2c
1z−
1c
Fig. 4 FIR 2nd order digital filter structure
If ( )f i is not consider, difference equation of FIR 2nd order digital filter can be show in (5) and transfer function is shown in (6)
1 2( ) ( ) ( 1) ( 2)z k y k c y k c y k= − − − − (5)
( ) ( )( )
1 21 21
Z zH z c z c z
Y z− −= = − − . (6)
As same as encoder. Simulation has to use ( )f i so
difference equation can be shown in (7)
1 2( ) { ( ) ( 1) ( 2)}z k f y k c y k c y k= − − − − (7) To recovery the data, decoded coefficient has to be the
same as encoded coefficient for pole-zero cancellation.
III. IMPLEMENTATION
An implementation in this section will show design of encoder-decoder on FPGA using 8-bit input data.
A. Design of 8-bit encoder using IIR 2nd order digital filter Step to design:
Difference equation of encoder is y(k) = x(k)+c1y(k-1)+c2y(k-2)
Determine initial conditions are y(-1) = 0, y(-2) = 0 Determine data formats are x.xxx xxxx. Congratulate 2-bit on MSB of coefficients, so the
coefficient formats are xxx.xxx xxxx. We have to increase word-length of input data by congratulate 2-bits on MSB for process and truncate 2-bit on MSB of output data. The structure of 8-bit encoder is shown in Fig. 5.
Fig. 5 8-bit IIR 2nd order filter structure
Result of 10-bits Tap0 multiply by 10-bits c1 is 20-bits M1, we use only 10-bits M1 which is M1(16:7). For design of hardware implementation, we do not use ( )f i because overflow will occur by itself.
B. Design of 8-bit decoder using FIR 2nd order digital filter Step to design:
Difference equation of encoder is y(k) = x(k)-c1y(k-1)-c2y(k-2)
Determine initial conditions are x(-1) = 0, x(-2) = 0 Determine data formats are x.xxx xxxx. Congratulate 2-bit on MSB of coefficients, so the
coefficient formats are xxx.xxx xxxx. We have to increase word-length of input data by
congratulate 2-bits on MSB for process and truncate 2-bit on MSB of output data. The 8-bit decoder structure can be shown in Fig. 6.
Fig. 6 8-bit FIR 2nd order filter structure
Result of 10-bits Tap0 multiply by 10-bits c1 is 20-bits M1, we use only 10-bits M1 which is M1(16:7). The RTL schematic structure can be shown in Fig. 7.
Fig. 7 RTL schematic structure of 8-bit encoder-decoder
For experiment, we use two computers for data communications through serial port. Alice computer sends plaintexts to chaotic encoder on FPGA via serial communication then decrypted the ciphertext by chaotic decoder and then transmit recovered data to Bob computer via serial communication through serial port. If Bob computer need to send message to Alice, it uses the same procedure. Charlie computer is used for test security of the system by trap data from Alice and Bob.
IV. RESULTS
The results are shown that the system can indicate to chaotic system. We will prove that if filter coefficients of encoder are same as filter coefficients of decoder, ciphertext can decrypt to get original plaintext in this session.
A. Simulated results To indicate the system is chaotic system, we assign the
input is zero and determine initial conditions are y(-1) = -0.6135, y(-2) = 0.6135 and filter coefficients are c1 = 0.5, c2 = -1 using 10,000 data points then plot trajectory of the system by output feedback first order compare to output feedback second order. The trajectory of the system is shown in Fig. 8.
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1trajectory
output feedback first order
outp
ut fe
edba
ck s
econ
d or
der
Fig. 8 Trajectory from 8-bit second order digital filter.
From Fig. 8, the trajectory explains a fractal geometry or self-similarity which is a property that indicates chaos behavior
For simulation, we use audio data as input and determine encoded-decoded coefficients be the same c1 = 0.5, c2 = -1. The results are shown in Fig. 9 and Fig. 10.
Fig. 9 The results of chaotic encoded-decoded for audio data.
Fig. 10 Spectrum of chaotic encoded-decoded sound data.
From Fig. 9 and Fig. 10 show that decoded data is same as input data. Moreover, we use image as input and configure encoder-decoder coefficients be the same. The result is shown in Fig. 11.
Fig. 11 The result of chaotic encoded-decoded for image data.
B. Hardware Simulation and Experimental results Hardware simulation of 8-bits encoder-decoder which
defines the same filter coefficients is shown in Fig. 12. So, ciphertext can decrypt to get original data. If filter coefficients are not the same, ciphertext cannot decrypt to get original data that show in Fig. 13.
Fig. 12 Simulation result of 8-bits encoder-decoder using the same filter coefficients.
Fig. 13 Simulation result of 8-bits encoder-decoder using difference filter coefficients.
For experimental results of chaotic encoder-decoder which are implemented on FPGA, we measure voltage of 8-bit input signal, encrypted signal and decrypted signal. The experimental results are shown in Fig. 14-19.
Fig. 14 Voltage of 8-bit signals using filter coefficients of chaotic decoder
are same as filter coefficients of chaotic encoder 1st time
Fig. 15 Voltage of 8-bit signals using filter coefficients of chaotic decoder
are same as filter coefficients of chaotic encoder 2nd time
Fig. 16 Voltage of 8-bit signals using filter coefficients of chaotic decoder
are same as filter coefficients of chaotic encoder 3rd time
In Fig. 14-16 we use filter coefficients of chaotic decoder are same as filter coefficients of chaotic encoder. In addition, ciphertext will change every process even if the same input. It represents the dynamic system. In Fig. 17-19 we use filter coefficients of chaotic decoder are not same as filter coefficients of chaotic encoder. The results of data transmission using serial communications with chaotic encoder-decoder are shown in Fig. 20-21. The sender “Alice” sends “telecommunication” to chaotic encoder on FPGA then decrypt the ciphertext by chaotic decoder and transmit recovered data to receiver “Bob”.
Fig. 17 Voltage of 8-bit signals using filter coefficients of chaotic decoder
are not same as filter coefficients of chaotic encoder 1st time
Fig. 18 Voltage of 8-bit signals using filter coefficients of chaotic decoder
are not same as filter coefficients of chaotic encoder 2nd time
Fig. 19 Voltage of 8-bit signals using filter coefficients of chaotic decoder
are not same as filter coefficients of chaotic encoder 3rd time
In addition, we assume both Alice and Bob know the initial conditions and filter coefficients. We use Charlie computer to trap the data that is ciphertext in the medium.
Fig. 20 Serial communications with chaotic encoder-decode using same filter coefficients
Fig. 21 The data that is captured by Charlie
V. CONCLUSIONS
In this paper, we have presented an implementation of chaotic encoder-decoder on FPGA that using overflow non-linearity in digital filter to occur chaos in digital filter. Filter coefficients must be the same on both encoder and decoder for recovery ciphertext to get original plaintext. The results of
simulation are shown in Fig. 9-11 and the results of experiment are shown in Fig. 14-19 which represent the dynamic system. We can improve performance of encoder-decoder by using higher order digital filter with a cascade realization. Higher order digital filter will increase number of secret key (Filter coefficient) which mean increase higher security.
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