Chap 1 Basic Structure of Comp

8/17/2019 Chap 1 Basic Structure of Comp

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Faculty of Electrical and Electronic Engineering

Semester II, Session 2015/2016

BEC30303

Computer Architecture and Organization

Mohamad Hairol JabbarDepartment of Computer Engineering

http://fkee.uthm.edu.my/mhjabbar

Chapter 1:

Basic Structure of Computers


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COURSE CHAPTERS

Computer Architecture and Organization (BEC30303) | Chapter 1: Basic Structure of Computers

In this chapter, we will discuss about the overview of computer such asbasic elements, performance, and how it has been evolving.

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OUTLINE

• Computer types

• Functional units

• Basic operational concepts• Performance

• Computer evolution

Computer Architecture and Organization (BEC30303) | Chapter 1: Basic Structure of Computers 3


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COMPUTER TYPES


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WHAT IS A COMPUTER?

• An electronic device that can input, process,output and store data .

• It takes data and converts it into information• Data is a single fact of idea

• Information is data that has been processed

so that it can be presented in an organizedand meaningful way .

• Data = pieces of jigsaw puzzle, information =finished puzzle


Source: Go! All in One: Computer Conceptsand Applications, Pearson Education, 2012

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BASIC COMPUTER FUNCTIONS

• Input – gathers data/allows a user to add data

• Process – data is converted into information

• Output – display/present the processedresults

• Storage – data/information is stored for future

use


Source: Go! All in One: Computer Conceptsand Applications, Pearson Education, 2012

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COMPUTER TYPES

• Embedded computers – application specificcomputers

• Personal computers – general purposecomputers

• Servers and enterprise systems

• Supercomputers and grid computers – highest performance computers


What is the number 1 supercomputer inthe word? And how fast is it (teraflops)?

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FUNCTIONAL UNITS


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FUNCTIONAL UNIT BLOCKS


Basic functional units of a computer: processor, IO, and memory ,used to perform basic functions (input, process, output, storage)

I/O Processor

Output

Memory

Input andArithmetic

logic

Control

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INFORMATION HANDLED

• Instructions/machine instructions : – Govern the transfer of information within a

computer (between functional unit blocks)

– Specify the arithmetic and logic operations to be

performed by the computer

– It is the program• Data :

– Used as operands by the instructions

– It is the source of the program



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MEMORY UNIT

• Store programs and data • Two classes of storage:

– Primary storage: fast, store program in memorywhile they are being executed, large number ofsemiconductor storage cells

– Secondary storage: larger and cheaper


Primary storage Secondary storage

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ALU

• Arithmetic logic unit • Execute most computer operations – add,

sub, multiply• Primary functions:

– Load operands into memory, bring them to the

processor, perform operations in ALU, store theresults back to memory or retain in the processor



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CONTROL UNIT

• Control all computer operations • Also manage timing signals for IO transfers

• Operation of computer: – Accept information in the form of programs and

data through an input unit and store it in thememory

– Fetch the information stored in the memory,under program control, into an ALU, when data isprocessed

– Output the processed data through an output unit – Control all activities inside the machine through a

control unit



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CONTROL UNIT IN A PROCESSOR



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DATA PATH AND CONTROL PATH


Two types of functional units:

elements that operate on data values (combinational) – ALU

elements that contain state (state elements) – memory

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EXECUTION STEPS


Step name Action for R-typeinstructions

Action for Memory-reference Instructions

Action forbranches

Action for jumps

Instruction fetch IR = MEM[PC]

PC = PC + 4

Instruction decode/register fetch A = Reg[IR[25-21]]B = Reg[IR[20-16]]

ALUOut = PC + (sign extend (IR[15-0])


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BASIC OPERATIONAL CONCEPTS


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REVIEW UNDERSTANDING

• Activity in a computer in governed byinstructions

• To perform a task, a program consists of a listof instructions is stored in the memory

• Individual instructions are brought from the

memory into the processor, which executesthe specified operations

• Data to be used as operands are also storedin the memory



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EXAMPLES OF TYPICAL INSTRUCTION

• Add LOCA, R0• Add the operand at memory location LOCA to

the operand in a register R0 in the processor.• Place the sum into register R0.

• The original contents of LOCA are preserved.

• The original contents of R0 is overwritten.

• Instruction is fetched from the memory into

the processor – the operand at LOCA isfetched and added to the contents of R0 – theresulting sum is stored in register R0.



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SEPARATE MEMORY ADDRESS

• Load LOCA, R1• Add R1, R0

• Whose contents will be overwritten ?


Be careful with instruction set, different architectureshave different concepts for executing instructions!

For x86 architecture:

ADD destination, source = destination


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PROCESSOR-MEMORY CONNECTION


Processor

Memory

PC

IR

MDR

Control

ALU

Rn 1-

R1

R0

MAR

n general purposeregisters

Connection betweenprocessor and memory

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REGISTERS

• Common registers in processors: – Instruction register (IR)

– Program counter (PC)

– General purpose register (R0-Rn-1)

– Memory address register (MAR)

– Memory data register (MDR)



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TYPICAL OPERATION STEPS (1/2)

• Program resides in the memory through inputdevices

• PC is set to point to the first instruction

• The contents of PC are transferred to MAR

• A read signal is sent to the memory

• The first instruction is read out and loadedinto MDR

• The contents of MDR are transferred to IR• Decode and execute the instruction



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TYPICAL OPERATION STEPS (2/2)

• Get operands for ALU – General purpose register

– Memory (address to MAR, read, MDR to ALU)

• Perform operation in ALU

• Store the result back

– To general purpose register

– To memory



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INTERRUPT

• Normal execution of programs may bepreempted if some devices requires urgentservicing

• The normal execution of the current programmust be interrupted – the device raises aninterrupt signal

• The process – interrupt service routine

• Examples:

– Current system information backup and restore(PC, general purpose registers, controlinformation, specific information)



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BUS STRUCTURES

• There are many ways to connect differentcomponents inside a computer

• A group of lines that serves as a connectingpath for several devices is called a bus

• Address/data/control bus



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BUS STRUCTURE EXAMPLE


MemoryInput Output Processor

Block diagram of single bus structure

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SPEED ISSUE FOR BUS

• Different devices have differenttransfer/operation speeds

• If the speed of bus is bounded by the slowestdevice connected to it , the efficiency will bevery low

• How to solve this?• A common approach – use buffers (temporary

data storage in the communication lines)



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PERFORMANCE


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PERFORMANCE

• The most important measure of a computeris:

– How quickly it can execute programs

– How many instructions it can execute within aperiod of time

• Three factors affect performance: – Hardware design

– Instruction set

– Compiler


P H


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PERFORMANCE – HARDWARE

• Processor time to execute a programdepends on the hardware involved in theexecution of individual machine instructions.


Mainmemory Processor

Bus

Cachememory

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P M


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PERFORMANCE – MEMORY

• High speed and high capacity of primarymemory can improve the performance of acomputer

• The processor and a relatively small cachememory can be fabricated on a singleintegrated circuit.

• Consideration when integrating cachememories: – Speed

– Cost

– Memory management


P P C


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PERFORMANCE – PROCESSOR CLOCK

• High clock rate can improve the performanceof a computer

• The execution of each instruction is dividedinto several steps, each of which completes inone/several clock cycles

• Hertz – cycle per second


P E


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PERFORMANCE EQUATION

• T – processor time required to execute aprogram that has been prepared in high levellanguage

• N – number of actual machine languageinstructions needed to complete the execution

• S – average number of basic steps needed toexecute one machine instruction. Each stepcompletes in one clock cycle

• R – clock rate/speed


R

S N T

×= How to improve T?

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PIPELINE/SUPERSCALAR PROCESSOR


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PIPELINE /SUPERSCALAR PROCESSOR

• Instructions are not necessarily executed oneafter another

• The value of S does not have to be thenumber of clock cycles to execute oneinstruction

• Pipeline – overlapping the execution ofsuccessive instructions

• Superscalar – multiple instruction pipelines are implemented in the processor

• Goal – reduce S (could become


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CLOCK RATE /SPEED

• Increase clock rate: – Improve the IC technology to make circuits faster

– Reduce the amount of processing done in one

basic step (but may increase the number of basicsteps needed)

• Increase R that are entirely caused byimprovements in IC technology affect allaspects of the processor’s operation equally

except the time to access the main memory


CISC/RISC


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CISC/RISC

• CISC – Complex instruction set computers • RISC – Reduce instruction set computers

• RISC vs CISC = trade off between N and S • A key consideration is the use of pipelining:

– S close to 1 even though the number of basic

steps per instruction may be considerably larger – It is much easier to implement efficient pipelining

in processor with simple instruction sets



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PERFORMANCE MEASURE


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PERFORMANCE MEASURE

• T is difficult to measure – depends on variouselements

• Measure computer performance usingbenchmark programs

• System performance evaluation corporation

(SPEC) selects and publishes representativeapplication programs for different applicationsdomains, together with test results for many

commercial available computers


SPEC MEASUREMENT


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SPEC MEASUREMENT


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iSPEC ratingSPEC

ratingSPEC

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under testcomputeron thetimeRunning

computerreferenceon thetimeRunning

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MULTIPROCESSOR COMPUTER


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MULTIPROCESSOR COMPUTER

• Can be: – Execute a number of different application tasks in

parallel

– Execute subtasks of a single large task in parallel

• All processors have access to all memory –

shared memory• Cost – processors, memory units, complex

interconnection networks



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COMPUTER EVOLUTION

COMPUTER EVOLUTION


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COMPUTER EVOLUTION

• First generation – vacuum tube • Second generation – transistor

• Third generation – integrated circuit • Later generation – LSI, VLSI, ULSI


1ST GENERATION – VACUUM TUBE


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1 GENERATION VACUUM TUBE

• ENIAC: electronic numerical integrator andcomputer

• Designed and constructed at the Univ. ofPennsylvania (started 1943, completed 1946)


Source: http://classes.soe.ucsc.edu/ Structure of vacuum tube

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VACUUM TUBE AS A SWITCH


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VACUUM TUBE AS A SWITCH


Heated cathode send electrons to theanode. Electron mobility is controlled by a

filament (called a grid). If the grid power isoff, electrons flow to anode (switch on),otherwise, no electrons flow (switch off).

To picture therelative size of avacuum tube.

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ENIAC CHARACTERISTICS


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ENIAC CHARACTERISTICS

• Weight 30 tons• 1500 sq feet of area

• 18,000 vacuum tubes

• 140 kW power consumption

• 5,000 addition operations per second

• Decimal machine• Memory consists of 20 accumulator, each

with 10 digit number

• Manual programming – setting switches,plug/unplug cables


Why it is so large?

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EDVAC


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EDVAC

• Electronic discrete variable computer • Completed 1945

• Stored program concept :

– Attributed to ENIAC designers, most notably themathematician John Von Neumann

– Program represented in a form suitable for

storing in memory alongside the data• IAS computer:

– Princeton Institute of Advanced Studies (IAS)

– Prototype of all subsequent general-purposecomputers


EDVAC PICTURE


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EDVAC PICTURE


Source: http://web.soi.city.ac.uk/archive/image/lists/computers.html

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VON NEUMANN MACHINE


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Structure of the IAS computer, implementedVon Neumann computer architecture model

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IAS MEMORY FORMAT


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• The memory of the IASconsists of 1000 storagelocations (called “words”) of40 bits each

IAS memory formats

• Both data and instructions arestored in the memory

• Numbers are represented inbinary form and each instruction

is a binary code

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IAS COMPUTER STRUCTURE


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Detailed structureof IAS computer

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IAS REGISTERS


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• Contains a word to be stored in memory or sent to the I/Ounit

• Or is used to receive a word from memory or from the I/O unit

Memory buffer register(MBR)

Memory buffer register(MBR)

• Specifies the address in memory of the word to be writtenfrom or read into the MBR

Memory address

register (MAR)

Memory address

register (MAR)

• Contains the 8-bit opcode instruction being executedInstruction register (IR)Instruction register (IR)

• Employed to temporarily hold the right-hand instruction from aword in memory

Instruction bufferregister (IBR)

Instruction bufferregister (IBR)

• Contains the address of the next instruction pair to be fetchedfrom memoryProgram counter (PC)Program counter (PC)

• Employed to temporarily hold operands and results of ALUoperations

Accumulator (AC) andmultiplier quotient (MQ)Accumulator (AC) and

multiplier quotient (MQ)

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IAS OPERATIONS


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Flowchart of IASoperation

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IAS INSTRUCTION SET


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Instructions to beexecuted on the IAS

computer

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COMMERCIAL COMPUTERS


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• UNIVAC: – Universal automatic computer

– First commercial general purpose computers

– For both scientific and commercial applications

– Several version: UNIVAC I (1951), UNIVAC II(1958), UNIVAC III (1962)


IBM COMPUTERS


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• IBM 700 series computers: – Based on vacuum tubes technology

• IBM 701:

– 1953, for scientific applications

– Known as Defense Calculator

• IBM 702: – Targeted for business applications


2ND GENERATION – TRANSISTOR


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• Transistor is invented at Bell Labs in 1947• Is a solid state device made from silicon

• Advantages:

– Dissipates less heat than a vacuum tube

– Smaller

– Cheaper


Source: www.nobelprize.org

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2ND GENERATION CHARACTERISTICS


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• More complex arithmetic/logic/control units • The use of high level programming languages

(assembly languages):

– FOTRAN

– COBOL

• Provision of system software which providedthe ability to:

– Load programs

– Move data to peripherals and libraries

– Perform common computations


2ND GENERATION COMPUTERS


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• Appearance of the digital equipmentcorporation (DEC) in 1957

• PDP-1 (programmed data processor) was

DEC’s first computer

• This began the mini-computer phenomenon

that would become so prominent in the thirdgeneration


IBM 7000 COMPUTER SERIES


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IBM 7090 Computer

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IBM 7094 CONFIGURATION


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An IBM 7094configuration

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3RD GENERATION – INT. CIRCUIT


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• 1958, invention of IC• Discrete component:

– single, self-contained transistor

• Manufactured separately, packaged in theirown containers, soldered or wired together

onto circuit boards• Most important 3rd generation computer –

IBM System/360 and DEC PDP-8


INTEGRATED CIRCUIT


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• A computer consists of gates, memory cells,interconnection among this elements

• The gates and memory cells are constructed

of simple digital electronic components

• Many transistors can be produced at the

same time on a single silicon wafer• Transistors can be connected with a

processor metallization to/from circuits


WAFER /CHIP /GATE


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Relationship amongsilicon wafer, chip andlogic gate

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CHIP GROWTH


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Continuous growth oftransistor count in IC forDRAM memory

Year

Transistor

number

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TRANSISTOR GROWTH TREND


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• Observed by Gordon Moore, 1965, laterknown as Moore’s Law

• The number of transistors that could be put

on a single chip was doubling in 18 months


Moore’s Law, 1965

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MOORE’S LAW EFFECT


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• The cost of computer logic and memorycircuitry has fallen at a dramatic rate

• Electrical path length is shortened in the IC

and increasing operating speed

• Computer becomes smaller and is more

convenient to use in a variety of environments• Reduction in power and cooling requirements

• Fewer interchip connections


IBM SYSTEM /360 COMPUTERS


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DEC PDP-8 COMPUTERS


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DEC PDP-8 BUS STRUCTURE


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PDP-8 bus structure

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LATER COMPUTER GENERATIONS


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• LSI (Large scale integration)• VLSI (Very large scale integration)

• ULSI (Ultra large scale integration)

• Semiconductor memory microprocessors


Still using IC technology, but withmore advanced transistor technology

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CHARACTERISTICS


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Source: http://www.csi.ucd.ie/

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INTEL PROC. REVOLUTION (1/4)


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1970s Processors

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1980s Processors

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1990s Processors

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Recent Processors

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COMPUTER EVOLUTION SUMMARY


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The trend is from increasing numberof switching elements in an IC

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IT IS ALL ABOUT SWITCH


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Source: http://www.csi.ucd.ie/ The future of electronic technologyrelies on the new switch technology!

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PERFORMANCE BALANCE (1/2)


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• Adjust the organization and architecture tocompensate for the mismatch among thecapabilities of the various components

• Architecture examples includes: – Increase the number of bits that are retrieved at

one time by making DRAMs “wider” rather than

“deeper” and by using wide bus data paths

– Reduce the frequency of memory access by

incorporating increasingly complex and efficient

cache structures between the processor andmain memory


PERFORMANCE BALANCE (2/2)

– Change the DRAM interface to make it more


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Change the DRAM interface to make it moreefficient by including a cache or other buffering

scheme on the DRAM chip

– Increase the interconnect bandwidth betweenprocessors and memory by using higher speed

buses and a hierarchy of buses to buffer and

structure data flow


IMPROVEMENT IN CHIP ARCHITECTURE


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• Increase hardware speed of processor : – Fundamentally due to shrinking logic gate size

– More gates, packed more tightly, increase clock

rate – Reduce signal propagation time

• Increase size and speed of caches :

– Reduce cache access time

• Change processor organization/architecture :

– Increase effective speed of instruction exec. – Parallelism


X86 ARCHITECTURE


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• Results of decades of design effort oncomplex instruction set computers (CISCs)

• Incorporates the sophisticated design

principles once found only on mainframesand supercomputers


X86 EVOLUTION (1/2)


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• 8080: – First general purpose microprocessor

– 8 bits machine with 8 bits data path to memory

• 8086: – 16 bits machine

– Used an instruction cache or queue• 80286:

– Enabled addressing a 16 MB memory instead of

just 1 MB


X86 EVOLUTION (2/2)


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• 80386: – Intel’s first 32 bit machine

– First Intel processor to support multitasking

• 80486: – More sophisticated cache technology and

instruction pipelining

– Built-in math coprocessor


X86 EVOLUTION – PENTIUM


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Pentium

• Superscalar

• Multipleinstructionsexecuted inparallel

Pentium Pro

• Increasedsuperscalarorganization

• Aggressiveregisterrenaming

• Branchprediction

• Data flowanalysis

• Speculativeexecution

Pentium II

• MMXtechnology

• Designedspecifically toprocess video,audio, andgraphics data

Pentium III

• Additionalfloating-pointinstructions tosupport 3Dgraphicssoftware

Pentium 4

• Includesadditionalfloating-pointand otherenhancementsfor multimedia

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PROBLEMS – CLOCK /LOGIC (1/2)


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• Power: – Higher density logic and faster clock : increasepower

– Dissipating heat• Memory latency:

– Memory speeds lag processor speed


PROBLEMS – CLOCK /LOGIC (2/2)

RC d l


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• RC delay: – Speed at which electrons flow limited byresistance and capacitance of metal wires

connecting them – Delay increases as RC product increases

– Wire interconnects thinner , increasing resistance

– Wire closer together , increasing capacitance


PROCESSOR-MEMORY SPEED GAP


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Source: Patterson D., Anderson T. et al.: A Casefor Intelligent RAM: IRAM. IEEE Micro (1997)

Huge speedgap andincreasing!

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X86 EVOLUTION – MULTICORE


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Instruction setarchitecture is

backward

compatible withearlier versions

X86 architecture

continues todominate the

processormarket outsideof embedded

systems

X86 architecture

continues todominate the

processormarket outsideof embedded

systems

– Core

• First Intel x86 microprocessor

with a dual core , referring tothe implementation of two

processors on a single chip

– Core 2

• Extends the architecture to 64bits

• Recent Core offerings have upto 10 processors per chip

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PROCESSOR SPEED TRENDS


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Year

Frequencyhas stalled

Number ofprocessor coresis increasing

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MULTICORE

St t t ( ) i l


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• Strategy – use two (or more) simpleprocessors on the chip rather than one morecomplex processor

• The use of multiple processors on the samechip provides the potential to increaseperformance without increasing the clock rate

• Increasing performance through parallelexecution/processing


MANY INTEGRATED CORE (MIC)

Leap in performance as well as the


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• Leap in performance as well as thechallenges in developing software to exploitsuch a large number of cores

• > 50 cores per die/chip • 512 bit SIMD instructions


Source: intel.com

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GPU

Graphic processing unit


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• Graphic processing unit • Core designed to perform parallel operations

on graphics data

• Used as vector processors for a variety ofapplications that require repetitivecomputations

• High computational density and high memorybandwidth

• Throughput processor: many concurrentthreads


EMBEDDED SYSTEMS

• General definition:


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• General definition: – A combination of computer hardware andsoftware , and perhaps additional mechanical or

other parts, designed to perform a dedicatedfunction .

– In many cases, embedded systems are part of a

larger system of product , as in the case of anantilock braking system in a car.


EMBEDDED SYSTEMS EXAMPLEEmbedded System Examples in different market segments


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Almost all electronic devices other than desktop computerand server are embedded system devices!

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ARM PROCESSORS

• Advanced RISC Machine


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• Family of RISC-based microprocessors andmicrocontrollers

• Design microprocessors and license them tomanufacturers

• Most widely used embedded processorarchitecture


www.arm.com

Why RISC is used widely inembedded system devices?

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ARM PROCESSORS EVOLUTIONFamily Notable Features Cache Typical MIPS @

MHz

ARM1 32-bit RISC None


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ARM2 Multiply and swap

instructions;Integrated memory

management unit,

graphics and I/O

processor

None 7 MIPS @ 12 MHz

ARM3 First use of processorcache 4 KB unified 12 MIPS @ 25 MHz

ARM6 First to support 32-bitaddresses; floating-

point unit

4 KB unified 28 MIPS @ 33 MHz

ARM7 Integrated SoC 8 KB unified 60 MIPS @ 60 MHz

ARM8 5-stage pipeline; static

branch prediction

8 KB unified 84 MIPS @ 72 MHz

ARM9 16 KB/16 KB 300 MIPS @ 300MHz

ARM9E Enhanced DSPinstructions

16 KB/16 KB 220 MIPS @ 200MHz

ARM10E 6-stage pipeline 32 KB/32 KB

ARM11 9-stage pipeline Variable 740 MIPS @ 665

MHz

Cortex 13-stage superscalarpipeline Variable 2000 MIPS @ 1 GHz

XScale Applicationsprocessor; 7-stage

pipeline

32 KB/32 KB L1512 KB L2

1000 MIPS @ 1.25GHz

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FINISH

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