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Microprocessor
CUT
Dr Mohamad KHALIL
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Microprocessor- course outline
Memories RAM, ROM
EPROM ,EEPROM Increasing the capacity of the memory Microprocessor 6800
Architecture Addressing modes, instructions
Interrupt Peripherals Parallel Serial Timer
Microcontroller PIC 16F84 Architecture Programming
Microcontroller PIC 16F877A Architecture Programming
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Microprocessor
Memories
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Introduction
Une mmoire est un ensemble de cellules. Une bascule D est une mmoire
Une mmoire est reprsente par une matrice. Elle est adresse pardes lignes et de colonnes. Les informations se trouvent dans la cellule
La cellule commande peut tre lue ou crite selon la commande R/W(read /write)
Cest un exemple dune mmoire 16 cellules. Elle a besoin de 8 lignespour ladressage. Pour adresser une cellule, un seul 1 doit se prsentersur les lignes et sur les colonnes..
Cest pas une bonne solution si la capacit de la mmoire augmentent Exemple: pour une mmoire 1024 bits on a besoin de 20 fils!!
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Memory basics
Au lieu de slectionner une seule cellule par adresse, on pourraslectionner plusieurs cellules par une seule adresse.. On pourra
lire ou crire avec a commande R/W.
Address wires Data wires
If A=110010One cell selected
With 6 address wires,
we can select 64Positions (two bits perPosition)
With n Address wires,we can select 2nPositions (two bits perPosition)
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Memory basics
Lensemble de fils dadresse sappelle bus dadresse: A0,A1 A15 Lensemble de fils de donnes sappelle bus de donnes :D0,D1 Lensemble de fils de contrle sappelle fils de contrle: R/W, CLK, R, S
Les caractristiques de chaque mmoire sont: Temps daccs (minimal time needed to read or write its content) Capacit
Chaque mmoire a une entre CS pour enable ou disable la mmoire.Elle est utilise quand plusieurs mmoires sont utilises par le microprocesseur.
toutes les mmoires ont le mme bus de donnes et cest Cs qui choisit unemmoire a la fois.
2kx n memory
ADRS OUTDATACSWR
kn
n
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Capacity
1 address bit: 2 locations, 0-------1 2 address bits: 4 locations, 0------3
3 address bits: 8 locations, 0------7 4 address bits: 16 locations, 0------15 (F) 5 address bits: 32 locations, 0------31(1F) 6 address bits: 64 locations, 0------63(3F) 7 address bits: 128 locations, 0------127(7F) 8 address bits: 256 locations, 0------255(FF) 9 address bits: 512 locations, 0------511(1FF) 10 address bits: 1024 locations, 0------1023(3FF) (1K) 11 address bits: 2048 locations, 0------2047(7FF)(2K) 12 address bits: 4096 locations, 0------4095(FFF)(4K) 13 address bits: 8K locations, 0------1FFF
14 address bits: 16K locations, 0------3FFF 15 address bits: 32K locations, 0------7FFF 16 address bits: 64K locations, 0------FFFFNotes on addres 1Kilo:210=1024 Notes on data: 8 bits=byte
1Mega: 220 16 bits=word
1Gega:230 32 bits=long word
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Classification of memory
Classes of memories:
RAM SRAM DRAM RDD-RAM SDRAM
ROM ROM PROM EPROM EEPROM
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Random access memory
Sequential circuits all depend upon the presence of memory. A flip-flop can store one bit of information.
A register can store a single word, typically 32-64 bits. Random access memory, or RAM, allows us to store even larger amounts
of data. Well see:
The basic interface to memory. How you can implement static RAM chips hierarchically.
This is the last piece we need to put together a computer!
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Introduction to RAM
Random-access memory, or RAM, provides large quantities of temporarystorage in a computer system.
Remember the basic capabilities of a memory: It should be able to store a value. You should be able to read the value that was saved. You should be able to change the stored value.
A RAM is similar, except that it can store manyvalues.
An addresswill specify which memory value were interested in. Each value can be a multiple-bit word (e.g., 32 bits).
Well refine the memory properties as follows:
A RAM should be able to:
- Store many words, one per address- Read the word that was saved at a particular address
- Change the word thats saved at a particular address
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Picture of memory
You can think of computer memory as being onebig array of data.
The address serves as an array index. Each address refers to one word of data.
You can read or modify the data at any givenmemory address, just like you can read ormodify the contents of an array at any given
index. If youve worked with pointers in C or C++, thenyouve already worked with memory addresses.
Address Data
0000
00010002
.
.
.
.
.
.
.
.
.
.
FFFD
FFFE
FFFF
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Block diagram of RAM
This block diagram introduces the main interface to RAM. A Chip Select, CS, enables or disables the RAM. ADRSspecifies the address or location to read from or write to. WRselects between reading from or writing to the memory.To readfrom memory, WR should be set to 0.
OUTwill be the n-bit value stored at ADRS.To write to memory, we set WR = 1.
DATAis the n-bit value to save in memory.
This interface makes it easy to combine RAMs together, as well see.
2kx n memory
ADRS OUTDATACSWR
kn
n CS WR Memory operation0 x None1 0 Read selected word
1 1 Write selected word
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Memory sizes
We refer to this as a 2kx n memory. There are k address lines, which can specify one of 2kaddresses.
Each address contains an n-bit word.
For example, a 224x 16 RAM contains 224= 16M words, each 16 bits long. The RAM would need 24 address lines. The total storage capacityis 224x 16 = 228bits.
2kx n memory
ADRS OUT
DATACSWR
k
n
n
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Typical memory sizes
Some typical memory capacities: PCs usually come with 128-512MB RAM.
PDAs have 8-64MB of memory. Digital cameras and MP3 players can have
32MB or more of storage.
Many operating systems implement virtualmemory, which makes the memory seem larger
than it really is. Most systems allow up to 32-bit addresses.This works out to 232, or about four billion,different possible addresses.
With a data size of one byte, the result isapparently a 4GB memory!
The operating system uses hard disk spaceas a substitute for real memory.
Address Data
00000000
0000000100000002
.
.
.
.
.
.
.
.
.
.
FFFFFFFD
FFFFFFFE
FFFFFFFF
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Reading RAM
To readfrom this RAM, the controlling circuit must: Enable the chip by ensuring CS = 1.
Select the read operation, by setting WR = 0. Send the desired address to the ADRS input. The contents of that address appear on OUT after a little while.
Notice that the DATA input is unused for read operations.
2kx n memory
ADRS OUTDATA
CSWR
kn
n
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Writing RAM
To writeto this RAM, you need to: Enable the chip by setting CS = 1.
Select the write operation, by setting WR = 1. Send the desired address to the ADRS input. Send the word to store to the DATA input.
The output OUT is not needed for memory write operations.
2kx n memory
ADRS OUTDATA
CSWR
kn
n
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Static memory
How can you implement the memory chip? There are many different kinds of RAM.
Well start off discussing static memory, which is most commonlyused in caches and video cards.
Later wemention a little about dynamic memory, which forms thebulk of a computers main memory.
Static memory is modeled using one latchfor each bit of storage.
Why use latches instead of flip flops? A latch can be made with only two NAND or two NOR gates, but aflip-flop requires at least twice that much hardware.
In general, smaller is faster, cheaper and requires less power. The tradeoff is that getting the timing exactly right is a pain.
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Starting with latches
To start, we can use one latch to store each bit. A one-bit RAM cellisshown here.
Since this is just a one-bit memory, an ADRS input is not needed. Writing to the RAM cell:
When CS = 1 and WR = 1, the latch control input will be 1. The DATA input is thus saved in the D latch.
Reading from the RAM cell and maintaining the current contents: When CS = 1 or when WR = 0, the latch control input is also 0, so
the latch just maintains its present state.
The current latch contents will appear on OUT. CS=0, C=0 , no changes
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My first RAM
We can use these cellsto make a 4 x 1 RAM.
Since there are fourwords, ADRS is two bits. Each word is only one
bit, so DATA and OUTare one bit each.
Word selection is donewith a decoder attachedto the CS inputs of theRAM cells. Only one cellcan be read or writtenat a time.
Notice that the outputsare connected togetherwith a singleline!
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Those funny triangles
The triangle represents a three-state buffer. Unlike regular logic gates, the output can be one of threedifferent
possibilities, as shown in the table.
Disconnected means no output appears at all, in which case its safe toconnect OUT to another output signal.
The disconnected value is also sometimes called high impedanceor Hi-Z.
EN IN OUT
0 x Disconnected
1 0 0
1 1 1
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Connecting three-state buffers together
You can connect several three-statebuffer outputs together if you can
guaranteethat only one of them isenabled at any time.
The easiest way to do this is to use adecoder!
If the decoder is disabled, then all thethree-state buffers will appear to bedisconnected, and OUT will also appeardisconnected.
If the decoder is enabled, then exactlyone of its outputs will be true, so onlyone of the tri-state buffers will be
connected and produce an output. The net result is we can save some wireand gate costs. We also get a little moreflexibility in putting circuits together.
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Bigger and better
Here is the 4 x 1 RAMonce again.
How can we make awider memory withmore bits per word, likemaybe a 4 x 4 RAM?
Duplicate the stuff inthe blue box!
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Bigger RAMs from smaller RAMs
We can use small RAMs as building blocks for making larger memories,by following the same principles as in the previous examples.
As an example, suppose we have some 64K x 8 RAMs to start with: 64K = 26x 210= 216, so there are 16 address lines. There are 8 data lines.
8816
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8
8
16
Making a larger memory
We can put four 64K x 8 chipstogether to make a 256K x 8
memory. For 256K words, we need 18address lines.
The two most significantaddress lines go to thedecoder, which selects one of
the four 64K x 8 RAM chips. The other 16 address lines are
shared by the 64K x 8 chips.
The 64K x 8 chips also share WRand DATA inputs.
This assumes the 64K x 8 chipshave three-state outputs.
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Analyzing the 256K x 8 RAM
There are 256K words of memory,spread out among the four smaller
64K x 8 RAM chips. When the two most significantbits of the address are 00, thebottom RAM chip is selected. Itholds data for the first 64Kaddresses.
The next chip up is enabled whenthe address starts with 01. Itholds data for the second 64Kaddresses.
The third chip up holds data for
the next 64K addresses. The final chip contains the data ofthe final 64K addresses.
8
8
16
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Address ranges
8
8
16 11 1111 1111 1111 1111 (0x3ffff)
to
11 0000 0000 0000 0000 (0x30000)
10 1111 1111 1111 1111 (0x2ffff)
to
10 0000 0000 0000 0000 (0x20000)
01 1111 1111 1111 1111 (0x1ffff)
to
01 0000 0000 0000 0000 (0x10000)
00 1111 1111 1111 1111 (0x0ffff)
to
00 0000 0000 0000 0000 (0x00000)
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Making a wider memory
You can also combine smaller chips to make wider memories, with thesame number of addresses but more bits per word.
Here is a 64K x 16 RAM, created from two 64K x 8 chips. The left chip contains the most significant 8 bits of the data. The right chip contains the lower 8 bits of the data.
16
8 8
8 8
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Other memories
Last time we showed how to build arbitrarily-large static memoriesfrom single-bit RAM cells.
Today well look at some other kinds of memories. Dynamic RAM is used for the bulk of computer memory. Read-only memories and PLAs are two programmable logic devices,
which can be considered as special types of memories.
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Dynamic memory in a nutshell
Dynamic memoryis built with capacitors. A stored charge on the capacitor represents a logical 1.
No charge represents a logic 0. However, capacitors lose their charge after a few milliseconds. The
memory requires constant refreshingto recharge the capacitors.(Thats whats dynamic about it.)
Dynamic RAMs tend to be physically smaller than static RAMs.
A single bit of data can be stored with just one capacitor and onetransistor, while static RAM cells typically require 4-6 transistors. This means dynamic RAM is cheaper and densermore bits can be
stored in the same physical area.
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SDRAM
Synchronous DRAM, or SDRAM, is one ofthe most common types of PC memory now.
Memory chips are organized into modulesthat are connected to the CPU via a 64-bit(8-byte) bus.
Speeds are rated in megahertz: PC66, PC100and PC133 memory run at 66MHz, 100MHzand 133MHz respectively.
The memory bandwidthcan be computed bymultiplying the number of transfers persecond by the size of each transfer.
PC100 can transfer up to 800MB persecond (100MHz x 8 bytes/cycle).
PC133 can get over 1 GB per second.(from amazon.com)
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DDR-RAM
A newer type of memory is Double Data Rate, or DDR-RAM. Its very similar to regular SDRAM, except data can be transferred on
boththe positive and negative clock edges. For 100-133MHz buses, theeffective memory speeds appear to be 200-266MHz.
This memory is confusingly called PC1600 and PC2100 RAM, because 200MHz x 8 bytes/cycle = 1600MB/s 266MHz x 8 bytes/cycle = 2100MB/s.
DDR-RAM has lower power consumption, using 2.5V instead of 3.3V likeSDRAM. This makes it good for notebooks and other mobile devices.
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RDRAM
Another new type of memory called RDRAMis used in the Playstation 2 as well as some
Pentium 4 computers. The data bus is only 16 bits wide. But the memory runs at 400MHz, and data
can be transferred on both the positive andnegative clock edges.
That works out to a maximum transferrate of 1.6GB per second.
You can also implement two channelsof memory, resulting in up to 3.2GB/s ofbandwidth.
(from amazon.com)
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Dynamic vs. static memory
In practice, dynamic RAM is used for a computers main memory, sinceits cheap and you can pack a lot of storage into a small space.
These days you can buy 256MB of memory for as little as $60. You can also load a system with 1.5GB or more of memory. The disadvantage of dynamic RAM is its speed.
Transfer rates are 800MHz at best, which can be much slower thanthe processor itself.
You also have to consider latency, or the time it takes data to travelfrom RAM to the processor. Real systems augment dynamic memory with small but fast sections of
static memory called caches.
Typical processor caches range in size from 128KB to 320KB.
Thats small compared to a 128MB main memory, but its enough tosignificantly increase a computers overall speed.
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Read Only Memory (ROM)
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Read Only Memory (ROM)
Read but cannot write.
Non volatile. Used for: Microprogramming. System programs. Whole programs in embedded systems.
Library subroutines and function tables. Constants.
Manufactured with the data wired into the chip. No room for mistakes.
M d f
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Memories and functions
ROMs are actually combinational devices, notsequential ones!
You cant store arbitrary data into a ROM,so the same address will always contain thesame data.
You can think of a ROM as a combinationalcircuit that takes an address as input, andproduces some data as the output.
A ROM tableis basically just a truth table. The table shows what data is stored at each
ROM address.
You can generate that data combinationally,using the address as the input.
Address
A2A1A0
Data
V2V1V0
000 000001 100
010 110
011 100
100 101
101 000
110 011
111 011
D d
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Decoders
We can already convert truth tables to circuits easily, with decoders.
For example, you can think of this old circuit as a memory that storesthe sum and carry outputs from the truth table on the right.
X Y Z C S0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
ROM t
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ROM setup
ROMs are based on this decoder implementation of functions. A blank ROM just provides a decoder and several OR gates.
The connections between the decoder and the OR gates areprogrammable, so different functions can be implemented. To program a ROM, you just make the desired connections between the
decoder outputs and the OR gate inputs.
ROM l
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ROM example
Here are three functions, V2V1V0, implemented with an 8 x 3ROM. Blue crosses (X) indicate connections between decoder outputs and OR
gates. Otherwise there is no connection.
V2= m(1,2,3,4) V1= m(2,6,7) V0= m(4,6,7)
A2A1A0
Th l i
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V2 V1 V0
A
2A1A0
The same example again
Here is an alternative presentation of the same 8 x 3 ROM, usingabbreviated OR gates to make the diagram neater.
V2= m(1,2,3,4)V1= m(2,6,7)
V0= m(4,6,7)
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ROM RAM
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ROMs vs. RAMs
There are some important differences between ROM and RAM. ROMs are non-volatiledata is preserved even without power. On
the other hand, RAM contents disappear once power is lost. ROMs require special (and slower) techniques for writing, so theyreconsidered to be read-only devices.
Some newer types of ROMs do allow for easier writing, although thespeeds still dont compare with regular RAMs.
MP3 players, digital cameras and other toys use CompactFlash,Secure Digital, or MemoryStick cards for non-volatile storage. Many devices allow you to upgrade programs stored in flash ROM.
P mm bl l i
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Programmable logic arrays
A ROM is potentially inefficient because it uses a decoder, whichgenerates allpossible minterms. No circuit minimization is done.
Using a ROM to implement an n-input function requires: An n-to-2ndecoder, with n inverters and 2nn-input AND gates. An OR gate with up to 2ninputs. The number of gates roughly doubles for each additional ROM input.
A programmable logic array, or PLA, makes the decoder part of the
ROM programmable too. Instead of generating all minterms, you canchoose which products (not necessarily minterms) to generate.
PLA
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PLA
PROM
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PROM
Programmable read only memory
Non volatile. Can be programmed - written into - only once. Programming is done electrically and can be done after manufacturing. Special equipment is needed for the programming process.
Uses fusesinstead of diodes. Fuses that need to be removed are vaporized during theprogramming process using a high voltage pulse (10 30 V).
CAN NOT BE ERASED.
EPROM
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EPROM
Erasable programmable read only memory
Uses floating-gate MOS transistors with insulatingmaterial that changes behavior when exposed to ultravioletlight.
Programmed electrically and erased optically. Erasing can be repeated a relatively large but limited
number of times (~100,000 times).
Erasing time ~20 minutes.
Electrically read and written. Before writing, ALLcells must be erasedby exposure
to ultraviolet light.
Non volatile. More expensivethan PROM.
EEPROM
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EEPROM
Electrical erasable read only memory
EEPROM or E2PROM Erasable electrical address by addressUses the same floating-gate transistors, except that the insulating
material is much thinner.
Its operation can be inverted using voltage.
Can be written to any time withouterasing the previous contents.
Only the bytes addressed are modified. Write takes a relatively long time(~100sec/byte). Can be erased only about 10,000 times.
Non volatile. Updatable in place. More expensive and less dense than EPROM.
Flash Memory
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Flash Memory
Called flash due to the speed of re-programming.
Uses electrical erasuretechnology. An entire chip can be erased in 1-2 sec. Possible to erase only blocks of data.
Does not provide byte level erasure. Uses one transistor per bit.
Very high density.
Cost is between EPROM and EEPROM. Non Volatile.
Increasing the capacity of the memory
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Increasing the capacity of the memory
Procedure: Find the capacity of the memory that can be used by the
microprocessor Find the capacity and the characteristics of the available memories Put these chips of memories in a table (ascending way) Find the range of addresses for each chip (beginning address and
final address)
Find the expression of CS Connect with the microprocessor
Example:
Connect the 4 chips of RAM: 8K bytes , 8K bytes, 16 K bytes, 32 Kbytes with the microprocessor 6800 (16 address bits).