Chap10 Phase Locked Loops

8/8/2019 Chap10 Phase Locked Loops

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Chapter X. Phase-Locked Loops (PLL)

Figure 10-1. Phase-locked loop applications.


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The Phase Detector

A simple analog phase detector is shown in Figure 10-2a. Consider the phase

detector as a simple switch, as illustrated in Figure 10-2b. The signal with frequency

fo simply opens and closes the (diode) switch. If 0ffi , then the circuit behavior is

that of a mixer producing the sum and difference frequencies. The capacitors shown

are chosen to bypassfi,fo, andfi +fo, and therefore only the beat (fi -fo) signal is seen

at vd. After the loop is locked,fo will be exactly equal tofi .

A phase difference between the two input signals results in a dc voltage Vd,

which is proportional to the phase difference, e = i - o .

Figure 10-2. (a) Analog phase detector. (b) Simpified model.

A mixer performs the mathematical function of multiplication. Thus for

sinusoidal inputs,

( ) ( )

( ) ( )[ ] ( ) ( )[ ]0000

00

sinsin

cos2sin

++++++=

++=

tAtA

tAv

iiii

iid


3/26

When phase-locked, o = i, the second harmonic term, Asin[2 ot + o

+ i], is filtered out, leaving

Vd =Asin( i - o) (10-1)

This voltage is directly proportional to the input signal amplitude and the phase error

e if the signal amplitude is held constant. Indeed, for small e, this transfer

function is linear as seen in Figure 10-3.

Figure 10-3. Analog phase detector characteristic-output voltage

versus input phase difference.

Figure 10-4. Phase detector waveforms.

Figure 10-4 helps to show the results graphically as oscilloscope

measurements. When the signals are out of phase by 90o as in part (a), a zero dc

output results; if the phase is slightly advanced as in part phase as in part (b), a small

negative dc output is produced; and when the signals are exactly in phase as in part

(c), the result is a dc output proportional to the fi signal level-exactly the kind of

signal that is needed for a lock indication in telephone touchtone decoders or AGC in

coherent receivers.


4/26

Phase Detector Gain

The PD characteristic is a continuous sinusoid repeating every 2 radians.

Also, during the tracking mode, operation is limited to the portion of the curve

between + /2 where | e| < /2. For sinusoidal inputs it is clear from Figure 10-6

that the slope of the phase detector characteristic curve,Vd =Asin e (10-2)

is not constant. In fact, it rises with a maximum slope at e = 0, and levels off to a

slope of zero (no gain) at e = /2 radians.

The peak voltage A is the volts-per-radian gain of this phase detector

because the tangents to the peak and the PD curve at e = 0 intersect at one radian,

as seen in Figure 10-6. Therefore the gain of the analog phase detector is

=radian

voltsAk (10-3)

Figure 10-6. Sinusoidal characteristic of analog phase detector.

If the input signals are both square-waves, the phase detector characteristic

will be linear, as illustrated in Figure 10-7. The gain of this circuit is constant over the

range of input e = + /2 and is given by k = Vd/ e = A/( /2). That is,

=radian

volts2

Ak (10-4)


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Figure 10-7. Phase comparator characteristic for square-wave

inputs.

Figure 10-8 Integrated circuit balanced detector.

Figure 10-8 is typical of balanced integrated circuit implementations. This

circuit is also used as a balanced AM modulator for producing double-sideband /

suppressed-carrier signals and consists of differential amplifiers. The oscillator input

polarity determines which differential pair conducts, while the signal input

determines whether 1CR

or 2CR receives the current. The output voltage will be thedifference between 11 CRi and 22 CRi .


6/26

Digital Phase (Timing) Comparators

Digital phase detectors can be realized using an exclusive-OR (Figure 10-9)

or an edge-trggered set-reset flip-flop (RS-FF) circuit. The exclusive-OR output Y is

low when both inputs are high or low; otherwise Y is high, indicating or. The

output is smoothed (integrated) to produce Vd. The exclusive-OR requires

symmetrical squarewave inputs, which may become a system problem, whereas the

edge-triggered RS-FF works well with pulses.

Figure 10-9. Digital implementation of phase detector using an

exclusive-OR gate.

As illustrated for the circuit of Figure 10-10, the RS-FF phase detector canproduce a linear PLL over a full e range of 2 rad, which is twice that for the other

phase detectors. The problem with using digital phase detectors in sensitive

communication receiver applications is in the difficulty of filtering the sharp impulses

and their harmonics to prevent radio-frequency interference (RFI).

Figure 10-10. Digital implementation of phase detector using a set-

reset flip-flop.


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Amplifiers

Figure 10-11. Operational amplifiers increase PLL loop gain.

The second loop component is an amplifier commonly referred to as the dc

amp. Its function sis to increase the loop gain by amplifying the phase detector output

voltage. Figure 10-11 shows three voltage amplifiers and their gain parameter

VA Ak = (volts out/volts in). The bandwidth of the dc amp must be very high

compared to the loop bandwidth or loop instability will result-even to the point of

oscillation due to excessive phase shift around the loop, which would produce

positive (regenerative) feedback.


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Voltage-Controlled Oscillator (VCO)

Figure 10-12. Tuning diode control of free-running multivbrator.

The frequency of the free-running multi-vibrator circuit of Figure 10-12 is

controlled by the variable reactance of D1 and D2. In IC implementations, D1 and D2

are realized by reverse-biased collector junctions. It should be noted that the control

voltage must not exceed VE + 0.5V + ve, where ve is the positive peak of the oscillator

signal acrossRE and 0.5V causes forward bias of the silicon diodes. The input-output

characteristic for the VCO is shown in Figure 10-13.

Figure 10-13. VCO characteristic.


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BASIC LOOP BEHAVIOR

Locking the loop

Start with switch 1S open (Figure 10-14) and a signal generator with

frequency fi connected to the input. With fi not equal to the free-running frequency

(fFR), the phase detector will produce the sum and defference frequencies. The loop

(low-pass) filter filters out the sum frequency (fi +fFR),fi, andfFR, while the difference

(fi - fFR)-the beat between the signal generator and VCO-is allowed to pass through.

The beat is amplified and seen as 0V on an oscilloscope. As the generatir frequency is

varied to bring fi closer to fFR, the beat frequency gets lower and lower. This is

illustrated in Figure 10-15.

Figure 10-14. PLL block diagram.

Figure 10-15. Beat-frequency output at Vo with loop open. The

input generator frequency is being varied fromfi fFR.


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Acquisition

In Figure 10-14, with the VCO input grounded and Vo = 0, measurements will

show that fi = fFR. However, if FRi ff , then thebeat is observed at Vo. When the

switch is closed, the beat-frequency signal at Vowill cause the VCO frequency fo to

change. If the voltage is large enough (high loop gain) and the filter bandwidth wide

enough, then the VCO will be deviated from fFR and lock at the instant that fo = fi .

The amount by which the VCO frequency must be changed is f=fi -fFR. The time

required for the loop to lock depends on the type of loop and loop dynamics. For the

simplest PLL with no loop filter, this acquisition time is on the order of 1/kv seconds.

Also, the range offiover which the loop will lock, the lock range, is equal to the

hold-in range for the simple PLL.

Locked Loop: The Tracking Mode

When the loop is locked we know that fo = fi. Only a phase difference

between the signal and the VCO can exist. This phase difference e = i - o is

called the static (dc) phase error. e is the input to the phase detector when the loop

is locked and is required in order for the phase detector to produce a dc output

voltage Vd which, when amplified by the dc amplifier, will produce exactly enough Vo

to keep the VCO frequency deviated by f. Iffi increases, then fincreases and e

must increase in order to provide for more Vo to keep the VCO tracking fi. The

definition of locked is that fi = fo and the loop will track any change in fi. Any

subsequent shift of i or o will be tracked-out so that only e remains.


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Hold-In Range

The range of frequencies forfi over which the loop can maintain lock is

called hold-in range. Assuming that the amplifier does not saturate and the VCO has a

wide frequency range, the phase detector characteristic limits the hold-in range. It

should be clear from the phase detector characteristics (Figures 10-6 and 10-7) that,

as the static phase error increases due to increasingfi, a limit forVd is reached beyond

which the phase detector cannot supply more voltage for VCO correction. The phase

detector simply cannot produce more than A volts. The total range ofVd is A = 2A,

so that the total range of e is radians. From Equation 10-7, the minimum to

maximum input frequency range,fi(max) -fi(min) = fH, will be

fH = kL

or

fH = kv / 2 (10-9)

The edge-triggered R-S flipflop phase comparator of Figure 10-9 can provide twice

this, fH = kv.


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Loop Gain and Static Phase Error

The locked PLL is seen in Figure 10-16. The phase comparator develops an

output voltage Vd in response to a phase difference between the reference input and

the VCO. The transfer gain k has units of volts/radian of phase difference. The

amplifier shown is wideband with a voltage gain of kA volts/volt (dimensionless).

Thus, Vo= kAVd.

Figure 10-16. PLL in tracking mode (locked).

The VCO free-running frequency isfFR. The VCO frequencyfo will change in

response to an input voltage change. The transfer gain ko has units of kHz/V. The loop

gain for this system is simply the gain of each block multiplied around the loop, thus

kL = k.

kA.

ko (10-6)

The units ofkL are (V/rad).(V/V).(kHz/V) = kHz/rad.

Assume that a signal with frequencyfi is an input to the phase detector, and

the loop is locked. If the frequency difference before lock was f= fi -fER, then a

voltage Vo = f/ ko is required to keep the VCO frequency equal to fi. So the phase

comparator must produce Vd= Vo/kA = f/ kokA, and the static phase error e = i

- o must be e = Vd/k . Combining gives e = f/kokAk = f/kL. This is a

fundamental equation for the PLL in phase lock;

e = f/ kL. (10-7)

In many computations the loop gain must be in units of radians/second rather

than in kHz/radian. The conversion is made using 2 radians/cycle. Hence, loop

gain is also given by

kv = 2 k kAko (10-8)

in unit of sec-1 or radians/second.


13/26

EXAMPLE:Figure 10-17 provides enough information to analyze the static behavior of a

phase-locked loop.

1. Determine kA for the op-amp.

2. Calculate the loop gain in units of sec-1 and in dB (at = 1 rad/s).

3. With S1 open as shown, what is observed at Vo with an oscilloscope?

4. When the loop is closed and phase-locked, determine

(a) the VCO output frequency,

(b) the static phase error at the phase comparator output, and

(c) Vo (is this rms, pk-pk, or what?).

5. Determine the hold-in range fH.

6. DetermineA, the maximum value ofVd.

Figure 10-17. Example PLL.

Solution:

1. =+= 1/ 1RRk fA 4 k/1k + 1 = 5.

2. 1.00 == kkkk AL V/rad x 5 x (-30 kHz/V) = -15x103(Hz/rad). Then, kv = 15x103

cycles/s-rad x (2 rad/cycle) = 94.3 k sec-1, and kv(dB) = 20 log kv =

20log(94.3x103) = 99.5dB at 1 rad/s.

3. Vo will be a sinusoidally varying voltage with a frequency of |fi fFR| = 10 kHz.

This assumes that a very small capacitor internal to the phase comparator filters

outfo,fiandfo +fi.


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4. (a). When the loop is locked,fo =fi= 100 kHz by definition of locked, and only a

phase difference can exist between the input signal and VCO. This phase

difference e is the loop-error signal (static phase error) which results in Vd at the

detector output and, when amplified by kA, provides enough voltage Vo to make the

VCO frequency be exactly equal tofi.

(b). The free-running frequency of the VCO is 110 kHz. In order for the VCO to

equal 100 kHz, the VCO input voltage must be Vo = (100 kHz -110 kHz)/ko = 10

kHz/(-30 kHz/V) = 0.33Vdc. Then, because kA = 5, Vd must be Vd = 0.33V/5 =

0.0667V. Finally e = Vd/k = 0.0667V/0.1V/rad = 0.667 rad. Once again, we

have derived the basic relationship, e = f/kL = (fi -fER)/kL = -10 kHz/(-15x103

Hz/rad) = 0.667 rad.

(c). The input to the phase detector (loop-locked) was determined from e =

f/kL = 0.667 rad. Since Vd = k e, we have Vd = 0.1 V/rad x 0.667 rad =

0.0667Vdc. Now, we are assuming Zin of the op-amp is much larger than R of the

loop filter, so there is no voltage drop across R. The input to the op-amp is

0.0667Vdc, so that Vo= kAVd = 5 0.0667Vdc = 0.33Vdc. This is enough to keep the

VCO at 100 kHz when in fact its rest frequency is 110 kHz.

5. The question is, when the loop is locked, how much can fi change in frequency

before the loop just cannot provide enough Vo to keep the VCO atfo =fi?Assuming

that the VCO and dc amplifier don't saturate, we look at the phase detector

characteristic. Clearly Vd can increase with e until Vd ---> Vmax = A, at which point

e = /2. Beyond this, Vd decreases for increasing static phase error, and the

phase detector simply cannot provide more output voltage to continue increasingfo,

and the loop breaks lock. The total hold-in range is +2 , or rad. The frequency

difference between these break-lock points will be fH = e(max) x kL = x 15

kHz/rad = 47.1 kHz.

6. At the frequency where e = /2, we have Vd(max) = A. Therefore Vd = k e =

0.1 V/rad /2 rad = 0. 157Vdc.


15/26

FM and FSK APPLICATIONS of PLLs

When a PLL has locked to an input signal, the VCO will follow slow changes

in the input signal frequency fi. Suppose fi increases by an amount fi. In order for

the loop to remain locked (fo -fi), the VCO voltage must increase by Vo = fi/ko.

This voltage change is produced by the amplified change in Vd, which is produced by

an increased phase difference, e = 2 fi/kv.

As a specific example, suppose that an FM signal with carrier frequency fi is

modulated to an index ofmf= 4 by a 1-kHz sinusoid. The carrier frequency will be

deviated above and belowfi by an amount fi = mffm = 4 1 kHz = 4 kHz pk. If this

FM signal is the input to a PLL with a VCO gain of ko = 10 kHz/V and loop

bandwidth 1 kHz, then the VCO input voltage Vo will be a 1-kHz sinusoid with a

peak amplitude of Vo = fi/ko = (4 kHz pk)/(10 kHz/V) = 400 mV pk.

NOISE MARGIN

To get a quantitative idea of the loop noise margin, consider the results of

Example 10-3 as seen in Figure 10-23b. The output voltage Vo is 2V for a transmitted

MARK. How high can Vo rise on a noise transient caused by a deviation of theMARK frequency or circuit variations ofVo before the loop breaks lock? The static

phase error whenfi =fM = 2 kHz is e = f/kL = (2 kHz - 3.5 kHz)/(1.19 kHz/rad) =

1.26 rad. However, for typical phase detector's, the loop will break lock if e exceeds

/2 = 1.57 rad. Consequently loop transients that would cause e to increase by

0.31 rad will result in a loss of lock. In terms of voltages, Vd(max) = k e(max) =

(0.3184 V/rad) (1.57 rad) = 0.5V and Vo(max) = 5 0.5 = 2.5V. Since Vo(MARK) =

2V and we-have calculated Vo(max) = 2.5V, we see that the noise margin forVo will

be Vo(NM) = 0.5 Vpk. This can result from noise in the PLL itself, from the noise

input signal-amplitude if no limiter precedes the PLL or from an input signal

frequency deviation (due to noise) of fi(NM) = ko x Vo(NM) = (0.75 kHz/v) x

(0.5Vpk) = 375 Hz peak noise.


16/26

EXAMPLE:

A PLL with ko= -0.75 kHz/V,fFR = 3.5 kHz, k = 0.3184 V/rad, and kA = 5 is

used as an FSK demodulator. The input signal has fS = 4 kHz, fM =2 kHz, and the

modulation is shown in Figure 10-23a. As seen, the baud rate is 1333 bits/s and the

data is 1 0 0 Sketch accurately the PLL output Vo(t).

Solution:

Forfi =fM = 2 kHz, Vo = fo/ko = (fifFR)/ko= (2 kHz 3.5 kHz)/(-0.75 kHz/V)

= +2V. Forfi = fS = 4 kHz, Vo = (4 kHz 3.5 kHz)/(-0.75 kHz/V) = -0.67V. The loop

time constant is =1/kv = 1/(0.75 kHz/V)(0.3184 V/rad)(5)(2 rad/cycle) = 1/7502

= 0. 133 ms. It takes 0.133 ms forVo to rise from -0.67V to 63% of the total voltage

range 2V - (-0.67V) = 2.67V. 63% of 2.67V is 1.69V, so at time , Vo = 1.69V -

0.67V = 1.02V (see the plot ofVo in Figure 10-23b).

Figure 10-23. FSK input (a) and demodulated output (b) of PLL.


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Figure 8.3-6. PLL frequency multiplier.

Suppose a double-conversion SSB receiver needs fixed LO frequencies at

100 kHz (for synchronous detection) and 1.6 MHz (for the second mixer), and an

adjustable LO that covers 9.90 -- 9.99 MHz in steps of 0.01 MHz (for RF tuning).

The custom-tailored synthesizer in Fig. 8.3-7 provides all the required frequencies by

dividing down, multiplying up, and mixing with the output of a 10-MHz oscillator.

Figure 8.3-7. Frequency synthesizer with fixed and adjustable output.


18/26

Linearized PLL Models and FM Detection

Suppose that a PLL has been tuned to lock with the input frequencyfc, so

f= 0. Suppose further that the PLL has sufficient loop gain to track the

input phase (t) within a small error )(t , so )()()()(sin tttt v = . These

suppositions constitute the basis for the linearized PLL model in Fig. 8.3-8a,where the LPF has been represented by its impulse response h(t).

Since well now focus on the phase variations, we view (t) as the

input signal which is compared with the feedback signal

=t

vv dyKt )(2)(

to produce the output y(t). We emphasize that viewpoint by redrawing the linearized

model as a negative feedback system, Fig. 8.3-8b. Note that the VCO becomes an

integrator with gain 2 Kv while phase comparison becomes subtraction.

Figure 8.3-8. Linearized PLL modes. (a) Time domain;

(b) phase; (c) frequency domain.


19/26

Direct Frequency Synthesizers

Figure 10-37 shows a high-stability, 64-kHz master reference oscillator

followed (horizontally) by a comb generator, which is a circuit used to produce a

pulse rich in harmonics of the 64-kHz input signal. A harmonic-selector filter

controlled by tuning logic is tuned to the desired harmonic and rejects all other

spurious outputs. If the synthesizer consisted only of this group of blocks, the

resolution would be 64 kHz because the output can be switched only to the various

harmonics of the 64-kHz master reference.

In order to improve the resolution and thereby achieve a finer separation

between the possible Output frequencies, a divide-by-16 circuit is used with a comb

generator and selector filter to produce 4-kHz frequency steps. The selected

frequencies from the upper and lower harmonic-select filters are mixed to produce

sum and difference frequencies, and the output (switchable) filter passes the desired

output frequency. The resolution, or smallest possible discrete frequency step, is now

seen to be 4 kHz. For instance, withN1 = 2, N2 = 2, and the output filter passing, the

mixer sum, thenfo = 128 kHz + 8 kHz = 136 kHz. The next higher output frequency

would be 140kHz.

Figure 10-37. Direct synthesizer.


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A multicrystal, direct-synthesis scheme for producing the transmit carrier and

two receiver local oscillators for a 23-channel citizens band transceiver is shown in

Figure 10-38. This synthesizer is a 6-4-4 crystals/oscillator scheme (a 6-4-2 scheme is

also used) and, when tuned to emergency CB channel 9 (27.065 MHz carrier

frequency), crystals 3, 7, and 11 are used. With the receiver oscillator off, crystals 3

and 11 produce the transmit carrier: 37.700 - 10.635 = 27.065 MHz. With the receiver

oscillator on and the transmit oscillator off, the first and second local oscillators for

this double-conversion receiver are produced by the synthesis and receiver oscillators

as follows: 37.700 MHz from the synthesis oscillator with Xtal-3 is the 1st-LO

frequency. Thus, the 1st-IF frequency is 37.700 - 27.065 MHz = 10.635 MHz, so that

FM receiver IF transformers can be used. The receiver oscillator with Xtal-7(10.180

MHz) is the 2nd-LO, and the 2nd-IF frequency is 10.635 MHz - 10.180 MHz = 455

kHz, so that AM receiver IF transformers can be used.

Figure 10-38. Frequency synthesis (6-4-4) for 23-channel CB

transceiver.


21/26

Phase-Locked Synthesizers

The most frequency used technique for frequency synthesis is the indirect

method utilizing a voltage-controlled oscillator in a programmable PLL. The simplest

system is the one-loop synthesizer of Figure 10-39, consisting of a digitally

programmable divide-by-N circuit used to divide the VCO Output frequency for

comparison with a stable reference source.

Figure 10-39. Phase-locked frequency synthesizer.

The digitally programmable frequency-divider output,fo/N, is determined by

the value ofN selected by the user and is compared to the reference signal in the

phase detector (PD). When the loop is locked for a specific value ofN, thenfo/N=fref

by definition of phase-locked; therefore the synthesizer output is

fo =Nfref (10-26)

The divider can be a simple integer divider such as the 74192 programmable

up-down counter, or noninteger divider systems such as the fractional-N method

(producing fo = (N+1/M)fref) and the two-modulus prescaler circuit of Figure 10-44,

the MC12012, for example, using a technique called pulse swallowing. For our

purposes, only integer dividers are considered.


22/26

The loop gain for the simple PLL synthesizer of Figure 10-39 is

N

kkk

o

L

= (10-27)

it is important to realize that the frequency-divider circuit reduces the loop gain so

that the other loop components need to have relatively higher gain than the

conventional PLL. A more troublesome design problem, however, is that, as N

changes, so does the loop gain. There are linearizer circuit to ameliorate this problem.

Figure 10-40 Microprocessor-controlled LO synthesizer for TV.

Figure 10-40 shows the use of a very high frequency prescaler in a one-loop

synthesizer used for push-button TV channel selection. The VHF local oscillator

(LO) frequency is greater than 100 MHz, so high frequency emitter-coupled logic

(ECL) dividers are used to prescale the VHF signal below 1 MHz, where low-cost

TTL or CMOS technology can be used. The prescaler will reduce the resolution by an

amount equal to the prescale division rationP. Hence,

Resolution =Pfref (10-28)

with a prescaler.


23/26

EXAMPLE:

The microprocessor-controlled VHF LO synthesizer of Figure 10-40 has a

phase comparator with k = 1 V/rad and an output impedance of 3.5 k. Determinethe following:

1.fref.2. N for the TV to receive channel 5 (fLO= 123.000 MHz).3. The synthesizer frequency resolution.

4. Loop gain and value of capacitor to compensate the loop to = 0.5 and havethe VCO frequency within 10 % of its specified value in less than 10 msafter selection of channel 5. (Assume that the maximum frequency step at the

phase detector is within the loop bandwidth.)

5. What value must the VCO sensitivity be?

Solution:

1. fref = fXO/3580=3583.5 kHz/3580 = 1.00098 kHz.

2. refNf 2560 = , thereforeN= 123.000 MHz/[(256)(1.00098 kHz)] = 480.

3. With the prescaler, the resolution will be Pfref = 256fref = 256.25 kHz. To prove

this, change the programmable divider to N+1 = 481, and compare the new fo to

the old.

fo(N+ 1) =1.00098 kHz 256 481 =123,256.67 kHz

fo(N) = 1.00098 kHz 256 480 = 123,000.42 kHz

Resolution: fo(N+ 1) Nfo = 256.25 kHz.

4. With the assumption stated, the loop will lock up unaided (without frequency

sweep circuitry); hence, we use the universal overshoot and ringing curves of

Figure 10-27. Vo must stay within relative values 0.90 and 1.1 (+10 %) on the

= 0.5 curve. This is satisfied by nt = 4.6. With t = ts = 10 ms, we need the loop

to have n = 4.6/10 ms = 460 rad/s. Since = 0.5 vc k/ , then c = kvfor =

0.5. Also vcn k = , so that n = c = kv = 460 rad/s.

A capacitor is placed across the phase detector output (Ro = 3.5 k) to form

the lag-compensation network. C= 1/ cRo = 1/(460 3500) = 0.62 F.

5. kv = 2 k ko/N= 460 rad/s. Therefore, ko is required to be ko =Nkv/2 k = (256 x

480) x (460) / 2(1V/rad) = 9 MHz/V. This figure is not unrealistic for 123 MHz

VCO.


24/26

Translation Loops and Multiple-Loop Synthesizers

One technique used to reduce a high-frequency VCO output to reasonable

frequencies without a prescaler, and to provide a frequency offset, is shown with in

the dashed area of Figure 10-41. Figure 10-41 is the receiver block diagram for a PLL

synthesized 40-channel citizen band transceiver with delta tuning for fine-frequency

adjustments. The mixer and 35.42-MHz crystal oscillator translate the VCO

frequency range from 37.66-38.10 MHz down to 2.24-2.68 MHz for input to the

programmable divider. Notice that the reference oscillator also provides the second

LO for the double-conversion receiver.

Figure 10-41. PLL frequency synthesizer for a 40-channel CB

transceiver.


25/26

Multiple-loop synthesizers combine all of the techniques discussed thus far.

The addition of more loops increases the resolution and frequency coverage; the

individual loops also act as tracking filters to reduce unwanted mixer products and

spurious output components. Ideally, double-balanced mixers are used throughout.

Figure 10-42 illustrates the basic multiple-loop synthesizer for n loops. If the mixer

outputs are filtered to pass the difference frequency and the output frequency of each

VCO is lower for higher n, the synthesizer output frequency can shown to be

+++=

)( 322

2

1

n

n

refoMMM

N

M

NNff

(10-29)

and

Resolution =)( 32 n

ref

MMM

f

(10-30)

Figure 10-42. An n-loop, multiloop synthesizer.


26/26

A variation of the multiple-loop synthesizer shown in Figure 10-43 isused in

a Cubic Communications HF-1030 AM and single-sideband receiver. The figure is

incomplete but it is clear that the resolution is 10 Hz, and 3 million discrete local

oscillator frequencies can be synthesized. The oven temperature control of the

crystal-reference oscillator for the portable HF-1030 allows the unit to maintain

frequency stability specifications of 1 ppm/month and less than 1 Hz/C for

environmental temperature changes.

Figure 10-43. Multiloop main synthesizer for HF-1030

communications receiver.

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Chap10 Phase Locked Loops

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