Chap2 Mos Transistor Theory

7/25/2019 Chap2 Mos Transistor Theory

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Introduction to

CMOS VLSIDesign

Lecture 3:CMOS Transistor Theory

David Harris

Harvey Mudd College

Spring 2004


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CMOS VLSI Design3: CMOS Transistor Theory Slide 2

Outline

Introduction MOS Capacitor nMOS I-V Characteristics

pMOS I-V Characteristics Gate and Diusion Capacitance !ass "ransistors #C Delay Models


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Introduction

So ar$ %e have treated transistors as ideal s%itches &n O' transistor passes a inite a(ount o current

) Depends on ter(inal voltages

) Derive current-voltage *I-V+ relationships "ransistor gate$ source$ drain all have capacitance

) I , C *Vt+ -. t , *CI+ V) Capacitance and current deter(ine speed

&lso e/plore %hat a degraded level1 really (eans


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MOS Capacitor

Gate and ody or( MOS capacitor Operating (odes

)&ccu(ulation

) Depletion) Inversion

polysilicon gate

*a+

silicon dio/ide insulator

p-type ody3-

Vg4 0

*+

3-

0 4 Vg4 Vtdepletion region

*c+

3-

Vg. Vt

depletion region

inversion region


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Terminal Voltages

Mode o operation depends on Vg$ Vd$ Vs) Vgs, Vg) Vs) Vgd, Vg) Vd) Vds, Vd) Vs, Vgs- Vgd

Source and drain are sy((etric diusion ter(inals) 5y convention$ source is ter(inal at lo%er voltage

) Hence Vds0 nMOS ody is grounded6 7irst assu(e source is 0 too6

"hree regions o operation) Cutoff

) Linear

) Saturation

Vg

Vs Vd

VgdVgs

Vds3-

3

-

3

-


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nMOS Cutoff

'o channel

Ids, 0

3-

Vgs, 0

n3 n3

3-

Vgd

p-type ody

g

s d


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nMOS Linear

Channel or(s Current lo%s ro( d to s

) e-ro( s to d

Idsincreases %ith Vds Si(ilar to linear resistor

3-

Vgs. Vt

n3 n3

3-

Vgd, Vgs

3

-

Vgs. Vt

n3 n3

3

-

Vgs. Vgd. Vt

Vds, 0

0 4 Vds4 Vgs-Vt

p-type ody

p-type ody

g

s d

g

s dIds


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nMOS Saturation

Channel pinches o

Idsindependent o Vds 8e say current saturates

Si(ilar to current source

3-

Vgs. Vt

n3 n3

3-

Vgd4 Vt

Vds. Vgs-Vtp-type ody

g

s d Ids


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CMOS VLSI Design3: CMOS Transistor Theory Slide

I-V Characteristics

In 9inear region$ Idsdepends on

) Ho% (uch charge is in the channel:

) Ho% ast is the charge (oving:


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CMOS VLSI Design3: CMOS Transistor Theory Slide !"

Channel Charge

MOS structure loo;s li;e parallel plate capacitor%hile operating in inversion

) Gate ) o/ide ) channel

+

polysilicongate


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CMOS VLSI Design3: CMOS Transistor Theory Slide !!

Channel Charge



+

polysilicon

gate


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CMOS VLSI Design3: CMOS Transistor Theory Slide !2

Channel Charge



+

polysilicon

gate

Co/, o/ to/


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Channel Charge



+

polysilicon

gate

Co/, o/ to/o/ is per(ittivity

Vgc= (Vgs + Vgd)/2

Vgc= Vgs Vds/2

&vg6 gate to channelpotential


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Carrier elocity

Charge is carried y e- Carrier velocity vproportional to lateral ?-ield

et%een source and drain

v,


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Carrier elocity



v, ? called (oility ? ,


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Carrier elocity



v, ? called (oility ? , Vds9

"i(e or carrier to cross channel@

) t,


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Carrier elocity



v, ? called (oility ? , Vds9

"i(e or carrier to cross channel@

) t, 9 v


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nMOS Linear I-V

'o% %e ;no%) Ho% (uch charge


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CMOS VLSI Design3: CMOS Transistor Theory Slide !

nMOS Linear I-V



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CMOS VLSI Design3: CMOS Transistor Theory Slide 2"

nMOS Linear I-V



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CMOS VLSI Design3: CMOS Transistor Theory Slide 2!

nMOS Saturation I-V

I Vgd Vt$ channel pinches o near drain

) 8hen Vds. Vdsat, Vgs) Vt 'o% drain voltage no longer increases current

dsI =


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nMOS Saturation I-V



2dsat

ds gs t dsat

VI V V V =


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nMOS Saturation I-V



( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

=

= Substitute

Vdsat= Vgs Vtinto equation.


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nMOS I-V Summary

( ) 2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V


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!"ample

8e %ill e using a 06B ( process or your proect) 7ro( &MI Se(iconductor

) to/, A00

) , =E0 c(2

VFs) Vt, 06 V

!lot Idsvs6 Vds) Vgs, 0$ A$ 2$ =$ 4$ E

) se 89 , 42

( )1

2

!

".# !.!$ 10"$0 120 /

100 10ox

W W WC A V

L L L

= = =

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

Ids

*(&+

Vgs, E

Vgs, 4

Vgs, =

Vgs, 2

Vgs, A


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pMOS I-V

&ll dopings and voltages are inverted or pMOS Moility pis deter(ined y holes

) "ypically 2-=/ lo%er than that o electrons n

) A20 c(2

VFs in &MI 06B ( process "hus pMOS (ust e %ider to provide sa(e current

) In this class$ assu(e n p, 2

) FFF plot I-V here


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Capacitance

&ny t%o conductors separated y an insulator havecapacitance

Gate to channel capacitor is very i(portant

) Creates channel charge necessary or operation Source and drain have capacitance to ody

)&cross reverse-iased diodes

) Called diusion capacitance ecause it is

associated %ith sourcedrain diusion


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#ate Capacitance

&ppro/i(ate channel as connected to source Cgs, o/89to/, Co/89 , Cper(icron8 Cper(icronis typically aout 2 7(

n3 n3

p-type ody

8

9to/

SiO2gate o/ide

*good insulator$ o/, =6>0+

polysilicon

gate


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Diffusion Capacitance

Cs$ Cd ndesirale$ called parasiticcapacitance Capacitance depends on area and peri(eter

) se s(all diusion nodes) Co(parale to Cg

or contacted di

) Cgor uncontacted

) Varies %ith process


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CMOS VLSI Design3: CMOS Transistor Theory Slide 3"

$ass Transistors

8e have assu(ed source is grounded 8hat i source . 0:

) e6g6 pass transistor passing VDDV

DD

VDD


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CMOS VLSI Design3: CMOS Transistor Theory Slide 3!

$ass Transistors

8e have assu(ed source is grounded 8hat i source . 0:

) e6g6 pass transistor passing VDD

Vg, VDD) I Vs. VDD-Vt$ Vgs Vt) Hence transistor %ould turn itsel o

nMOS pass transistors pull no higher than VDD-Vtn

) Called a degraded A1)&pproach degraded value slo%ly *lo% Ids+

pMOS pass transistors pull no lo%er than Vtp

VDD

VDD


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$ass Transistor C%ts

VDD

VDD

VSS

VDD

VDD

VDD

VDD

VDD

VDD


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$ass Transistor C%ts

VDD

VDD V

s

, VDD

-Vtn

VSS

Vs, JV

tpJ

VDD

VDD-Vtn VDD-VtnV

DD-V

tn

VDD

VDD

VDD

VDD

VDD

VDD

-Vtn

VDD-2Vtn


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!ffectie &esistance

Shoc;ley (odels have li(ited value) 'ot accurate enough or (odern transistors

) "oo co(plicated or (uch hand analysis Si(pliication@ treat transistor as resistor

) #eplace Ids*Vds$ Vgs+ %ith eective resistance #

K Ids, Vds#

) # averaged across s%itching o digital gate

"oo inaccurate to predict current at any given ti(e) 5ut good enough to predict #C delay


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&C Delay Model

se eLuivalent circuits or MOS transistors) Ideal s%itch 3 capacitance and O' resistance

) nit nMOS has resistance #$ capacitance C

) nit pMOS has resistance 2#$ capacitance C

Capacitance proportional to %idth #esistance inversely proportional to %idth

;g

s

d

g

s

d

;C;C

;C

#;

;g

s

d

g

s

d

;C

;C

;C

2#;


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&C Values

Capacitance) C , Cg, Cs, Cd, 2 7( o gate %idth) Values si(ilar across (any processes

#esistance) # B F( in 06Bu( process) I(proves %ith shorter channel lengths

nit transistors

) May reer to (ini(u( contacted device *42 +) Or (aye A ( %ide device) DoesnNt (atter as long as you are consistent


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Inerter Delay !stimate

?sti(ate the delay o a anout-o-A inverter

2

A&

2

A


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C

C#

2C

2C

#

2

A&

C

2C

2

A


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C

C#

2C

2C

#

2

A&

C

2C

C

2C

C

2C

#

2

A


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CMOS VLSI D i3 CMOS T i t Th Slid 4"



C

C#

2C

2C

#

2

A&

C

2C

C

2C

C

2C

#

2

A

d , B#C

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Chap2 Mos Transistor Theory

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