No Slide Title*
Chapter 4
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Connection of the memory to the CPU
MAR
MDR
Memory
k
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Organization of bit cells in a memory chip
From Figure 5.2 Page 296 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
Chapter 4 - The Memory System
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Organization of a 1Kx1 memory chip
From Figure 5.3 Page 297 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
Chapter 4 - The Memory System
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Semiconductor Memories
Nonvolatile memory
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ROM
PROM : Programmable Read Only Memory
Programmable by user only once
Flexible and convenient compared to ROM
Programmed by burning the fuse using high current pulse
Chapter 4 - The Memory System
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A simple 4-word ROM
From Figure 11-12 Page 298 of “Microprocessors: principles and applications”, Charles M.Gilmore, McGraw Hill pub.
Chapter 4 - The Memory System
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A simple 4-word ROM using MOS
From Figure 11-13 Page 299 of “Microprocessors: principles and applications”, Charles M.Gilmore, McGraw Hill pub.
Chapter 4 - The Memory System
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EEPROM
No requirement of physically removed from the circuit for reprogramming
Use special voltage level to erase data
Any cell contents can be delete selectively
Chapter 4 - The Memory System
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EPROM
Reprogrammable
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EPROM 2764, 27128, 27256
From Figure 11-15, Page 301 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.
Chapter 4 - The Memory System
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Flash Memory
Electrically erasable
Single cell can be read but can be written only an entire block of cells.
Prior to writing, the previous of the block are erased.
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SRAM cell
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DRAM cell
word line
bit line
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SRAM VS DRAM
DRAM
Need to be refreshed periodically
Chapter 4 - The Memory System
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DRAM: Multiplexed Row-Column addressing
From Figure 11-7, Page 291 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.
Chapter 4 - The Memory System
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Reducing Address pins of IC chip
RAS = Row Address Strobe
CAS = Column Address Strobe
DRAM: Multiplexed Row-Column addressing
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Static RAM
2Kx8
8Kx8
From Figure 11-5, Page 289 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.
Chapter 4 - The Memory System
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Dynamic RAM chip: Example
From Figure 11-6, Page 290 of “Microprocessor : Principle and Application”, Charles M. Gilmore, McGraw Hill pub.
Chapter 4 - The Memory System
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Memory Module
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FROM http://www.buycomputermemory.com/computer-memory-types-and-memory-technology.html
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Internal organization of a 2Mx8 DRAM
From Figure 5.7 Page 300 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
Chapter 4 - The Memory System
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SDRAM
Can be used with clock speed 100 and 133 MHz
Built in refresh circuitry
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Structure of Synchronous DRAM
From Figure 5.8 Page 302 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
Chapter 4 - The Memory System
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Burst read of length 4 in an SDRAM
From Figure 5.9 Page 303 of “Computer Organization”, Carl Hamacher, 5th edition, McGraw Hill pub.
Row
Col
D0
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Processor
Memory
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Is the North-bridge chip in typical PC
Activate/Deactivate signal RAS and CAS timing for DRAM
Interposed between Processor and Memory
Refresh DRAM if required
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From http://www.via.com.tw/en/p4-series/pt800.jsp
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From http://www.via.com.tw/en/p4-series/pt880.jsp
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Memory hierarchy
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4
Processor
From Figure 11-15, Page 301 of “Microprocessor : Principle and Application”, Charles M. Gilmore , McGraw Hill pub.
Vsupply
word line
bit line
From Figure 11-7, Page 291 of “Microprocessor : Principle and Application”, Charles M. Gilmore , McGraw Hill pub.
From Figure 11-5, Page 289 of “Microprocessor : Principle and Application”, Charles M. Gilmore , McGraw Hill pub.
From Figure 11-6, Page 290 of “Microprocessor : Principle and Application”, Charles M. Gilmore , McGraw Hill pub.
Memory
Memory
Controller
Row/Column
address
Address
data
Processor
Clock
R/W
CS
CAS
RAS
R/W
Request
Clock
Processor
Registers