back-gate

channel

isolation

buried oxide

channel

top-gate

Well doping

channel

Depletion layer

isolation

halo

CMOS Scaling Challenges

Table 2a High Performance Logic Technology Requirements2003 ITRS

Calendar Year

2003

2004

2005

2006

2007

2008

2010

2013

2016

2018

Technology Node (nm)

100

90

65

45

32

22

18

MPU Gate Length

45

37

32

28

25

18

13

9

7

Gate Dielectric Equivalent Oxide Thickness (EOT) (nm) [1]

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.50

0.45

Electrical Thickness Adjustment Factor (Gate Depletion and Quantum Effects) (nm) [2]

0.8

0.8

0.7

0.7

0.4

0.4

0.4

0.4

0.4

0.4

Electrical Equivalent Oxide Thickness in Inversion (nm) 4

2.1

2.0

1.8

1.7

1.3

1.2

1.1

1.0

0.9

0.9

Vdd (V) [4]

1.2

1.2

1.1

1.1

1.1

1.0

1.0

0.9

0.8

0.7

Bulk-Si Performance Trends Maintaining historical CMOS performance trend requires new semiconductor materials and structures by 2008-2010... Earlier if current bulk-Si data do not improve significantly.Best Case: Projected forwardMIT Antoniadis

Single Gate Non-classical CMOS

Device

Transport-enhanced Devices

Ultra-thin Body

Source/Drain Engineered Devices

Concept

Strained Si, Ge, SiGe, SiCGe or still other semiconductor; on bulk or SOI

Fully depleted SOI with body thinner than 10nm

Ultra-thin channel and localized ultra-thin BOX

Schottky source/drain

Non-overlapped SD extensions on bulk, SOI, or DG devices

Application/Driver

HP CMOS

HP, LOP, and LSTP CMOS

HP, LOP, and LSTP CMOS

HP CMOS

HP, LOP, and LSTP CMOS

Multiple Gate Non-classical CMOS

Device

Multiple Gate FET

N-Gate (N>2) FET

Double-gate FET

Concept

Tied gates (number of channels >2)

Tied gates,side-wall conduction

Tied gatesplanar conduction

Independently switched gates,planar conduction

Vertical conduction

Application/Driver

HP, LOP, and LSTP CMOS

HP, LOP, and LSTP CMOS

HP, LOP, and LSTP CMOS

LOP and LSTP CMOS

HP, LOP, and LSTP CMOS

Technology Enhancements for High PerformanceCalculations performed using MASTAR ST Microelectronics T. Skotnicki

Technology Enhancements for High PerformanceCalculations performed using MASTAR ST Microelectronics T. Skotnicki

Scope of Emerging Research DevicesBulk CMOSDouble-Gate CMOS

back-gate

channel

isolation

buried oxide

channel

top-gate

Well doping

channel

Depletion layer

isolation

halo

Emerging Research DevicesRequirements & Motivations for Beyond CMOSFundamental RequirementsEnergy restorative functional process (e.g. gain)Compatible with CMOSAt or above room temperature operationCompelling MotivationsFunctionally scaleable > 100x beyond CMOS limitHigh information processing rate and throughputMinimum energy per functional operationMinimum, scaleable cost per function

2003 ITRSEmerging Research DevicesMEMORYPhase Change MemoryFloating body DRAMNanofloating Gate MemorySingle Electron MemoryInsulator Resistance Change MemoryMolecular MemoryLOGICRapid Single Flux Quantum Devices1D structuresResonant Tunneling DevicesSingle Electron TransistorsMolecular devicesQuantum Cellular AutomataSpin Transistors

Emerging Research Memory Devices

Storage Mechanism

Present Day Baseline Technologies

Phase Change Memory*

Floating Body DRAM

Nano-floating Gate Memory**

Single/Few Electron Memories**

Insulator Resistance Change Memory**

Molecular Memories**

Device Types

DRAM

NOR Flash

OUM

1TDRAM

eDRAM

Engineered tunnel barrier or nanocrystal

SET

MIM oxides

Bi-stable switch

Molecular NEMS

Availability

2004

2004

~2006

~2006

~2006

>2007

~2010

>2010

Cell Elements

1T1C

1T

1T1R

1T

1T

1T

1T1R

1T1R

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Emerging Research Memory DevicesMemory elementFloating body DRAM Charge stored in body of PDSOI MOSFETNanofloating Gate Memory Flash with engineered tunnel barrier OR charge stored on silicon nano-crystalsSingle-electron memory Charge stored on a quantum dot channel of an Single Electron Transistor (SET)

CapacitorPhase-Change memory- R=f(crystalline - or amorphous - phase)Insulator resistance change Memory R=f(formation/dissolution of metal nanowire?)Molecular MemoryR=f(bias voltage)

Resistor

Floating Body Cell (FBC) of nFET on PD-SOI1 Write: Operation of the cell in saturation injects holes into the body.

0 Write: Forward-biasing of the pn junction ejects holes from the body.(T.Ohsawa et. al.,ISSCC02,p.152)

Medium-Term Emerging DevicesNano Floating Gate Memory

Nanofloating gate memory is evolution of conventional floating gate (FLASH) memory

Nanofloating gate memory (NFGM)NFGM includes several possible evolutions of conventional floating gate memory. Graded tunnel barrier Engineered shape of tunnel barrierNano-sized memory nodeMultiple silicon nanocrystal dotsThe multiple floating dots are separated and independent, and electrons are injected to the dots via different paths. The endurance problem can be much improved in multidot (nanocrystal) memory

The Graded (crested) Barrier ConceptEngineered tunnel barriers serve to increase the write/erase performance of memory cells with keeping long retention time typical for floating gate memories.

Uses a stack of insulating materials to create a special shape of barrier enabling effective Fowler-Nordheim tunneling into/from the storage node.

Nanocrystal MemorySmaller write timeSmaller number of electrons per bitLarger retention timePrevents discharge through a localized path in defective insulatorMinimizes edge effectsLow write voltageField enhancement at nanodotsMultibit-per-cell storageImproved enduranceWrite current density is uniformly distributed along the nanodotsWrite current per nanodot is self-limited by Coulomb blockade

Phase Change MemoryTyler Lowrey, Energy Conversion Devices, Inc., http://www.ovonic.comChanges in ResistanceI, mA

Molecular MemoryUsing individual molecules as building block of memory cellsData are stored by applying external voltage that cause the transition of the molecule into one of two possible phase states. Reading data is performed by measuring resistance changes in the molecular cellIt is possible to combine molecular components with existing technology e.g. DRAM and floating gate memorySource: M.Reed et al - Yale U and Rice U.

Factor 1 - - Individual Performance Potential for each Technology Evaluation Criterion

Factor 2 - - Individual Risk Assessment for each Technology Evaluation Criterion

Overall Performance and Risk Assessment for Technology Entries Overall Performance and Risk Assessment (OPRA) = Sum [(Performance Potential) x (Risk Assessment)] (Summed over the eight Evaluation Criteria for each Technology Entry)

Maximum Overall Performance and Risk Assessment (OPRA) = 72

Minimum Overall Performance and Risk Assessment (OPRA) = 8

Overall Performance and Risk Assessment for Technology Entries

Technology Performance and Risk EvaluationEmerging Research Memory DevicesPotential/Risk

Memory Device Technologies

Performance [A]

Architecture compatible [B]*

Stability and reliability[C]

CMOS compatible[D]**

Operate temp[E]***

Energy efficiency [F]

Sensitivity parameter)[G]

Scalability[H]

Floating Body DRAM

2.3/2.3

3.0/3.0

2.0/2.7

3.0/3.0

3.0/3.0

2.0/3.0

2.3/2.9

2.8/2.7

Phase Change Memory

2.6/2.9

2.2/3.0

2.3/2.2

2.2/3.0

3.0/3.0

1.8/2.7

2.1/2.1

2.7/2.2

Nano-floating Gate Memory

3.0/2.2

2.9/3.0

2.0/2.7

3.0/3.0

3.0/3.0

2.1/2.8

1.6/2.0

2.4/2.0

Insulator Resistance Change Memory

2.4/2.1

2.7/2.7

2.2/2.4

2.1/2.8

3.0/2.9

2.8/2.0

2.1/2.0

2.7/2.4

Molecular Memory

1.6/1.2

1.8/2.0

1.8/1.4

1.9/2.1

2.8/2.3

2.3/1.9

2.1/1.7

2.6/2.2

Single/Few Electron Memory

1.1/1.3

1.9/1.3

1.1/1.0

2.4/1.9

1.3/1.3

2.4/1.2

1.3/1.0

2.6/1.4

Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter

Device

FET

RSFQ

1D structures

Resonant Tunneling Devices

SET

Molecular

QCA

Spin transistor

Cell Size

100nm

0.3m

100nm

100nm

40nm

Not known

60nm

100nm

Density

(cm-2)

3E9

1E6

3E9

3E9

6E10

1E12

3E10

3E9

Switch Speed

700GHz

1.2THz

Not known

1THz

1GHz

Not known

30MHz

700GHz

Circuit Speed

30GHz

250800GHz

30GHz

30GHz

1GHz

1.41017

21018

>21018

>1.51017

1.31016

>11018

21018

Binary Throughput, GBit/ns/cm2

86

0.4

86

86

10

N/A

0.06

86

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Emerging Research Logic Devices Binary decision functionRapid Single Flux Quantum DevicesTunneling in superconducting structures1D structuresDrift electron transport in nanowires and nanotubesResonant Tunneling DevicesResonant tunneling in semiconductor heterostructuresSingle Electron TransistorsSingle electron tunneling and coulomb blockade Molecular devicesElectron transport in moleculesQuantum Cellular AutomataTunneling Spin TransistorsSpin transport in transistor structure

Rapid Single Flux Quantum RSFQ logic is a dynamic logic based upon a superconducting quantum effect, in which the storage and transmission of flux quanta defines the device operation. The basic RSFQ structure is a superconducting ring that contains one Josephson Junction (JJ) plus an external resistive shunt. The storage element is the superconducting inductive ring and the switching element is the Josephson Junction. RSFQ dynamic logic uses the presence or absence of the flux quanta in the closed superconducting inductive loop to represent a bit as a 1 or 0, respectively. The circuit operates by temporarily opening the Josephson Junction, thereby ejecting the stored flux quanta.

CNT transistorS. J. Wind,J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, Appl. Phys. Lett 80 (2002) 3817Major Challenges for CNT FETs What are the ultimate limits to the speed, size, density and dissipated energy of an CNT switch (e.g. FET) switch? How can 100 or more CNTs be combined in parallel to provide a total current 100x current of a single CNT? Possibilities for integration of individual CNT components in a complex circuit (billions of components per cm2) are unclear.

Single Electron Transistor (SET)

Electron movements are controlled with single electron precision Coulomb blockade effect Logic state set by 1) current or 2) phase

source

gate

island

drain

Quantum Cellular Automata: Wireless or Systolic Logic Circuitry? Logic CellAdder Circuit

Technology Performance and Risk EvaluationEmerging Research Logic DevicesPotential/Risk

Logic DeviceTechnologies

Performance [A]

Architecture compatible [B]*

Stability and reliability[C]

CMOScompatible[D]**

Operate temp[E]***

Energy efficiency[F]

Sensitivity parameter)[G]

Scalability[H]

1D Structures

2.3/2.2

2.2/2.9

1.9/1.2

2.3/2.4

2.9/2.9

2.6/2.1

2.6/2.1

2.3/1.6

RSFQ Devices

2.7/3.0

1.9/2.7

2.2/2.8

1.6/2.2

1.1/2.7

1.6/2.3

1.9/2.8

1.0/2.1

Resonant Tunneling Devices

2.6/2.0

2.1/2.2

2.0/1.4

2.3/2.2

2.2/2.4

2.4/2.1

1.4/1.4

2.0/2.0

Molecular Devices

1.7/1.3

1.8/1.4

1.6/1.4

2.0/1.6

2.3/2.4

2.6/1.3

2.0/1.4

2.6/1.3

Spin Transistor

2.2/1.7

1.7/1.6

1.7/1.7

1.9/1.4

1.6/2.0

2.3/2.1

1.4/1.7

2.0/1.4

SETs

1.1/1.2

1.7/1.2

1.3/1.1

2.1/1.4

1.2/1.8

2.6/2.0

1.0/1.0

2.1/1.7

QCA Devices

1.4/1.3

1.2/1.1

1.7/1.8

1.4/1.6

1.2/1.4

2.4/1.7

1.6/1.1

2.0/1.4

Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter

Emerging Technology SequenceArchitectureNon-classicalCMOSMemoryLogicRiskQuasi ballistic FETUTB single gate FETUTB multiple gate FETFloating body DRAMNano FG SETMolecularPhase changeSETRSFQQCAMolecularResonant tunnelingQuantum computingDefect tolerantCellular arraySource/Drain engineered FETBiologically inspiredTransport enhanced FETsSpin transistor1-D structuresInsulator resistance change

Emerging Research DevicesSummary Potential solutions for device structures necessary to achieve the advanced nodes (< 45-nm) identified For the ITRS gate density and switching time - Power density (not switch size) limits charge based logic density and performance CMOS is approaching the maximum power efficiency Emerging Research Device Technologies will extend CMOS into new application domains

SET-Based Tunneling Phase Logic (TPL)Coulomb BlockadeNonlinear Voltage-Charge CharacteristicU. MinnesotaUC - Berkeley

This shows the principle of the cell operation.

The cell consists of a PD-SOI nFET with its body floating.

For writing data 1, we operate the transistor in saturation leading to impact ionization which injects holes into the body.

For writing data 0, we forward-bias the pn junction between the body and the drain, ejecting the stored holes from the body to the drain.

Different from nanodot floating gate memory, which uses single electron charge storing, which controls drift current flow through a continuous channel, the single electron transistor memory uses single electron charge transport trough discontinuous channel (consisting of double tunnel junction), which is governed by Coulomb blockade