CHAPTER 12

Exercises E12.1 (a) vGS = 1 V and vDS = 5 V: Because we have vGS < Vto, the FET is in

cutoff.

(b) vGS = 3 V and vDS = 0.5 V: Because vGS > Vto and vGD = vGS − vDS = 2.5 > Vto, the FET is in the triode region.

(c) vGS = 3 V and vDS = 6 V: Because vGS > Vto and vGD = vGS − vDS = −3 V < Vto, the FET is in the saturation region.

(d) vGS = 5 V and vDS = 6 V: Because vGS > Vto and vGD = vGS − vDS = 1 V which is less than Vto, the FET is in the saturation region.

E12.2 First we notice that for V, 1 or 0=GSv the transistor is in cutoff, and the drain current is zero. Next we compute the drain current in the saturation region for each value of vGS: 26

21

21 mA/V 1)2/80)(1050()/( =×== −LWKPK

2)( toGSD VvKi −= The boundary between the triode and saturation regions occurs at toGSDS Vvv −=

GSv (V) Di (mA) DSv at boundary 2 1 1 3 4 2 4 9 3 In saturation, iD is constant, and in the triode region the characteristics are parabolas passing through the origin. The apex of the parabolas are on the boundary between the triode and saturation regions. The plots are shown in Figure 12.7 in the book.

E12.3 First we notice that for V, 1 or 0 −=GSv the transistor is in cutoff, and the drain current is zero. Next we compute the drain current in the saturation region for each value of vGS:

405

2621

21 mA/V 25.1)2/200)(1025()/( =×== −LWKPK

2)( toGSD VvKi −= The boundary between the triode and saturation regions occurs at

toGSDS Vvv −= .

GSv (V) Di (mA) DSv at boundary −2 1.25 −1 −3 5 −2 −4 11.25 −3

In saturation, iD is constant, and in the triode region the characteristics are parabolas passing through the origin. The apex of the parabolas are on the boundary between the triode and saturation regions. The plots are shown in Figure 12.9 in the book.

E12.4 We have ( 3)2000sin()() +=+= tVtvtv GGin πGS

Thus we have 4max =GSV V, 3=GSQV V, and 2min =GSV V. The characteristics and the load line are:

406

For vin = +1 we have vGS = 4 and the instantaneous operating point is A. Similarly for vin = −1 we have vGS = 2 V and the instantaneous operating point is at B. We find VDSQ ≅ 11 V, VDS min ≅ 6 V, VDS max ≅ 14 V.

E12.5 First, we compute

V 721

2 =+

=RR

RVV DDG

and 2621

21 mA/V 5.0)10/200)(1050()/( =×== −LWKPK

As in Example 12.2, we need to solve:

( ) 021 22 =−+

−+

KRVVVV

KRV

S

GtoGSQto

SGSQ

Substituting values, we have 062 =−− GSQGSQ VV

The roots are VGSQ = −2 V and 3 V. The correct root is VGSQ = 3 V which yields IDQ = K(VGSQ − Vto)2 = 2 mA. Finally, we have VDSQ = VDD − RSIDQ = 16 V.

E12.6 First, we replace the gate bias circuit with its equivalent circuit:

Then we can write the following equations:

2621

21 mA/V 5.0)10/400)(1025()/( =×== −LWKPK

205.11 +−== DQsGSQGG IRVV (1)

407

2)( toGSQDQ VVKI −= (2) Using Equation (2) to substitute into Equation (1), substituting values, and rearranging, we have 0162 =−GSQV . The roots of this equation are

.V 4±=GSQV However V 4−=GSQV is the correct root for a PMOS transistor. Thus we have 5.4=DQI mA and V. 1120 −=−+= DQDDQsDSQ IRIRV

E12.7 From Figure 12.21 at an operating point defined by VGSQ = 2.5 V and VDSQ = 6 V, we estimate

( ) mS 3.3

V 1mA 1.14.4

=−

=∆∆

=GS

Dm v

ig

( )( )

31005.0V 2-14mA 3.29.21 −×=

−≅

∆∆

=GS

Dd v

ir

Taking the reciprocal, we find rd = 20 kΩ.

408

E12.8 ( ) ( )toGSQpoQ

toGSGSpoQGS

Dm VVKVvK

vvig −=−

∂∂

=∂∂

=−−

2int

2

int

E12.9 Ωk 7.4111

1==

++=′ D

LDdL R

RRrR

( ) ( ) 32.8k 7.4mS 77.1oc −=Ω×−=′−= Lmv RgA

E12.10 For simplicity we treat rd as an open circuit and let LR ′ = RD RL.

gsmsgs vgRvv +=in

gsmLo vgRv ′−=

mL

mLov gR

gRvvA

′+′−

==1in

E12.11 Ωk 197.3==′ LDL RRR

( )( )( )( ) 979.0

mS 77.1k 7.21mS 77.1k 197.3

1in

−=+

−=

′+′−

==ΩΩ

mL

mLov gR

gRvvA

E12.12 The equivalent circuit is shown in Figure 12.28 in the book from which we

can write

409

0in =v xgs vv −= xmd

x

S

xgsm

d

x

S

xx vg

rv

Rvvg

rv

Rvi ++=−+=

Solving, we have

dSm

x

xo

rRgi

vR 111

++==

E12.13 Refer to the small-signal equivalent circuit shown in Figure 12.30 in the

book. Let LDL RRR =′ . gsvv −=in

gsmLo vgRv ′−=

mLov gRvvA ′== in inininin vgRvvgRvi msgsms +=−=

sm Rgi

vR1

1in

inin +

==

If we set v (t) = 0, then we have vgs = 0. Removing the load and looking back into the amplifier, we see the resistance RD. Thus we have Do RR = .

E12.14 See Figure 12.34 in the book. E12.15 See Figure 12.35 in the book.

Problems P12.1 See Figures 12.1 and 12.2 in the book. P12.2 Cutoff: iD = 0 for vGS ≤ Vto

Triode: iD = K[2(vGS − Vto)vDS − vDS

2] for vDS ≤ vGS − Vto (or vGD ≥ Vto) and vGS ≥ Vto Saturation: iD = K(vGS − Vto)2 for vGS ≥ Vto and vDS ≥ vGS − Vto (or vGD ≤ Vto)

410

P12.3* 221 mA/V 25.0)/( == LWKPK

(a) Saturation because we have vGS ≥ Vto and vDS ≥ vGS − Vto. iD = K(vGS − Vto)2 = 2.25 mA (b) Triode because we have vDS < vGS − Vto and vGS ≥ Vto. iD = K[2(vGS − Vto)vDS − vDS

2] = 2 mA (c) Cutoff because we have vGS ≤ Vto. iD = 0.

P12.4* iD

vGS = 4

3 V 2 V vDS

P12.5 The device is in saturation for vDS ≥ vGS − Vto = 3 V. The device is in the

triode region for vDS ≤ 3 V. In the saturation region, we have iD = K(vGS − Vto)2

= 0.1(vGS − 1)2 for vGS ≥ 1

In the pinchoff region, we have iD = 0 for vGS ≤ 1 The plot of iD versus vGS in the saturation region is:

411

P12.6 (a) Saturation because we have vGS ≥ Vto and vDS ≥ vGS − Vto. (b) Triode because we have vGS ≥ Vto and vDS ≤ vGS − Vto. (c) Saturation because we have vGS ≥ Vto and vDS ≥ vGS − Vto.

(d) Cutoff because we have vGS ≤ Vto.

P12.7 With the gate connected to the drain, we havevDS = vGS so vDS ≥ vGS − Vto. Then, if vGS is greater than the threshold voltage, the device is operating in the saturation region. If vGS is less than the threshold voltage, the device is operating in the cutoff region.

P12.8 For the NMOS enhancement transistors, we have Vto

= +1 V. For the PMOS enhancement transistors, we have Vto

= −1 V. (a) This NMOS transistor is operating in saturation because we have vGS

≥ Vto and vDS ≥ vGS − Vto. Thus, Ia = K(vGS − Vto)2 = 0.9 mA. (b) This PMOS transistor is operating in saturation because we have vGS ≤

Vto and vDS = −4 ≤ vGS − Vto = −3 −(−1) = −2. Thus, Ib = K(vGS − Vto)2 = 0.4 mA.

(c) This PMOS transistor is operating in the triode region because we have vGS ≤ Vto and vDS = −1 ≥ vGS − Vto = −5 −(−1) = −4. Thus, Ic = K[2(vGS − Vto)vDS − vDS

2] = 0.7 mA. (d) This NMOS transistor is operating in the triode region because we

have vGS ≥ Vto and vDS = 1 ≤ vGS − Vto = 3 − 1 = 2. Thus, Id = K[2(vGS − Vto)vDS − vDS

2] = 0.3 mA.

P12.9 With vGS = vDS = 5 V, the transistor operates in the saturation region for which we have iD = K(vGS − Vto)2. Solving for K and substituting values we obtain K = 125 µA/V2. However we have K = (W/L)(KP/2). Solving for W/L and substituting values we obtain W/L = 5. Thus for L = 2 µm, we need W = 10 µm.

P12.10 To obtain the least drain current choose minimumW and maximum L (i.e., W1 = 0.25 µm and L1 = 2 µm). To obtain the greatest drain current choose maximumW and minimum L (i.e., W2 = 2 µm and L2 = 0.25 µm). The ratio between the greatest and least drain current is (W2/L2)/(W1/L1) = 64.

P12.11* In the saturation region, we have iD = K(vGS − Vto)2. Substituting values, we obtain two equations:

412

0.2 mA = K(2 − Vto)2

1.8 mA = K(3 − Vto)2

Dividing each side of the second equation by the respective side of the first, we obtain

( )( )2

2

23

to

to

VV−−

=9

Solving we determine that Vto = 1.5 V. (We disregard the other root, which is Vto = 2.25 V, because the transistor would then be in cutoff with vDS = 2 V and would not give a current of 0.2 mA as required.) Then, using either of the two equations, we find K = 0.8 mA/V2.

P12.12 For a device operating in the triode region, we have

iD = K[2(vGS − Vto)vDS − vDS2]

Assuming that vDS << vGS − Vto this becomes

iD ≅ K2(vGS − Vto)vDS Then, the resistance between drain and source is given by

( )toGSDDSd VvKivr

−==

21/

With the device in cutoff (i.e., vGS ≤ Vto), the drain current is zero and rd is infinite. Evaluating, we have:

vGS (V)

rd (kΩ)

0.5 ∞ 1.0 10 1.5 5 2.0 3.33

P12.13 (a) This is an NMOS transistor. We have vGS = Vin and vDS = 5 V. With Vin

= 0, the transistor operates in cutoff and Ia = iD = 0. With Vin = 5, the transistor operates in satruation and Ia = iD = K(vGS − Vto)2 = 3.2 mA.

(b) This is a PMOS transistor. We have vGS = Vin − 5 and vDS = −5 V.

413

With Vin = 0, the transistor operates in satruation and Ib = iD = K(vGS − Vto)2 = 3.2 mA. With Vin = 5, the transistor operates in cutoff and Ib = iD = 0.

P12.14 Because vGD = 3 − 5 = −2 V is less than Vto, the transistor is operating in

saturation. Thus, we have iD = K(vGS − Vto)2. Substituting values gives 0.5 = 0.5(vGS − 1)2 which yields two roots: vGS = 2 and vGS = 0 V. However,

the second root is extraneous, so we have vGS = 2 = 3 − 0.0005R which yields R = 2000 Ω.

P12.15* We have 2)( toGSD VvKi −=

5. Substituting values and solving, we obtain

.2−=GSv and 5.1=GSv V. However, if 5.1=GSv , the PMOS transistor is operating in cutoff. Thus, the correct answer is 5.2−=GSv V.

P12.16 Distortion occurs in FET amplifiers because of curvature and nonuniform

spacing of the characteristic curves.

P12.17* The load-line equation is VDD = RDiD + vDS, and the plots are:

Notice that the load line rotates around the point (VDD, 0) as the resistance changes.

P12.18 The load-line equation is VDD = RDiD + vDS, and the plots are:

414

Notice that the load lines are parallel as long as RD is constant.

P12.19* For VGG = 0, the FET remains in cutoff so VDSmax = VDSQ =VDSmin = 20 V. Thus, the output signal is zero, and the gain is zero. For amplification to take place, the FET must be biased in the saturation or triode regions.

P12.20 (a) The 1.7 MΩ and 300 kΩ resistors act as a voltage divider that establishes a dc voltage VGSQ = 3 V. Then if the capacitor is treated as a short for the ac signal, we have vGS(t) = 3 + sin(2000πt) (b), (c), and (d) iD

vGS = 4 V 3 V 2 V vDS

From the load line we find VDSQ = 16 V, VDSmax = 19 V, and VDSmin = 11 V.

P12.21* For vin = +1 V we have vGS = 4 V. For the FET to remain in saturation, we

415

must have VDSmin ≥ 3 V at which point the drain current is 4.5 mA. Thus, the maximum value of RD is RDmax = (20 − 3)/4.5 mA = 3.778 kΩ.

P12.22 The Thévenin equivalent for the drain circuit contains a 12-V source in series with a 1.2-kΩ resistance. Then, we can construct the load line and determine the required voltages as shown:

P12.23 The KVL equation around the loop consisting of the VDD source, the nonlinear element, and the drain/source is DSDDD viV +== 21.020

The load line in this case is a parabola with its apex at iD = 0, vDS = 20 V as shown:

416

P12.24 Using KVL, we have ( )2000sin(3107)2000sin() tttvGS π+−=−+π= Thus, the maximum value of vGS is −2 V, the Q-point value is −3 V, and the

minimum value is −4 V. Applying KVL again, we obtain the load-line equation:

DDS iv −=− 10 in which the current is in mA. The load line is:

From the load line, we determine that the maximum value of vDS is

approximately −1.6 V, the Q-point is −5.5 V, and the minimum value is −8.8 V. The corresponding output voltages are 8.4 V, 4.5 V, and 1.2 V.

P12.25 We are given

vDS(t) = VDC + V1msin(2000πt) + V2mcos(4000πt)

Evaluating at t = 0.25 ms and observing that the plot gives vDS = 4 V at that instant we have

4 = VDC + V1m − V2m Similarly at t = 0 we have

11 = VDC + V2m and at t = 0.75 ms we have

16 = VDC − V1m − V2m Solving the previous three equations we have VDC = 10.5 V, V2m = 0.5 V and V1m = −6 V. Thus the percentage second−harmonic distortion is V2m/V1m × 100% = 8.33%. Thus this amplifier has a very large amount of distortion compared to that of a high quality amplifier.

417

P12.26 In an amplifier circuit, we need to bias the MOSFET so the ac signal to be amplified can cause changes in the currents and voltages resulting in an amplified signal. If the signal peak amplitude was smaller than 1 V, the transistor had Vto = 1 V, and we biased the transistor at VGSQ = 0, the transistor would remain in cutoff, iD(t) would be zero for all t, and the signal would not be amplified.

P12.27* For this circuit, we can write VGSQ = 15 − IDQRS

Assuming operation in saturation, we have

IDQ = K(VGSQ − Vto)2

using the first equation to substitute into the second equation, we have IDQ = K(15 − IDQRS − Vto)2 = 0.25(14 − 3IDQ)2

where we have assumed that IDQ is in mA. Rearranging and substituting values, we have

2DQI − 9.777IDQ + 21.777 = 0

The correct root is the smaller one which is IDQ = 3.432 mA. Then we have VDSQ = 30 − RDIDQ − RSIDQ = 16.27 V.

P12.28* We can write DQSDSQDD IRVV +=

.kΩ. Substituting values and solving, we

obtain 3=SR Next we have .mA/V 2)/( 221 == LWKPK Assuming

that the NMOS operates in saturation, we have 2)( toGSQDQ VVKI −= Substituting values and solving, we find 0=GSQV V and 2=GSQV V. The

correct root is 2=GSQV V. (As a check we see that the device does operate in saturation because we have DSQV greater than .toGSQ VV − ) Then we have =+ SGSQ= DQG IRVV 8 V. However we also have

21

2

RRRVV DDG +

=

Substituting values and solving, we obtain =2R 2 MΩ.

418

P12.29* We can write 28220 ++== DQDD IV in which IDQ is in mA. Solving, we obtain 5=DQI mA. Then, we find 400/2 == DQs IR Ω. Next, we have

.mA/V 75.0) 2=/(21= LWKPK Assuming that the NMOS operates in

saturation, we have 2)( toGSQDQ VVKI −= Substituting values and solving we find 582.1−=GSQV V and 582.3=GSQV

V. The correct root is 582.3=GSQV V. (As a check, we see that the device does operate in saturation because we have 8=DSQV V, which is greater than .toGSQ VV − ) Then, we have 582.52 =+= GSQG VV V. However, we also have

21

2

RRRVV DDG +

=

Substituting values and solving, we obtain =1R 2.583MΩ. P12.30 First, we use Equation 12.11 to compute

V 521

2 =+

=RR

RVV DDG

As in Example 12.2, we need to solve:

( ) 021 22 =−+

−+

KRVVVV

KRV

S

GtoGSQto

SGSQ

Substituting values, we have 02553.31489.12 =−− GSQGSQ VV

The roots are VGSQ = 2.4679 V and −1.319 V. The correct root is VGSQ = 2.4679 V which yields IDQ = K(VGSQ − Vto)2 = 0.5387 mA. Finally, we have VDSQ = VDD − RDIDQ − RSIDQ = 9.936 V.

P12.31 Assuming that the MOSFET is in saturation, we have

VGSQ = 10 − IDQ IDQ = K(VGSQ − Vto)2

419

where we have assumed that IDQ and K are in mA and mA/V2 respectively. (a) Using the second equation to substitute in the first, substituting values and rearranging, we have

VGSQ2 − 7VGSQ + 6 = 0

which yields VGSQ = 6 V. (The other root, VGSQ = 1 V, is extraneous.)

IDQ = 4 mA

VDSQ = 20 − 2IDQ = 12 V

(b) Similarly for the second set of values, we have

VGSQ2 − 3.5VGSQ − 1 = 0

VGSQ = 3.765 V

IDQ = 6.234 mA

VDSQ = 20 − 2IDQ = 7.53 V

P12.32 We can write DQSDSQDQDDD IRVIRV ++=

.k 3 Ω=

. Substituting values and solving we obtain SR Next we have .mA/V 2.0)/( 2

21 == LWKPK

Assuming that the NMOS operates in saturation, we have 2)( toGSQDQ VVKI −= Substituting values and solving we find 236.1−=GSQV V and 236.3=GSQV

V. The correct root is 236.3=GSQV V. (As a check we see that the device does operate in saturation because we have DSQV greater than

.toGSQ VV − ) Then we have 236.6=+= DsGSQG iRVV V. However we also have

21

2

RRRVV DDG +

=

Substituting values and solving, we obtain =2R 1.082 MΩ. P12.33 We have VG = VGSQ = 10R2/(R1 + R2) = 2.5 V. Then we have IDQ = K(VGSQ −

Vto)2 = 0.5625 mA. VDSQ = VDD − RDIDQ = 4.375 V.

420

P12.34* We have VGSQ = VDSQ = VDD − RDIDQ. Then substituting IDQ = K(VGSQ − Vto)2, we have

VGSQ = VDD − RDK(VGSQ − Vto)2

Substituting values and rearranging, we have

VGSQ2 + 2VGSQ − 39 = 0

Solving we determine that VGSQ = 5.325 V and then we have IDQ = K(VGSQ − Vto)2 = 4.675 mA.

P12.35 Beause vGD1 is zero, the first transistor operates in saturation. We have .A/V 50)/( 2

1121

1 µ== LWKPK Then, we have 2

11 )( toGSQD VVKi −= Substituting values and solving, we find 5.1−=GSQV V and 5.2=GSQV V.

The correct root is 5.2=GSQV V.

Then, the resistance is 5.122.05.25

1

==−

=D

GSQ

iV

R kΩ

The second transistor has 2222

12 A/V 100)/( µ== LWKPK and

4.0)( 222 =−= toGSQD VVKi mA.

Provided that Vx is larger than 2 V, the second transistor operates in saturation, iD2 is constant, and the transistor is equivalent to an ideal 0.4-mA current source.

P12.36 See Figure 12.20 in the book.

P12.37 pointpoint

1 −−

∂∂

=∂∂

=QDS

Dd

QGS

Dm v

irvig

P12.38 For constant drain current in the saturation region, we have rd = ∞.

P12.39 For VDSQ = 0, the vertical spacing of the drain characteristics is zero.

Therefore gm = 0 at this operating point. Then the small-signal equivalent circuit consists only of rd. FETs are used as electronically controllable resistances at this operating point.

421

P12.40* In the triode region, we have

iD = K[2(vGS − Vto)vDS − vDS2]

DSQQDSQGS

Dm KVKv

vig 22

pointpoint

==∂∂

=−

−

P12.41* In the triode region, we have

iD = K[2(vGS − Vto)vDS − vDS

2]

( )point

point

21−

−

−−=∂∂

= QDStoGSQDS

Dd vVvK

vir

)(21

DSQtoGSQd VVVK

r−−

=

P12.42 From Figure P12.42 at an operating point defined by VGSQ = 2.5 V and

VDSQ = 6 V, we have

( ) mS 9.4V 1

mA 5.14.6=

−==

GS

Dm v

ig∆∆

( )( )

310225.0V 4-8mA 1.30.41 −×=

−≅

∆∆

=DS

Dd v

ir

Taking the reciprocal, we find rd = 4.44 kΩ.

P12.43 mS 99 point

2

point

==∂∂

=−

−QGS

QGS

Dm v

vig

Ω=

==∂∂

=−

−

k 10

mS 1.01.01 pointpoint

d

QQDS

Dd

rvir

P12.44 mS 155.8)1exp(3)exp(3 point

point

===∂∂

=−

−QGS

QGS

Dm v

vig

422

Ω=

==∂∂

=−

−

k 5

mS 2.002.01 point

point

d

QDSQDS

Dd

r

vvir

P12.45 We will sketch the characteristics for vGS ranging a few tenths of a volt

on either side of the Q point. gm determines the spacing between the charactersistic curves. For gm = 2 mS, the curves move upward by 0.2 mA for each 0.1 V increase in vGS.

Also, we will sketch the characteristics for vDS ranging a few volts on

either side of the Q point. rd determines the slope of the charactersistic curves. For rd = 5 kΩ, the curves slope upward by 0.2 mA for each 1 V increase in vDS.

The sketch of the curves is:

P12.46 This transistor is operating with constant vDS. Thus, we can determine gm

by dividing the peak ac drain current by the peak ac gate-to-source voltage.

mS 5.0V 2.0

mA 0.1==

∆∆

== DSQDS VvGS

Dm v

ig

The Q-point is mA. 2 and V, 1 V, 4 === DQGSQDSQ IVV P12.47 This transistor is operating with constantvGS. Thus, we can determine rd

by dividing the peak ac drain-to-source voltage by the peak ac drain

423

current.

Ω==∆∆

==

k 200mA 01.0V 2

GSQGS VvD

DSd i

vr

The Q-point is mA. 3 and V, 2 V, 5 === DQGSQDSQ IVV P12.48 Coupling capacitors act as open circuits for dc and as approximate short

circuits for the ac signals to be amplified. Coupling capacitors are used in discrete circuits to isolate the various stages for dc so the bias points of the various stages can be determined independently while connecting the ac signal. The output coupling capacitor prevents dc current from flowing through the load and causes the ac signal to appear across the load. Furthermore, the input coupling capacitor connects the ac signal and prevents the dc component of the source from affecting the bias point of the input stage.

Coupling capacitors are replaced by short circuits in midband small-signal equivalent circuits. They cause the gain of an amplifier to decline as the signal frequency becomes small.

P12.49 See Figure 12.22 in the book.

P12.50* (a) V 33.07.1

3.02021

2 =+

=+

=RR

RVV DDG

V 3== GGSQ VV 2

21 mA/V 5.2)/( == LWKPK

mA 10)( 2 =−= toGSQDQ VVKI V 10 =−= DSQDDDDSQ IRVV S 01.02 == DQm KIg

(b) Ω 500/1/1

1=

+=′

LDL RR

R

5−=′−= Lmv RgA

Ωk 255/1/1

121

=+

=RR

Rin

Ωk 1== Do RR

424

P12.51 (a) V 33.07.1

3.02021

2 =+

=+

=RR

RVV DDG

V 3== GGSQ VV 2

21 mA/V 75.0)/( == LWKPK

mA 75.0)( 2 =−= toGSQDQ VVKI V 19.25 =−= DSQDDDDSQ IRVV S 0015.02 == DQm KIg

(b) Ω 500/1/1

1=

+=′

LDL RR

R

75.0−=′−= Lmv RgA

Ωk 255/1/1

121

=+

=RR

Rin

Ωk 1== Do RR Notice that the gain of the circuit can change a great deal as the

parameters of the FET change. P12.52 (a)

(b) ( ) ( ) foinininminLo RvvivgiRv −=−′=

fL

fLmL

in

ov RR

RRgRvvA

+′′−′

==

v

f

in

inin A

RivR

−==

1

The circuit used to determine output impedance is:

425

We define ( )fDD RRRR +=′ . Then we can write

vgs = vx RR

Rf+

and ix = D

x

Rv′ + gmvgs

RRRg

RivR

f

m

D

x

xo

++′

== 11

(c) The dc circuit is:

VGSQ = VDSQ IDQ = K(VDSQ − Vto)2 IDQ = (VDD − VDSQ)/RD Using the above equations, we obtain 055293 2 =+− DSQDSQ VV VDSQ = 7.08 V and IDQ = 4.31 mA

( ) S 1016.42 3

point

−

−

×=−=∂∂

= toGSQQGS

Dm VVK

vig

426

(d) Ωk 31.2==′ LDL RRR Av = − 9.37 Rin = 9.64 kΩ Ro = 414 Ω

(e) vo(t) = v(t) ×R + R

Rin

in × Av = −0.164sin(2000πt)

(f) This is an inverting amplifier that has a very low input impedance compared to many other FET amplifiers.

P12.53* Referring to the circuit shown in Figure P12.53, we have VGSQ = VDSQ IDQ = K(VGSQ − Vto)2 IDQ = (VDD − VDSQ)/RD From the previous three equations we obtain: 01.106.51.1 2 =−− DSQDSQ VV VDSQ = 6.50 V and IDQ = 6.135 mA

( ) mS 5.32point

=−=∂∂

=−

toGSQQGS

Dm VVK

vig

Ω 2531

1=

+=

+==

mDxmDx

x

x

xo gRvgRv

vivR

P12.54 See Figure 12.26 in the book. P12.55 If we need a voltage-gain magnitude greater than unity, we choose a

common-source amplifier. To attain lowest output impedance usually a source follower is better.

427

P12.56* We have

K =

LW

2KP

= 400 µA/V2

Assuming operation in saturation, we have IDQ = K(VGSQ − Vto)2

Solving for VGSQ and evaluating we have VGSQ = Vto + /KI DQ = 3.236 V

VG = VDD 21

2

RRR+

= 10 V

VG = VGSQ + RSIDQ Solving for RS and substituting values we have

RS = (VG − VGSQ)/IDQ = 3.382 kΩ

We have gm = 2 KI DQ = 1.789 mS

Ωk 257.1/1/1/1

1=

++=′

dSLL rRR

R

6922.01

=′+

′==

Lm

Lm

in

ov Rg

RgvvA

Ω==== k 7.66621 RRRivR G

in

inin

Ω=++

= 9.386111

dsm

o

rRg

R

P12.57 (a) We start by assuming that the MOSFET is operating in the

saturation region, so we have 2)( toGSQDQ VVKI −=

Also, we have 221 mA/V 5.1)/( == LWKPK

For a dc Q-point analysis, the capacitors behave as open circuits. Writing a voltage equation from the gate through Rs and back to ground through the VSS source, we obtain

GSQ SSDQs VIRV =+ Substituting for IDQ we have

SStoGSQsGSQ VVVKRV =−+ 2)(

428

Then substituting numerical values, we have 15)1(5.4 2 =−+ GSQGSQ VV Solving, we obtain VGSQ = 2.656 V (The other root is extraneous.) Then we have

mA 114.4)( 2 =−= toGSQDQ VVKI V 316.5)(30 =+−= DSDSQDSQ RRIV

Since VDSQ is higher than VGSQ − Vto the assumption that the device operates in the saturation region is valid. mS 968.42 == KIg DQm (b) Using the results from Exercise 12.13, we have

Ω==′ k 308.2LDL RRR 465.11in =′== mLov gRvvA

Ω=+

== 6.1881

1in

inin

sm RgivR

P12.58 See Figure 12.31 in the text. P12.59

429

P12.60 (a)

(b) All inputs high:

(c) All inputs low:

430