Introduction to VLSI and System-on-Chip Design
http://www.cs.nctu.edu.tw/~ldvan/
Lan-Da Van (范倫達), Ph. D.
Department of Computer Science
National Chiao Tung University
Taiwan, R.O.C.
Fall, 2013
SPICE
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-2
Outlines
Introduction
Full-Custom Design Flow
A SPICE Tutorial
Sources and Passive Components
Transistor DC Analysis
Transient Analysis
Subcircuits and Measurement
Device Models
Level 1 Models
Level 2 and 3 Models
BSIM Models
Conclusion
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-3
Full Custom Design Step
Spec. Def.: clock freq., I/O timing, function mapping...
Process Selection: (0.35um/0.18um/0.13um/90nm/65nm/45nm, logic, mixed-mode, Embed)CMOS, BiCMOS,GaAs, MEMS
Circuit Architecture: Dynamic/Static logic, Parallel/Serial/Pipelined ...
Circuit Simulation: functional simulation, timing verification, spec. analysis...
Layout Design: HandCraft Placement&Route
Layout Verification: DRC/ERC, LVS, ...
Post Layout Simulation: LPE, Delay Calculation , Back annotation
Lecture 7
Introduction to VLSI and System-on-Chip Design
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Specification
?
f
In Out
0 0 1 0 1 x
1 0 1 1 0 1
1/0 1/1
Function
Timing
2500um X 2500um Area
Power
T
Signal to Noise Ratio
200mW
50dB
Lecture 7
Introduction to VLSI and System-on-Chip Design
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Full-Custom Simulation Flow
Circuit Design and Simulation
Layout Design and Verification
Post Layout Verification
Tapeout Tapeout
Composer HSpice /Spectre
(Virtuso,Laker)/ (Calibre)
RC Extraction (Calibre)
GDSII
Design Environment–
Design Framework II (Cadence) Circuit Simulation - HSPICE Layout Editor – Virtuoso (Cadence), Laker (思源)
Layout Verification - Calibre, Diva, Dracula, Hercules
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-6
Circuit Architecture Design
Parallel v.s Sequential
Number of clock phase
Number of pipeline stage
Dynamic logic / Static logic
Current-mode /Voltage-mode operation
Gain stage type and stage number
Differential signal v.s. Single ended
Compensation scheme
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-7
Circuit Parameter Setting
In full-custom design, each parameter (including W/L,
capacitance, resistance) can be obtained by spec.
DC current (ID = F(VGS, W/L)) can be obtained by KCL,
KVL.
Delay time can be obtained by Tr (L/W)driver * (WL)load
In analog circuit, gain : -gm*ro , gm (W/L)1/2 , go = ID
According to the demanded current and voltage, we can
derive coarse estimated value of W/L.
According to environment, the capacitance can be
determined.
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-8
Design Corner
Because of process variation, the parameters of the transistor will be varied.
Each NMOS and PMOS have well-defined range of the process variations, those are slow, typical, and fast.
5 design corners simulation: ss,sf,tt,fs,ff
NMOS
PMOS
typical slow slow
typical
fast
fast Model
.lib “model_file” TT
.lib “model_file” SS
Or
.lib “model_file” mos_tt
Lecture 7
Introduction to VLSI and System-on-Chip Design
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Layout Design and Verification
電路設計及模擬的驗證決定電路的組成及相關參數，但仍不是實體的成品，積體電路的實際成品需經晶圓廠製作
設計者需提供積體電路製作的實體描述稱為佈局
佈局設計將所設計的電路轉換為電路製作的圖形描述格式
Laker工具提供佈局設計的環境
為讓晶片製作過程的合理變動不致影響製作的結果，電路設計者所設計的電路佈局必需滿足晶圓廠所提供的佈局規範。(Design Rule Check)
電路設計及佈局設計為不同階段的獨立設計過程，必須確保佈局設計及原電路的一致性。(Layout v.s. Schematic)
Calibre, Dracula等軟體提供佈局驗證的功能
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-10
Post Layout Simulation
實際的訊號線具有阻抗及負載，對原電路將造成特性上的改變，完整設計應考量訊號線的負載延遲效應。
準確的連接線模型方可促成正確的模擬結果。
完整的連接線負載包含龐大數量的雜散元件，完整的模擬將增加所需的時間，device reduction 為必須的考量。
佈局後模擬包含 電路及雜散元件萃取 + 電路模擬等兩項步驟。
Extraction Reduction
Lecture 7
Introduction to VLSI and System-on-Chip Design
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由於積體電路中訊號線的距離相當接近，一條訊號線上的訊號轉態會干擾鄰近訊號線的位準(Interconnect
coupling)。
由於積體電路的所有元件均位於同一基底上，因此，雜訊可能會透過基底干擾其他電路的運作(Substrate coupling)。
由於電路的電源訊號係由金屬線連至晶片各處，金屬線上的雜散電感值將使電流變化轉換為電壓降產生雜訊影響電路的運作(IR drop induced power/ground bounce)
Circuit Signal input
Noise input
Noise Analysis
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-12
Outlines
Introduction
Full-Custom Design Flow
A SPICE Tutorial
Sources and Passive Components
Transistor DC Analysis
Transient Analysis
Subcircuits and Measurement
Device Models
Level 1 Models
Level 2 and 3 Models
BSIM Models
Conclusion
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-13
Circuit Simulation: SPICE (1975)
SPICE: Simulation Program for Integrated Circuits
Emphasis SPICE was originally developed at the Electronics Research
Laboratory of the University of California, Berkeley (1975).
HSPICE is a robust industry standard.
Circuit simulators like SPICE numerically solve device
models and Kirchoff’s laws to determine time-domain
circuit behavior.
Numerical solution allows more sophisticated models
and non-functional (table-driven) models.
Written in FORTRAN for punch-card machines
– Circuits elements are called cards
– Complete description is called a SPICE deck
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Writing SPICE Deck
Writing a SPICE deck is like writing a good program
– Plan: sketch schematic on paper or in editor
Modify existing decks whenever possible
– Code: strive for clarity
Start with name, email, date, purpose
Generously comment
– Test:
Predict what results should be
Compare with actual
Garbage In, Garbage Out!
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Source
DC Source Vdd vdd gnd 2.5
Piecewise Linear Source Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8
Pulsed Source Vck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps
800ps
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MOSFET Element
M element for MOSFET Mname drain gate source body type
+ W=<width> L=<length>
+ AS=<area source> AD = <area drain>
+ PS=<perimeter source> PD=<perimeter drain>
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Common Elements & Units
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Example: RC Circuit
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Simulation Result (Textual)
.plot v(in) v(out)
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Simulation Result (Graphical)
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DC Analysis
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IV Characteristics Result
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Transient Analysis
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Transient Result
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layout view
schematic view
symbol view
Cell View
View name and view type are defined in technology file.
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Subcircuits
Declare common elements as subcircuits .subckt inv a y N=4 P=8
M1 y a gnd gnd NMOS W='N' L=2
+ AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'
M2 y a vdd vdd PMOS W='P' L=2
+ AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10’
.end
Ex: Fanout-of-4 Inverter Delay
– Reuse inv
– Shaping
– Loading
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Example: FO4 Inverter Delay (1/3)
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Example: FO4 Inverter Delay (2/3)
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Introduction to VLSI and System-on-Chip Design
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Example: FO4 Inverter Delay (3/3)
Lecture 7
Introduction to VLSI and System-on-Chip Design
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Outlines
Introduction
Full-Custom Design Flow
A SPICE Tutorial
Sources and Passive Components
Transistor DC Analysis
Transient Analysis
Subcircuits and Measurement
Device Models
Level 1 Models
Level 2 and 3 Models
BSIM Models
Conclusion
Lecture 7
Introduction to VLSI and System-on-Chip Design
Lan-Da Van VLSI-07-31
SPICE MOSFET Models
Level 1: Based on the Shichman-Hodges equations that are similar to hand analysis Not very accurate
Simple channel length modulation
Simple body effect model
Level 2: Based on the Grove-Frohman equations more accurate model and faster (effective channel length,
etc.)
Level 3: Based on the empirical equations more accurate model and faster (effective channel length,
etc.)
BSIM (Berkeley Short-Channel Insulated Gate Field Effect
Transistor Model): efficient empirical model BSIM1 (level 13), BSIM2 (level 39), BSIM3v3 (level 47),
BSIM4 (level 54),
Lecture 7
Introduction to VLSI and System-on-Chip Design
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Some SPICE Model Parameters
L: transistor length
W, : transistor width
KP: transconductance
GAMMA: body bias factor
AS, AD: source/drain areas
CJSW: zero-bias sidewall capacitance
CGBO: zero-bias gate/bulk overlap
capacitance
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Level 1 MOS FET Model
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Conclusion and Reference
Widely discuss the following items: Design Flow
SPICE Simulation
SPICE Commands
Device Model
Reference: Neil Weste and David Harris, “CMOS VLSI Design: A
Circuits and Systems Perspective”, 4rd, 2005.
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