15

CHAPTER 2

UPFC WITHOUT DC LINK CAPACITOR

2.1 INTRODUCTION

The unified power flow controller, which has been recognized as one of the

best featured FACTS devices [20, 38, 40], is capable of providing simultaneous

active and reactive power flow control, as well as voltage magnitude control.

The UPFC is a combination of static synchronous compensator and static

synchronous series compensator which is connected via a common dc link, to allow

bi-directional flow of real power between series output terminals of SSSC and the

shunt terminals of the STATCOM, and is allowed to provide concurrent real and

reactive power compensation.

The UPFC comprises of two voltage source inverters, operated from a

common dc link provided by a dc storage capacitor. The dc link capacitor should be

properly designed so as to substantially reduce the ripple present in the dc

voltage [57]. The ratings of this dc link capacitor bank pose a significant impact on

the cost and physical size of the UPFC. Besides, this capacitor has shorter life when

compared to ac capacitor of same rating. This in turn limits the life and reliability of

the voltage source inverter [50]. Therefore efforts have to be taken to eliminate the

need of the dc link capacitor and still obtain more or less the same performance. It is

in this pretext two different schemes of UPFC without dc link capacitor have been

proposed.

In the first method the dc link capacitor present in the UPFC is eliminated

and suitable modulation techniques [85, 86] are employed in the converter

configurations so as to operate the UPFC without degrading its performances. The

16

front end converter is operated through a relatively new PWM scheme that enables

to regulate the dc link voltage, minimize the ripples and improve the shape of the dc

link current. Space vector modulation (SVM) strategy is used to fire the switches in

the VSI.

In the second method a matrix converter is employed in UPFC whereby the

classical ac/dc and dc/ac converter structure with dc link capacitor is replaced by a

matrix converter. The indirect space vector modulation technique is used to control

the matrix converter present in the UPFC. The ISVM algorithm for the matrix

converter has the inherent capability of controlling simultaneously both the output

voltage vector and the instantaneous input current displacement angle [87].

The scope includes evaluating the performance of the proposed schemes of UPFC

on a sample power system, in its different operating modes through MATLAB based

simulation and highlights its ability as a powerful voltage regulator and a power

controller.

2.2 POWER SYSTEM WITH THE EXISTING SCHEME OF UPFC

The scheme of UPFC connected with a simple power system is shown in the

Fig. 2.1. UPFC is placed between two sections B2 and B3 of the transmission line.

The feeding network is represented by a Thevenin’s equivalent circuit [88, 89] at

bus B1 where the voltage source is a 230 kV with a short circuit power level of

10,000 MVA and an X/R = 8. The system parameters are given in APPENDIX-A.

The STATCOM model in the UPFC is connected in shunt with the

transmission line using a step-down transformer having leakage reactance XT and a

three phase IGBT based current source rectifier. The ac voltage difference across

this transformer leakage reactance produces reactive power exchange between the

STATCOM and the power system at the point of interface. The voltage can be

regulated to improve the voltage profile of the interconnected power system. Thus

the main function of STATCOM is to regulate the bus voltage magnitude either by

absorbing or generating reactive power to the ac grid network. The SSSC which is

17

connected in series with the transmission line through a series transformer enhances

the power flow over the line by emulating a series capacitance. The capacitance

effect in series with the line is brought by injecting a voltage which is lagging the

line current by 90°.

Fig. 2.1 Power system embedded with a conventional scheme of UPFC

2.3 PROPOSED SCHEME OF UPFC WITHOUT DC LINK CAPACITOR

The elimination of dc link capacitor results in considerable ripple in the dc

link voltage and current distortions in the ac side. To overcome such problems three

capacitors of much smaller rating and lower cost are used in the STATCOM side.

The first converter present in the STATCOM side is operated as a current source

rectifier (CSR) with a suitable pulse width modulation (PWM) technique.

The objectives of this rectifier are to maintain a fixed dc voltage on the dc link

without the dc link capacitor and to regulate the bus voltage. This CSR is connected

in shunt with the transmission line through a coupling transformer. The converter

present in the SSSC is connected in series with the transmission line through a series

insertion transformer. It is controlled using space vector modulation technique to

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enable it to generate synchronous ac voltage of controllable magnitude and phase

angle with reduced harmonics.

The scheme of ac-dc-ac conversion without dc link capacitor is shown in

Fig.2.2. The filter components R, Lf and Cf present at the input side of the first

converter have a significant role in maintaining the dc link current constant and

reducing the distortions at the transformer and CSR interface. The switching

functions of the current source rectifier and voltage source inverter are adjusted to

maintain the average dc side voltage and current constant [45].

Fig. 2.2 Scheme of ac-dc-ac conversion without dc link capacitor

2.3.1 Modulation Techniques

It is assumed that the ac input voltages to the current source rectifier after the

step down shunt transformer are the three-phase balanced sinusoidal voltages. The

expected line currents in the STATCOM side and the fundamental component of the

line voltages injected into the transmission line in the SSSC side are described as

( )a m i in

b m i in

c m i in

i = I cos ω t - ψ

2πi = I cos ω t - ψ - 32πi = I cos ω t - ψ + 3

⎛ ⎞⎜ ⎟⎝ ⎠⎛ ⎞⎜ ⎟⎝ ⎠

(2.1)

19

where ψin is the STATCOM side power factor angle

su om Tu

sv om Tv om Tu

sw om Tw om Tu

v = V cosθ 2πv = V cosθ = V cos θ - 32πv = V cosθ = V cos θ + 3

⎛ ⎞⎜ ⎟⎝ ⎠⎛ ⎞⎜ ⎟⎝ ⎠

(2.2)

where θTu, θTv and θTw are the angle of the expected output voltage vectors.

A Modified PWM Strategy for the CSR

The dc side voltage of UPFC is essentially decided by the switching function of

the first converter present in the STATCOM and the ac input voltage. In one full cycle of

the ac input there are six switching intervals, during which one of the line or phase

voltages will have the maximum absolute value. For example, in the interval 1, Vsa has the

largest absolute voltage and in the interval 2, Vsc has the largest absolute voltage and so

forth in all the intervals of the three phase sinusoidal voltage of a cycle.

Each switching interval is divided into two portions. During the interval 1,

when Vsa has the largest absolute voltage, T1 is held ON with T6 for the first 30o

conduction period and all other rectifier switches remain in the OFF state. The dc

side voltage is Vdc = Vsa-Vsb. In portion 2, for the next 30o conduction period T1 is

held ON with T2 and all other rectifier switches are OFF. The dc side voltage is

Vdc = Vsa-Vsc. The above sequence is applicable for all other intervals. By

providing this switching sequence, dc voltage at the dc link can be maintained with a

constant value.

Table 2.1 shows the states of the rectifier switches and the dc voltage of each

portion for all the six intervals. Fig.2.3a) and Fig.2.3b) depict the carrier waveform

and the PWM scheme applied to the front end converter using sinusoidal pulse width

modulation (SPWM) technique respectively. The carrier which is initially triangular in

nature slowly changes into ramp and serves to reduce the line side THD. Fig. 2.3c) clearly

depicts the switching pulses applied to the switches present in the converter 1.

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Table 2.1 Switch state and the dc voltage in each interval

Interval Portion 1 Portion 2 ON switch Vdc ON switch Vdc 1 T1, T6 Vsa- Vsb T1, T2 Vsa - Vsc 2 T2, T1 Vsa - Vsc T2, T3 Vsb - Vsc 3 T3, T2 Vsb - Vsc T3, T4 Vsb - Vsa 4 T4, T3 Vsb - Vsa T4, T5 Vsc - Vsa 5 T5, T4 Vsc - Vsa T5, T6 Vsc - Vsb 6 T6, T5 Vsc- Vsb T6, T1 Vsa - Vsb

Fig. 2.3 a) Carrier signal

Fig. 2.3b) PWM scheme for the first converter

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Fig. 2.3c) Switching pulses for the first converter

The first converter switches commutate only at the transition between adjacent portions. The switches are made to commutate with zero current by setting zero voltage vector of the inverter to occur at both the beginning and ending of each portion. A separate synchronizing circuit is required [48] to ensure the occurrence of zero voltage vector of the second converter during the commutation of the first converter switches when conventional sinusoidal pulse width modulation technique is employed. However this need for synchronizing circuit can be eliminated if space vector modulation technique is employed instead of sinusoidal pulse width modulation for the second converter.

SVM Strategy for the VSI

Space vector modulation is essentially an averaging technique that takes into consideration that a three-phase inverter has only eight switch states. Each leg has two switch states. Therefore, 23 states can be obtained for the three independent legs of the inverter. The desired three phase voltages at the output of the inverter, operated in the 180° mode can be represented by an equivalent vector Vo rotating in the counter clockwise direction in a two dimensional (d, q) plane as shown in Fig. 2.4. For example, when the desired line to line output voltage vector Vo is in sector 1, it could be synthesized by the pulse-width modulation of the adjacent state space vectors V4(100) and V6(110). The duty cycle of each being d4 and d6 respectively, with the zero vectors V0(000) or V7(111) of duty cycle d0.

22

a m in Tu4 64 6

M 3V cos ψ θd V +d V = 2

(2.3)

d0 = 1-d4-d6

where Ma is the modulation index and 0<Ma <0.866

Using the same theory, analogous vectors and respective duty cycles can be

derived when the system operates in other sectors. The SVM train of pulses applied

to the inverter is as shown in Fig.2.5.

Fig. 2.4 Space vector diagram

Fig. 2.5 SVM pulses applied to the inverter

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2.3.2 Modes of Operation of the Proposed Scheme of UPFC

Automatic Voltage Control Mode for STATCOM

The controller seen in Fig.2.6 is an integral part of the converter present in

STATCOM to operate it in the automatic voltage control mode. Its function is to

maintain a fixed dc voltage in the dc link without the storage capacitor and ensure

unity power factor in the supply side.

Fig. 2.6 Control block diagram of STATCOM

The reference waveform for the pulse width modulator is derived from the

direct and quadrature components Vd,av and Vq,av respectively. The real power

reference is derived from a dc bus voltage controller and the reactive power is

directly controlled treating iq* as zero, in order to achieve unity power factor

operation [90]. The decoupled control system ensures that a change in the real power

reference can be envisaged without any transient in the reactive power reference and

vice versa. The parameters of the PI controllers used are given in the Table 2.2.

Automatic Power Flow Control Mode for SSSC

The main function of the static synchronous series compensator is to control

the power flow over the transmission line. The control scheme [43] shown in the

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Fig.2.7 operates the SSSC in the automatic power flow control mode. The reference

inputs (Pref and Qref) are chosen accordingly.

Fig. 2.7 Control block diagram of SSSC

A phase locked loop (PLL) is used to determine the instantaneous angle θ of

the three-phase line voltage Vabc sensed at bus B2 of Fig.2.6. The active and reactive

power flows over the transmission line are determined from the actual line currents

and voltages. Separate PI controllers with optimal values seen in Table 2.2, are used

in the feedback path to regulate the active power and reactive power. The

modulation index Ma to the PWM modulator is derived as

a a a,seM = ΔM M+ (2.4)

where ( )ia p ref act

KΔM = K + P -Ps

⎛ ⎞⎜ ⎟⎝ ⎠

The reference angle θT to the PWM modulator is generated as

Tθ = θ - β (2.5)

where ( )ip ref act

Kβ = K + Q -Q

s⎛ ⎞⎜ ⎟⎝ ⎠

The desired compensation is obtained by either adding or subtracting π/2

with β depending upon whether it is inductive or capacitive. The modulation index

Ma and the phase angle θT are applied to the PWM modulator to generate the SSSC

compensating voltage.

25

Table 2.2 PI controller parameters of the proposed UPFC scheme

PI controllers Kp Ki PI1 0.015 1.6

PI2 0.1 40

STATCOM PI3 0.1 40

PI1 20 2 SSSC

PI2 16 25

2.3.3 Performance Evaluation of the Proposed Scheme of UPFC

Automatic Voltage Control Mode

The proposed model of UPFC is simulated using MATLAB/Simulink.

Fig.2.8 shows the bus voltage and current in the STATCOM side, which are found

to be almost in phase with each other. This explains that the UPFC performs the role

of shunt compensator by either absorbing or supplying the reactive power with the

transmission line. There exists a small phase difference between the bus voltage and

current so as to absorb power from the ac system in order to replenish the operating

losses of the converter.

The THD response of the line current and line voltage in the STATCOM side

given in Figs.2.9 a) and 2.9 b) respectively are found to be very low through a

proper choice of filter components. The dc link voltage and current waveforms of

the proposed scheme of UPFC are compared with that of the existing scheme in

Fig.2.10. Fig.2.11a) shows the distorted dc link current waveform when the dc link

as well as ac capacitors are not present. The steady dc current obtained at the dc link

depicted in Fig.2.11b) emphasizes the necessity of using capacitors on the

ac side.

26

Fig. 2.8 Transmission line voltage and current with UPFC

Fig. 2.9a) Line current THD in the STATCOM side

Fig. 2.9b) Line voltage THD in the STATCOM side

27

a) Existing scheme of UPFC

b) Proposed scheme of UPFC

Fig. 2.10 Comparison of dc link voltage and current

28

a) without AC capacitor

b) with AC capacitor

Fig. 2.11 DC link current of the proposed UPFC scheme

Automatic Power Flow Control Mode

The UPFC is operated with the most powerful control mode namely the

automatic power flow control mode in which the UPFC can directly control the

active and reactive power by controlling the magnitude and angle of the series

injected voltage. The VSI output voltage of the series converter is shown in the

Fig.2.12. This voltage, which is injected in series with the transmission line, lags

the line current almost by 90˚ as seen in Fig.2.13. This reveals that the SSSC

operates in the capacitive mode. The occurrence of a very small deviation of the

injected voltage with respect to the line current is due to the real power losses of the

coupling transformer and the switches in the VSI.

29

Fig.2.12 VSI output voltages with SVM technique

Fig. 2.13 Series injected voltage with respect to transmission line current

30

The transient performance of the system is evaluated by suddenly changing

the load at time t = 0.1 s from an initial value of 300 MW, 220 MVAR to a new

value of 270 MW, 220 MVAR. The variation of P and Q over the line is found to

track almost their reference set values irrespective of load variations as depicted in

Fig.2.14 because of the voltage injected in series at an appropriate angle.

Fig. 2.14 Real and reactive power flow over the transmission line with UPFC

A three-phase fault of 50 ms duration is introduced in the transmission line at

t = 0.2 s and is allowed to be cleared at t = 0.25 s. The voltage across the

STATCOM bus suddenly goes to zero as shown in Fig.2.15a). This results in a

corresponding reduction in dc voltage and current magnitudes and the output of the

VSI present in the SSSC side as depicted in Figs 2.15b) and 2.15c) respectively.

However P and Q of the transmission line settles to their reference values within a

small interval of time once the fault is cleared as seen in Fig. 2.15d).

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a) Line voltage and current in the STATCOM side

b) DC link voltage and current

32

c) VSI output voltages in the SSSC side

d) Real and reactive power flow over the transmission line

Fig. 2.15 Transient responses for a three-phase fault with UPFC

33

2.4 UPFC USING MATRIX CONVERTER

Though the proposed scheme of UPFC without dc link capacitor perform

similar to the existing scheme of UPFC a noisy dc link performance is observed due

to the lack of dc capacitor. To overcome this limitation, a matrix converter is

employed in UPFC as shown in Fig.2.16 whereby the classical ac/dc and dc/ac

converter structure with dc link capacitor is replaced by a matrix converter [91].

Matrix converters which have an array of nine bidirectional switches are found to be

more reliable and potential enough to have much longer life, because of the absence

of the dc link capacitor. Besides, it has several advantages such as single stage

conversion, bidirectional power flow, less number of switches and guarantees input

and output sinusoidal voltages and currents with reduced THD [92-95]. The indirect

space vector modulation technique has been used to control the matrix converter

present in the UPFC [94, 95]. The ISVM algorithm for the matrix converters has the

inherent capability of controlling simultaneously both the output voltage vector and

the instantaneous input current displacement angle.

Fig. 2.16 Proposed scheme of UPFC with matrix converter

34

2.4.1 Switching Algorithm

In matrix converter, each output phase is connected to each input phase

depending on the state of the switches. Considering that each bidirectional switch is

either in the ON or OFF condition, (29 = 512) different states of the matrix converter

can be defined. For safe operation of the matrix converter input phases should never

be short circuited and output phases should never be opened at any switching time.

Hence the number of allowable switching combination is reduced to 27. Out of

these 27 switching combinations 18 active switching vectors and three zero vectors

are used. The MC switching combination is given in the APPENDIX-B.

In the indirect space vector modulation technique, the matrix converter is

considered as a two stage transformation converter: a rectification stage to provide a

constant imaginary dc link voltage per switching period and an inverter stage to

produce three phase output voltages. However it is only the same nine switches that

perform both rectification and inversion.

Input Current SVM

The SVM uses a combination of two adjacent vectors and a zero vector to

produce the reference current vector as depicted in Fig. 2.17. The input currents can

be considered constant during a short switching interval Ts. Then, for the switching

combination from groups II and III in Appendix-B, the input phase current space

vector is defined as

( )120 12023

−= + +j ji a b ci i i e i e (2.6)

It is assumed that there are only seven discrete positions in the complex

plane, called the input current switching state vectors (SSVs), as shown in Fig.2.17.

For example, if the switching combination 1 from the sub group II-A in the

(APPENDIX–B) is used, the input phase currents are Ia = IA, Ib = 0 and

Ic = -IA, producing the SSV I1 if IA > 0 and I4 if IA < 0 switching combination 4

35

produces the same SSVs but for the opposite polarity of IA. The remaining four

SSVs are produced in a similar manner. All the SSVs have the same magnitude,

which from Fig.2.17 is

k o m2I = I3

kє{1,…6} (2.7)

where om AI = i is the maximum output current

Fig. 2.17 Input current SVM

The desired reference current vector is defined as

i inj(ω t-ψ )in imi = I e (2.8)

where Iim is the maximum input current

ψin is the STATCOM side power factor angle

The input current iin can be approximated by adjacent two switching state

vectors, Iγ and Iδ as shown in Fig.2.18.

Fig. 2.18 Current vector in sector 1

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The switching combinations from subgroups II-B and II-C produce SSVs in

same positions but with different magnitudes, given by equation (2.7) and by

Iom = ׀iB׀ and Iom = ׀iC׀ respectively. The switching combinations from group III

result in the zero input current SSV I0. The duty cycles of the SSVs are

γγ ai si

S

T πd = = M sin - θT 3

⎛ ⎞⎜ ⎟⎝ ⎠

(2.9)

δδ ai si

S

Td = = M sinθT

(2.10)

zizi γ δ

S

Td = = 1 - d - dT

(2.11)

where Mai is the modulation index of the virtual rectifier stage.

ai0 M 1≤ ≤

imai

om L

2IM =3I cosφ

where Lφ is the displacement angle between the output voltage and current

Output Voltage SVM

The output line voltage space vector is defined as

( )j120 j120o AB BC CA

2V V V e V e3

−= + + (2.12)

which assumes seven discrete positions in the complex plane, as shown in Fig. 2.19.

Fig. 2.19 Output voltage SVM

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The reference voltage vector is defined as

( )Tj θ + 30o omv = 3 V e

°

(2.13)

This vo can be approximated by two adjacent switching state vectors, Vα and

Vβ and the zero voltage vector Vz using PWM technique as shown in Fig.2.20.

βα zvo α β z

S S S

TT TV = V + V + VT T T

α α β β zv z= d V + d V + d V (2.14)

where Vo is the sampled value of vo at an instant within the switching cycle TS.

The duty cycle of the active switching vectors for the inversion stage Vα and

Vβ are calculated as

α a svπd = M sin - θ3

⎛ ⎞⎜ ⎟⎝ ⎠

(2.15)

β a svd = M sinθ (2.16)

where Ma is the modulation index of the inversion stage a0 M 1≤ ≤

oma

im in

2 VM = 3V cosψ

where Vom is the maximum output voltage

Vim is the maximum input voltage

Fig 2.20 Voltage vector in sector 1

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A proper balance between the input currents and the output voltages is

obtained in the same switching period. Each switching pattern of the inversion stage

should include both the active sequence of the rectification stage as shown in

Fig.2.21. In the first active portion of the inversion stage, the durations of the

rectification stage active switching vectors are obtained by the following product:

dαγ = dαdγ

dαδ = dα dδ

In second active portion these durations are calculated as follows:

dβγ = dβ dγ

dβδ = dβdδ

Each duty cycle sequence is a result of the product of the rectification and

inversion stage duty cycles. One switching sequence is completed by the zero

vectors with a duty ratio of

( )z αγ αδ βγ βδd = 1- d + d + d + d (2.17)

The duration of each sequence is found by multiplying the corresponding

duty cycle to the switching period.

Fig. 2.21 ISVM switching pattern

Thus in the ISVM method, the four active states and the zero state to be

applied in each PWM period are determined according to the sector in which the

space vectors of output voltage and input current lie. In order to reduce harmonic

distortion, duty cycles are symmetrically distributed round the zero state duty cycle

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as shown in this figure. The train of pulses obtained using ISVM is shown in

Fig.2.22.

Fig. 2.22 ISVM pulses applied to the matrix converter

2.4.2 Control Scheme of MC based UPFC

The closed loop control scheme shown in Fig.2.23 is an integral part of the

matrix converter present in the UPFC to operate the STATCOM part of the UPFC in

improving the power factor and SSSC part to enhance the power flow over the line.

A single closed control strategy has been used for controlling both the input current

displacement angle as well as the series injected voltage, thereby controlling the

power flow. The references derived separately from the STATCOM and SSSC parts

of the UPFC are combined in the ISVM pulse generator. The ISVM pulse generator

in turn generates appropriate control pulses for the matrix converter switches.

The SSSC control is similar to that described in section 2.3.2.

The parameters of the PI controllers are given in Table 2.3. In the shunt control, in

order to achieve unity power factor the real and reactive power components of the

current must be controlled independently. The real and reactive current references

40

are derived from the instantaneous real and reactive power flow over the line. The

instantaneous real and reactive power can be written in terms of d-q quantities as

( )d d q q3P = V I + V I2

(2.18)

( )d q q d3Q = V I - V I2

(2.19)

From equations (2.18 and 2.19) the real and reactive current references are

derived as follows

ref d ref q*d 2 2

d q

P V + Q V2I = 3 V + V⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠

(2.20)

ref q ref d*q 2 2

d q

P V + Q V2I = 3 V + V⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠

(2.21)

where Pref is the real power reference

Qref is the reactive power reference

Fig. 2.23 Closed loop control scheme of UPFC with MC

The reactive power reference Qref is set to 0 in order to achieve unity power factor. The derived two phase current commands are converted into three phase quantities using dq-abc transformation. These three phase current references are fed as control signals to the rectifier SVM pulse generator. Similarly the voltage

41

references derived from series control part are fed to the inverter SVM pulse generator. The MC pulse generator uses the control signals from the rectifier and inverter pulse generators for generating appropriate control signals to the matrix converter switches.

Table 2.3 PI controller parameters of the MC based UPFC

PI Controllers Kp Ki

PI1 20 2

PI2 16 25

2.4.3 Performance Evaluation of the MC based UPFC

The performance of the matrix converter based UPFC is analyzed through MATLAB/Simulink based simulation. The matrix converter output phase and line voltages along with their fundamental components are shown in Figs. 2.24 and 2.25 respectively.

Fig. 2.24 MC output phase voltage with its fundamental

42

Fig. 2.25 MC output line voltage with its fundamental

The initial load in the system with the ratings of 600 MW, 150 MVAR

connected at load bus B5 through the circuit breaker CB1 is disconnected at time

t = 0.15 s and a second load with ratings of 650 MW, 200 MVAR is connected to

the system. The transmission line current lags the transmission line voltage as

shown in Fig.2.26 in the absence of UPFC. The STATCOM part of the UPFC

maintains the line current almost in phase with the voltage as depicted in Fig.2.27.

This shows that the UPFC performs the role of shunt compensator by either

absorbing or supplying the reactive power for any load variations.

The magnitude of the quadrature voltage injected by the SSSC depending on

the load variations varies as depicted in the Fig.2.28 in order to maintain the real and

reactive power flow over the line to follow the set reference values as shown in

Fig.2.29.

43

Fig. 2.26 Transmission line current and voltage before compensation

Fig. 2.27 Transmission line current and voltage with shunt compensation

44

Fig. 2.28 Series injected voltage and transmission line current

Fig. 2.29 Real and reactive power flow over the transmission line with MC

based UPFC

45

2.5 SUMMARY

The contribution of this chapter is to propose a novel structure of UPFC to be

connected into the transmission line. Since the cost and space occupied by the dc

link capacitor in the existing UPFC structure are quite large the proposed schemes

eliminate the dc link capacitor. With the proposed scheme 1 a noisy dc link

performance is obtained in the dc link, which is due to the lack of dc capacitor. To

reduce this problem space vector modulation technique is employed for the voltage

source inverter present in the SSSC side. Also another scheme of UPFC is proposed

whereby the classical ac/dc and dc/ac converter structure with dc link capacitor is

replaced by a matrix converter. The indirect space vector modulation technique

effectively used to generate the control pulses for the matrix converter switches.

The performance of the proposed schemes has been analyzed with

MATLAB/Simulink assuming that the UPFC is connected with the 230 kV

transmission line of sample power system. The STATCOM offers a good voltage

regulation and the SSSC controls the magnitude and angle of the injected voltage so

as to maintain the real and reactive power flow over the transmission line to follow

the set reference values in spite of variations in the load and the operating

conditions. The proposed schemes of UPFC interfaced in the sample power system

accomplish a similar performance as that of a traditional system.