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Multiplication
More complicated than addition accomplished via shifting and addition
More time and more area Let's look at 3 versions based on grade
school algorithm
0010 (multiplicand)
__x_1011 (multiplier)
Multiplication: Implementation
64-bit ALU
Control test
MultiplierShift right
ProductWrite
MultiplicandShift left
64 bits
64 bits
32 bits
Done
1. TestMultiplier0
1a. Add multiplicand to product andplace the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
Product Multiplier Multiplicand 0000 0000 0011 0000 0010
0000 0010 0001 0000 01000000 0110 0000 0000 10000000 0110
Second Version
MultiplierShift right
Write
32 bits
64 bits
32 bits
Shift right
Multiplicand
32-bit ALU
Product Control test
Done
1. TestMultiplier0
1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register
2. Shift the Product register right 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
0000 0000 0011 00101: 0010 0000 0011 00102: 0001 0000 0011 00103: 0001 0000 0001 00101: 0011 0000 0001 00102: 0001 1000 0001 00103: 0001 1000 0000 00101: 0001 1000 0000 00102: 0000 1100 0000 00103: 0000 1100 0000 00101: 0000 1100 0000 00102: 0000 0110 0000 00103: 0000 0110 0000 0010
0000 0110 0000 0010
Product Multiplier Multiplicand
Final Version
ControltestWrite
32 bits
64 bits
Shift rightProduct
Multiplicand
32-bit ALU
Done
1. TestProduct0
1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register
2. Shift the Product register right 1 bit
32nd repetition?
Start
Product0 = 0Product0 = 1
No: < 32 repetitions
Yes: 32 repetitions
Signed Multiplication
Convert the multiplier and multiplicand to positive numbers and remember the original signs.
Negate the product if the original signs disagree.
A more elegant method: Booth’s algorithm
Booth’s Algorithm
Classifying groups of bits into the beginning, the middle or the end of a run of 1s
Take a look at 2-bit groups
0 1 1 1 0
Middle of Run
End of Run Beginning of Run
Current Bit Bit to the right Explanation Example1 0 Beginning of a run of 1s 000011110001 1 Middle of a run of 1s 000011110000 1 End of a run of 1s 000011110000 0 Middle of a run of 0s 00001111000
Booth’s Algorithm (Cont’d)
Depending on the current and previous bits, do one of the following: 00: no arithmetic operation 01: End of a string of 1s, so add multiplicand to
the left half of the product 10: Beginning of a strings of 1s, so subtract the
multiplicand from the left half of the product 11: no arithmetic operation
Shift the Product register right 1 bit.
Example
2x-3 = 6 or 0010x1101 = 1111 1010Iteration Step Multiplicand Product0 Initial values 0010 0000 1101 0
1c:10=>P-M 0010 1110 1101 012: Shift right P 0010 1111 0110 11b:01=>P=P+M 0010 0001 0110 122: Shift right P 0010 0000 1011 01c:10=>P-M 0010 1110 1011 032: Shift right P 0010 1111 0101 11d:11=> no operation 0010 1111 0101 142: Shift right P 0010 1111 1010 1
Multiply by 2^i via shift
Shift left by one bit --> multiply by 2 Shift left by n bit --> multiply by 2^n Proof of Booth’s Algorithm
Why does it work for 2’s complement signed number?
In other words, if (ai-1 - ai) = 0 do nothing = 1 add b = -1 subtract b
Booth’s algorithm can be written as: (a-1 - a0) x b x 2^0+ (a0- a1) x b x 2^1 + …+(a30-a31)x b x 2^31 = … = b x a
ai ai-1 Operation 0 0 Do nothing 0 1 Add b 1 0 Subtract b 1 1 Do nothing
Multiply in MIPS
Use a pair of 32-bit registers to contain the 64-bit product, called Hi and Lo mult: signed multiplication multu: unsigned multiplication mflo: move from lo to fetch the integer 32-bit product mfhi
Both mult and multu ignore overflow! You must take care of this yourself in the software. How? Check the value of Hi Hi must be 0 for multu Hi must be the replicate sign of Lo for mult
Division
Some definitions:Dividend, Divisor, Quotient, Remainder
Dividend = Quotient X Divisor + Remainder Example: 1001010 divided by 1000 1001 QuotientDivisor 1000 1001010 Dividend –1000
10 101 1010 –1000 10 Remainder (or Modulo result)
First Version of the division hardware
64-bit ALU
Controltest
QuotientShift left
RemainderWrite
DivisorShift right
64 bits
64 bits
32 bits
Done
Test Remainder
2a. Shift the Quotient register to the left,setting the new rightmost bit to 1
3. Shift the Divisor register right 1 bit
33rd repetition?
Start
Remainder < 0
No: < 33 repetitions
Yes: 33 repetitions
2b. Restore the original value by addingthe Divisor register to the Remainder
register and place the sum in theRemainder register. Also shift the
Quotient register to the left, setting thenew least significant bit to 0
1. Subtract the Divisor register from theRemainder register and place the result in the Remainder register
Remainder > 0
Observations on the first version of the division hardware
1/2 bits in divisor always 0 1/2 of 64-bit adder is wasted 1/2 of divisor is wasted
Instead of shifting divisor to right, shift remainder to left?
1st step cannot produce a 1 in quotient bit (otherwise too big) switch order to shift first and then subtract, can
save 1 iteration
Second Version of the division hardware
Controltest
QuotientShift left
Write
32 bits
64 bits
32 bits
Shift left
Divisor
32-bit ALU
Remainder
Final Version of the division hardware
Write
32 bits
64 bits
Shift leftShift right
Remainder
32-bit ALU
Divisor
Controltest
Done. Shift left half of Remainder right 1 bit
Test Remainder
3a. Shift the Remainder register to the left, setting the new rightmost bit to 1
32nd repetition?
Start
Remainder < 0
No: < 32 repetitions
Yes: 32 repetitions
3b. Restore the original value by addingthe Divisor register to the left half of theRemainder register and place the sum
in the left half of the Remainder register.Also shift the Remainder register to theleft, setting the new rightmost bit to 0
2. Subtract the Divisor register from theleft half of the Remainder register andplace the result in the left half of the
Remainder register
Remainder 0
1. Shift the Remainder register left 1 bit
>
Signed Division
Remember signs of the divisor and dividend, negate the quotient if the signs disagree.
What about the sign of the remainder? Rule: Dividend and remainder must have
the same sign.
Division in MIPS
Same hardware can be used for both multiply and divide so long as we have a 64-bit register that can shift left or right and a 32-bit ALU that adds or subtracts.
Hi: contains remainder Lo: contains quotient div vs divu
Representing Real Numbers
We need a way to represent numbers with fractions, e.g., 3.1416 very small numbers, e.g., .000000001 very large numbers, e.g., 3.15576 x 109
Use normalized scientific notation Called floating point number because the binary point is not
fixed. Advantages:
simplifies data exchange simplifies floating point arithmetic algorithms increases accuracy
Floating Point Representation
Representation: sign, exponent, significand: (–1)sign x significand x2exponent
more bits for significand gives more accuracy
more bits for exponent increases range
IEEE 754 floating point standard: single precision: 8 bit exponent, 23 bit significand
double precision: 11 bit exponent, 52 bit significand
Need to worry about underflow, i.e., a number too small to be represented by floating point expression.
IEEE 754 floating-point standard
Leading “1” bit of significand is implicit Exponent is “biased” to make sorting easier
all 0s is smallest exponent all 1s is largest bias of 127 for single precision and 1023 for double precision summary: (–1)sign xsignificand) x2exponent – bias
Example: decimal: -.75 = -3/4 = -3/22
binary: -.11 = -1.1 x 2-1
floating point: exponent = -1+127 = 126 = 01111110 IEEE single precision: 10111111010000000000000000000
000
Converting Binary to Decimal Floating Point
1 1000001 01 0000…00 Sign bit =1 Exponent = 129 Significand = 1x2^-2 = 0.25 Decimal value = (-1)^1(1+0.25)x2^(129-12
7) =-5.0
Representing 0 in IEEE 754 standard
Smallest single precision normalized number
= 1.000000…00 x 2^(-126) Leading “1” bit of significand is implicit except for the value 0. Reserve exponent value 0 for zero so that the hardware won’t at
tach a leading 1 to it.
Exponent Significand Object represented
0 0 0
0 nonzero +- denormalized number
1-254 anything Floating point number
255 0 +- infinity
255 nonzero Not a Number (NaN)
Floating Point Addition
Decimal example: 9.999x10^1 + 1.610x 10^-1
Step 1: Align the decimal point Step 2: Add significands Step 3: Convert to normalized form, check
for underflow or overflow Step 4: Round the resulting significand
Floating-Point Addition
Done
2. Add the significands
4. Round the significand to the appropriatenumber of bits
Still normalized?
Start
Yes
No
No
YesOverflow orunderflow?
Exception
3. Normalize the sum, either shifting right andincrementing the exponent or shifting left
and decrementing the exponent
1. Compare the exponents of the two numbers.Shift the smaller number to the right until itsexponent would match the larger exponent
Block Diagram of Floating-Point Addition Unit
0 10 1 0 1
Control
Small ALU
Big ALU
Sign Exponent Significand Sign Exponent Significand
Exponentdifference
Shift right
Shift left or right
Rounding hardware
Sign Exponent Significand
Increment ordecrement
0 10 1
Shift smallernumber right
Compareexponents
Add
Normalize
Round
Floating-Point Multiplication
Example: 1.110x10^10x9.200x10^-5 Step 1: Add the exponent (then -127 since b
ias is counted twice) Step 2: Multiply the two significands Step 3: Normalized the result, check for und
erflow or overflow Step 4: Round the resulting significand Step 5: Determine the sign
Floating-Point Multiplication
2. Multiply the significands
4. Round the significand to the appropriatenumber of bits
Still normalized?
Start
Yes
No
No
YesOverflow orunderflow?
Exception
3. Normalize the product if necessary, shiftingit right and incrementing the exponent
1. Add the biased exponents of the twonumbers, subtracting the bias from the sum
to get the new biased exponent
Done
5. Set the sign of the product to positive if thesigns of the original operands are the same;
if they differ make the sign negative
Floating-Point Instructions in MIPS
Addition: add.s, add,d Subtraction: sub.s, sub.d Multiplication: mul.s ,mul.d Division: div.s, div.d Comparison c.x.s or c.x.d where x may be eq,
neq, lt, le, gt,ge Branch: bclt (branch true), bclf (branch false) Separate registers for floating-point operations
Floating Point Complexities
Operations are somewhat more complicated In addition to overflow we can have “underflow” Accuracy can be a big problem
IEEE 754 keeps two extra bits, guard and round four rounding modes positive divided by zero yields “infinity” zero divide by zero yields “not a number” other complexities
Implementing the standard can be tricky Not using the standard can be even worse
see text for description of 80x86 and Pentium bug!
Rounding with Guard Digits
Add 2.56x10^0 to 2.34x10^2, assuming we have 3 significant decimal digits
With guard and round bits: (2.3400 + 0.0256)
Without guard and round bits Guard Round
Fallacies and Pitfalls
Floating point addition is associative, i.e, x+(y+z) = (x+y)+zCounter example: -1.5x10^38+ (1.5 x10^38+1)
Right shit is the same as an integer division by a power of 2: true for unsigned integers.
Summary
Computer arithmetic is constrained by limited precision Bit patterns have no inherent meaning but standards
do exist two’s complement IEEE 754 floating point
Computer instructions determine “meaning” of the bit patterns
Performance and accuracy are important so there are many complexities in real machines (i.e., algorithms and implementation).