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Chapter 3_ C6713

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    Chng 3: Kt TMS320C6713

    Chng3: KIT TMS320C6713

    Hnh 3.1: Kt TMS320C6713 DSK

    3.1 Gi i thi u TMS320C67133.1.1 T ng quan v TMS320C6713

    Kit DSK l mt h thng DSP hon chnh. Board DSK bao gm b x l s du chm ng C6713 v b Codec 32-bit stereo TLV320AIC23 (gi tt lAIC23) cho vic xut nh p tn hiu. B codec on board AIC23 s dng k thutsigma-delta bin i A/D v D/A. N c k t ni v i mt ng hh thng 12MHz. Tn s ly mu c th thay i t 8 n 96 Khz.

    B x l Kt TMS320C6713 ca hng Texas Instrument da trn kintrc VLIW (very-long-instruction-word), ph h p cho cc gii thut nng v tnhton s. Bnh chng trnh ni c tchc mi chu k c thn p 8 lnh, milnh di 32 bt.

    Cc b x l C67xx (nh C6701,C6711 v C6713) thuc v h cc b x l C6x du chm ng, trong khi C62xx v C64xx thuc v h cc b x lC6x du chm tnh. C6713 c thx l c du chm tnh v du chm ng. Ccyu cu phn cng cao hn cng c th c p ng v i cc khe cm m r ng.

    S khi ca kt TMS320C6713 hnh 3.2 bn d i.

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    Chng 3: Kt TMS320C6713

    Hnh 3.2: S kh i C6713 DSK

    Thnh ph n chnh trn Kit Trung tm l chp x l tn hiu TMS320C6713, chy xung nh p

    225Khz, TMS320C6713 nm trong dng chp TMS320C6x ca TI, y l dng vix l tc cao, s dng kin trc c bit p ng cc tc v x l tn hiu.Da trn kin trc VLIW, TMS320C6713 c kh nng xl cc s thc du chmng v c coi l dng chp x l tn hiu mnh nht ca TI hin nay.

    Bbin i tn hiu AIC23. Bn cng k t ni tn hiu vo ra: MIC IN (Microphone input), LINEIN (line input), LINE OUT (line output) v HEADPHONE (headphoneoutput).

    Tr ng thi ca 4 led v Dip Switch trn DSK c th cu hnh iukhin theo nhu cu ca ng i s dng.

    Cng USB giao ti p v i PC. Trn cng cng c thit k b JTAGnhng gip ta c th sa li chng trnh chy trn chip m khng cn niJTAG ngoi.

    Cng PRW (+5V) cung c p ngun cho board. Cng ny cung cp in

    p +1.26V cho li chp C6713 v +3.3V nui bnh v cc thit b ngoivi khc. Bnh : +16MB

    +512 KB bnh Flash. B nh trong: trn mch c 264kB b nh trong (4 KB b m d

    liu L1D; 4KB b m chng trnh L1P; 256 Kb bnh L2).Di y l s phn vng v a ch bnh ca kt (hnh 3.3)

    B nh ngoi: kt DSP c sn 16Mb b nh ngoi (SDRAM(Synchronous Dynamic RAM )) + 512 KB b nh Flash. Ngoi ra kt c th b sung bnh ngoi qua khe cm m r ng. V i chiu di thanh ghi 32 bt,

    kt c thqun l 4GB bnh ngoi.

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    Chng 3: Kt TMS320C6713

    C thnhn thy r ng, tuy hot ng v i xung nhp khng cao nhng ktTMS320C6713 c dung l ng b nh lu trl n, kh nng x l duchm ng, c sn JTAG nhng thun tin cho debug v tnh nng xlth i gian thc RTDX, hon ton thch h p cho nhiu ng dng thc t.

    Hnh 3.3: S phn vng v a ch bnh

    3.1.2 Khi qut ch c nngCc thit b ngoi vi trn board TMS320C6713 DSK giao ti p v i nhau

    thng qua b nh ngoi EMIF (External Memory InterFace). SDRAM, Flash vCPLD c k t ni v i nhau thng qua bus trn board. Tn hiu t b nh ngoi

    EMIF c k t ni thng qua cc card m r ng, s dng trn nhng khe cm m r ng trn bo.Giao ti p x l tn hiu m thanhtng tthng qua chp AIC23 Codec

    v jack audio 3.5mm (microphone input, line input, line output, v headphoneoutput). C th s dng microphone hoc line input ly tn hiu u vo. Ng rat ng t c ly ra qua ng ra lineout, v headphone.McBSP0 c s dng gi dng lnh t i giao din iu khin Codec, vMcBSP1 c s dng cho vicm cc d liu m thanh. McBSP0 v McBSP1 c th ti k t ni t i cc k t nim r ng trong phn mm.

    Mt thit b logic l p trnh CPLD s dng thc hin x l logic v

    gn k t cc thnh phn khc trn board. CPLD c thanh ghi c s dng cho x llogic.

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    Chng 3: Kt TMS320C6713

    Trn DSK gm 4 n LED v 4 cng tt DIP cung cp ng i dng thaotc tc ng qua li. C hai u c thc hin bi c v ghi vo thanh ghi CPLD.

    S dng ngun cung c p +5V, trn bo c mch iu chnh in p cung cp in cp 1,26 V cho li DSP v 3.3 V cho cng I/O.

    Code Composer giao ti p v i DSK thng qua mt JTAG gi l p v i giaodin cng USB. Cc DSK cng c ths dng v i m phng bn ngoi thng quak t ni JTAG bn ngoi.

    3.1.3 Bnh S khi bnh C6713

    Hnh 3.4: S kh i C6713

    DSK s dng bn vng bnh ngoi: CE0: SDRAM CE1: Bnh Flash v cng I/O (switch, leds) CE2 v CE3: chn k t ni t i daughter card

    H C67xx c khng gian a ch byte nh l n. M ngun chng trnhv d liu c th c cha bt c ni no trn khng gian a ch vng nh. r ng a ch 32 bt.

    Bn sau m t vnga ch b x l 6713. Theo mc nh, b nh trong nm u vnga ch.

    EMIF c 4 vng a ch ring bit gi l chip cho php c khng gian(CE0 CE3). SDRAM chim gi CE0 trong khi Flash v CPLD l CE1, CE2 vCE3 dnh cho cc card con (Daughter Card).

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    Chng 3: Kt TMS320C6713

    Hnh 3.5: B n vng nh

    External SDRAMSDRAM (Synchronous DRAM)DSK s dng mt 64 megabit ng b DRAM (SDRAM) trn EMIF

    32-bit. SDRAM l nh x bt u t CE0 (a ch 0x80000000), tng b nh csn l 16MB.

    B iu khin SDRAM tch h p l mt phn ca EMIF v phi ccu hnh trong phn mm cho hot ng tt. Mt s cc thng s quan tr ng nht c lit k di y:

    Bng 3.1 cc thng s ca SDRAM Thng s Gi tr

    CE0 Memory Type 32-bit wide SDRAM Num. Banks 4 Num. Row Address Lines 12 Num. Column Address Lines 8Chu k lm m i tr ng thi 1400

    Mt trong nhng thng s SDRAM chnh l chu k refresh. SDRAMs phi c refresh lin tc hoc n s tr nn bt n v mt ni dung. Cc DRAM c s dng trn DSK C6713 phi refresh mt dng mi 15,6 micro giy. Cc cuhnh c hin th trn s dng mt gi tr ca 1400 (0x578 (hex)). Ch nh chuk refresh (1400 x 11.11ns, chu k clock 90MHz).

    Tc Refresh = 64 ms / 4096(64ms t ng refresh 4K)

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    Chng 3: Kt TMS320C6713

    External Flash DSK c 128K Flash Bnh khng linh ng, c l p trnh li S dng lu trd liu ban u Lu trcc hng s c s dng trong qu trnh thc thi

    Hnh 3.6: K t n i gi a EMIF v i Flash

    Flash l mt loi b nh m khng b mt ni dung khi ngun in c tt. Khi truy xut ging nh truy xut b nh ch c ROM. Flash c th b xa trong tng khi l n l sectors hay pages. Mi khi c xa thng qua chuilnh c bit trong l p trnh. Cc khi xa c thghi ni dung tr li.

    DSK mc nh l thm hai chu k vit cho tt c nhng b nh khngng b.

    B nh Flash DSK l b nh khng bay hi, mc d cho php ghi lini dung, nhng khng th c ghi mt cch d dng, m phi m kha (unlock) b i mt s lnh c bit.

    Write 0xAA to 0x5555Write 0x55 to 0x2AAAWrite 0xA0 to 0x5555Ghi d liu m i t i 128 byte sector. My tnh da vo cng c c sn

    ghi d liu t i flash. Chc nng BSL cho php vit t i Flash.

    3.1.4 Switch c u hnh kh i ng DSK c 4 Switch cu hnh cho php ng i s dng iu khin tr ng

    thi hot ng. Khi Switch cu hnh c nhn SW3 gn Switch Reset. SW1 dng

    iu khin endianness ca DSP, SW2, SW3 cu hnh ch boot khi bt u thcthi DSP.SW4 iu khin ghp knh trn chip ca HPI v tn hiu McASP a ra k t ni m r ng t i HPI m r ng.

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    Chng 3: Kt TMS320C6713

    Bng 3.2: B ng c u hnh cc Switch

    3.1.5 Ngu n cung c pDSK s dng tn hiu in p +5V c c p b i ngun cung c p thng

    qua u cm J5. Tn hiu ny c i qua b iu chnh in p bn trong board a ra tn hiu in p +1.26Vv +3.3V. in p +1.26V s dng cho cc li DSPv in p +3.3V s dng cho cc cng I/O v cc chp khc trn board. u cmngun l loi jack cm 2.5mm.

    kim tra mc in p, ta c th kim tra ti cc im JP1, JP2 vJP4. Tt c dng I/O u i qua JP2, v dng in li i qua JP1.Tt c dng inca h thng i qua JP4.

    u J6 c dng in p +12V v -12V, cung c p ngun cho ccDaughter Card.

    3.2 Ch c nng t ng thnh ph n trn bo TMS320C6713 DSK 3.2.1 TMS320C6713

    TMS320C6713 DSP hot ng tn s225MHz. Li ca DSP c thit k thc thi cc php ton du chm ng. Bn ngoi li, C6713 tchh p mt s ti nguyn trn chip ci tin chc nng v ti thiu ha phn cng pht trin phc t p.

    VLIW Core l kin trc ca b x l cho php thc hinnhiu lnh trn 1 xung clock (8 lnh trn 6713 DSP ). Kin trc VLIW c th t c mc x l cao nhng n t gnh nng nhiu hn vo trnh bin dch s p x p thc thi cng lc lnh.

    192Kbytes b nh ni B nh trong tc cao cho s thcthi ti a.

    64Kbytes L2 cache/RAM 4 khi 16Kbytes ca RAM ni cth c cu hnh nh RAM hoc cache.

    4Kb Program/Data caches cache ring r cho m lnhchng trnh v dliu.

    On-chip PLL pht ra xung clock b x l t ngun xungclock tham chiu bn ngoi.

    2 timers . EDMA controller b iu khin DMA nng cao cho php

    truyn ti d liu tc cao m khng cn s can thi p tDSP. 2 McBSPs cng ni tip m nhiu knh. Mi McBSP c th

    c dng cho vic truyn ti d liu ni ti p tc cao v i thit b bn ngoi hocl p trnh li nh l mc ch I/O chung. McBSP1 c s dng truyn v nhn

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    Chng 3: Kt TMS320C6713

    d liu m thanh t AIC23. McBSP0 c dng iu khin codec thng qua ngvo ni tip. Thanh ghi MISC trong CPLD c s dng chn khi no McBSP0v McBSP1 c ni v i AIC23 hoc nhng k t ni m r ng.

    2 McASPs Cng m thanh ni tip a knh. Sdng cho nhiuknh v nhngng dng m thanh chuyn nghi p. Khng s dng trn DSK, nhngmang li nhng k t ni m r ng.

    2 giao din I2C Bus I2C l bus ni ti p c thh tr mt vi thit b chuntrn bus.

    EMIF giao din b nh m r ng. Mt bus 32 bit trn b nh m r ng v thit b khc c th c k t ni. N bao gm tnh nng nh trng thi ch bn trong v iu khin SDRAM. Giao din EMIF bao gm c ng b vo d b bnh .

    DSP c thit k thc thi ti xung nh p 225MHz v i 50MHz t b daong bn ngoi. thc thi bnh th ng trn 6713 DSK, vng kha pha bn trong c cu hnh v i b nhn ca 9 v b chia ca 2 t c 225Mhz t nguntham chiu 50MHz.

    K t ni gia AIC23 v i McBSP0, McBSP1

    Hnh 3.7: K t n i AIC23 v i McBSP

    Cc thit b TMS320C67x cha ng cc thit b ngoi vi giaoti p v i bnh off-chip, ng bx l, bx l gia my ch v thit b niti p. Bx l C6713 gm c:

    Enhanced DMA (EDMA)Truy c p b nh tng c ng tr c ti p (EDMA_enhaced direct memory

    access) iu khin truyn ti d liu gia cc vng trong bng bnh khng quas can thi p ca CPU. EDMA cung c p truyn ti d liu t i/t bnh ni, thit b ngoi vi ni, thit b bn ngoi trong bi cnh hot ng ca CPU. EDMA c 16knh c lp trnh c l p cho php thao tc 16 hot ng khc nhau.

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    Chng 3: Kt TMS320C6713

    EDMA c th c v vit d liu c bn t vng ngun hoc vng chtng ng trong bnh. EDMA cng cung c p vic truyn ti khi hoc truyn tikhung. Mi knh EDMA s l ng lp trnh c l p ca cc yu t d liu trn 1khung v s l ng khung cho mi khi.

    EDMA c cc tnh nng sau: DMA hot ng c l p v i CPU.Thng l ng cao: Cc yu t c th c truyn ti cng v i tc

    xung clock ca CPU.16 knh: EDMA c th gi vic theo di, kim tra cc ng cnh ca

    vic truyn ti 16 knh.Tch hot ng: Mt knh n c ths dng truyn v nhn, truyn

    t/t i thit b ngoi vi v bnh .Lp trnh u tin: Mi knh c cc u tin lp trnh c l p so v i CPU.Mi knh a ch thanh ghi ngun v chc thc cc ch scu hnh

    cho truyn ti c v ghi.a ch c th khng i, tng, gim hoc c iu chnh b i gi tr

    l p trnh.Lp trnh thay i r ng truyn ti: Mi knh c th c cu hnh

    c lp truyn ti byte, 16 bt word, 32 bt word.Xc thc: Mi ln truyn ti hon tt, EDMA s t ng qu trnh kh i

    to chnh n cho ln truyn ti k ti p.Lin k t: Mi knh EDMA c th c lin k t t i truyn ti ti p theo

    sau khi truyn ti k t ti hon tt.S kin ng b: Mi knh c bt u b i mt s kin. Chuyn giao

    c th l ng bphn t hoc khung.EDMA gi tt c d liu truyn gia b nh m L2/ b nh iu

    khin, v thit b ngoi ngoi vi.EDMA c th di chuyn d liu t v t i bt k a ch vng nh no

    bao gm c bnh ni (L2 SDRAM), thit b ngoi vi, v bnh ngoi.B iu khin RAM bao gm s kin v x l ngt, s kin gii m,

    tham s RAM, v a ch phn cng.EDMA c 16 knh c l p v chng c th c ginh u tin. Sau khi s kin xut hin, n truyn ti bng c c t bng RAM

    (PaRAM).EDMA c th truyn ti 8 bit bytes, 16 bt 1/2words, hoc 32 bt words.Sau khi truyn ti, ngun v/hoc ch vyu t a ch c th ging

    nhau, cng tng, gim mt yu t, hoc tng gim b i gi tr trong thanh ghiELECXD cho knh.

    Sau khi chng trnh truyn ti k t thc, EDMA c th ti p tc chotruyn d liu b i link b i lin k t chng trnh t i knh khc.

    EDMA C6713 h tr 16 knh EDMA.

    o Thanh ghi x l s kin+ER (Event Register): khi s kin n c pht hin, bt n cci t vo trong EER.

    +EER (Event Enable Register): bt n c thit l p 1 cho phpx l s kin. Gi tr 0 th khng cho php.

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    Chng 3: Kt TMS320C6713

    +ECR (Event Clear Register): nu mt s kin c cho phptrong EER v c a ln ER, bt ER t ng xa v 0 khiEDMA x l truyn ti s kin. Nu s kin b v hiu ha,CPU c thxa bt c s kin trong ER.+ESR (Event Det Register): Gi tr 1 ch p nhn thit l p s kin, cho php CPU yu cu s dng cng c g li.

    Host Port Interface (HPI) Giao din Host-Port (HPI_Host-Port Interface) l port song song 16 bt

    thng qua bx l ch c th truy xut tr c ti p khng gian bnh CPU.Chc nng thit b my ch nh qun l giao din, tng ln ddng ca

    vic truy c p.My ch v CPU c th trao i thng tin thng qua b nh trong v

    ngoi.My ch c th truy c p vo bnh nh x thit b ngoi vi.

    HPI c k t ni t i bnh ni thng qua b thanh ghi.Hoc my ch hoc CPU c th s dng thanh ghi iu khin HPI(HPIC) cu hnh giao din. My ch c th truy cp thanh ghi a ch my ch (HPIA) v thanh ghi d liu ch (HPID) dng truy c p t i khng gian b nh nica thit b.

    Two Multichannel Audio Serial Ports (McASPs)B x l TMS320C6713 bao gm 2 cng m thanh ni tip a knh

    (McASP).M un giao din McASP h tr mt truyn mt nhn.

    Mi McASP c 8 chn d liu ni ti p, chng c th c nh r v trring l t i bt k ca 2 vng.Cng ni ti p h tr ghp knh phn chia th i gian trn mi chn t 2-

    32 khe th i gian.D liu ni ti p trn mi vng c th c truyn ti v nhn trn nhiu

    chn d liu ni tip ng thi trn nh dng I2S (Inter-IC Sound).Truyn ti McASP c th c l p trnh t i nhiu ng ra S/PDIF

    IEC60958, AES-3, CP-430 c m ha d liu nhiu knh ng th i, v i b nh RAM thc hin y cc d liu ngi dng v cc tr ng tr ng thi knh.

    McASP cng cung cp tnh nng kim tra li v khi phc.

    McASP gm McASP0 vMcASP1 2 m un c l p truyn v nhn.o Tnh nng McASP:

    Cho php truyn v nhn 2 tc khc nhau L p trnh to ra ng hv khung ng b Dng TDM t 2 n 32 v 383 slots time H tr kch c slot time ca 8,12,16,20,24,28 v 32 bt nh dng d liu cho cc thao tc bt Chn d liu ni ti p t i 16 chn H tr giao din truyn ti m thanh s Khe 384 TDM v i giao din m thanh sbn ngoi (DIR) M r ng kim tra li v phc hi

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    Chng 3: Kt TMS320C6713

    Two Multichannel Buered Serial Ports (McBSPs) C th to s dch chuyn xung clock v ng b khung tn

    hiu bn trong hoc s dng tn hiu bn ngoi. C th truyn hoc nhn 8, 12, 16, 20, 24, hoc 32 bt word.

    Thanh ghi d liu m i cho php lin tc dng d liu. C truyn truyn v nhn ngt t i CPU hoc s kin t iEDMA.

    Chn a knh t i 32 phn t t 128 phn t khung TDMA Giao din tr c ti p t i cc codec chun cng nghi p. S khi McBSP.

    Hnh 3.8: S khi McBSP DX/DR : Truyn/nhn d liu ni ti p FSX/FSR: Truyn /Nhn ng bkhung CLKX/CLKR: Truyn/Nhn xung dch chuyn ni ti p XINT/RINT: Truyn/nhn ngt t i CPU XEVT/REVTL: Truyn/nhn ngt t i DMA CLKS: Xung ngoi.

    Truy n d liu:p ng truyn ti d liu ni ti p t i ghi vo DXR. Ni dung ca

    DXR c sao chp t i thanh ghi XRS. Bt u truyn ti ngay khi ng b khung (FSX) c tm thy. Mt bt ca d liu c truyn ti c dchchuyn ra khi SXR trong 1 xung truyn CLKX. D liu m i c th c ghi t iDXR s dng CPU hoc DMA.

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    Chng 3: Kt TMS320C6713

    Hnh 3.9: Qu trnh truy n d liu

    Thanh ghi iu khin port ni ti p (018C0008H )

    XINTM XEMPTY XRDY XRST RJUST RINTM RFULL RRDY RRST

    Thao tc truyn ni ti p: CPU hoc EDMA ghi mt t vo trong thanh ghi truyn d liu

    (DXR_Data Transmit Register). C XRDY c xa bt k khi nod liu c vit t i DXR.

    Sau khi mt t (32 bt) c dch ra ngoi thanh ghi XSR, s ctruyn ti song song vo trong XSR. C XRDY s c thit l p khixut hin truyn ti.

    Truyn ti cng ni ti p gi mt yu cu ngt (XINT) t i CPU khiXRDY chuyn t 0 ln 1 nu XINTM=00b vo trong SPCR. N gi

    tn hiu XEVT (Transmit Event Notice) t i EDMA.Nh n d liu:D liu nhn trn chn DR c dch vo trong thanh ghi RSR (Receive Shift Register) trong mi xung clock nhn (CLKR). D liutrong RSR c sao chp t i Recevice Buffer Register (RBR) v sau t i DRR (Data Receive Register). DRR c th c c b i mtCPU hoc DMA.S khi qu trnh nhn d liu:

    Hnh 3.10: Qu trnh nh n d liu

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    Chng 3: Kt TMS320C6713

    Thao tc nhn ni ti p: Bt RX c dch vo trong RSR (Receive Shift Register). Khi tt c c bt c nhn, 32 bt RSR c truyn song

    song ti thanh ghi m nhn (RBR-Receive Buffer Register)nu n r ng.

    RBR sao chp t i DRR (Data Receive Register) nu n r ng. Bt RRDY trong SPCR c thit l p ln mc 1 khi RSR cdi chuyn ti DRR, v n c xa v 0 khi DRR c c.

    Khi RRDY chuyn t 0 t i 1, McBSP pht t i CPU 1 yu cungt (RINT) nu RINTM=00b trong SPCR. Mt s kin nhn(REVT) c gi ti iu khin EDMA.

    To ra t c mu : Nh tn gi ca n, m un ny pht ratn hiu iu khin ging nh xung clock truyn/nhn v tn hiu ng b khung khi cn thit cho vic truyn ti d liu t i v t McBSP.Mch to xung clock cho php ng i s dng chn la clock CPU

    hoc ngun ngoi thng qua CLK t i pht ra CLKR/X. Thuc tnhtn hiu ng b khung ging nh chu k khung v r ng khung c l p trnh. FSR/X, CLKR/X l chn 2 chiu, v v th c th lu vo v u ra.

    To ra s kin/ngt: McBSP to ra s kin ng b t i DMA,cho bit d liu d liu c sn sng trong DRR hoc DXR l snsng cho d liu m i. Chng c c s kin ng bREVT, v ghis kin ng b XEVT. Tng tCPU c th c/vit ti McBSP cnc vo ngt (RINT v XINT).

    Two 32-Bit General Purpose TimersC62x/C67x c hai b nh th i 32 bt general-purpose c th

    c s dng : Time event Count event To xung Ngt CPU Gi s kin ng b t i b iu khin DMA. B nh thi c u vo l chn TINP, u ra l chn TOUT.

    Chn TINP c th c s dng thu u vo general-purpose,v u ra nh u ra general-purpose.Khi xung ni c cung c p, b nh th i kh i to m, kch hot

    cc thit b ngoi vi nh iu khin DMA hoc chuyn i A/D tng ng. Khixung ngoi c c p, b nh th i kh i to m cc s kin bn ngoi v ngt CPUsau mt s s kin c qui nh.

    3.2.2 CPLDC6713 DSK dng Altera EMP3128TC100-10 CPLD thc thi: 4 thanh ghiiu khin/ tr ng thi vng nh cho php phn

    mm iu khin nhiu im trn board. iu khin giao ti p daughter card v tn hiu. K t ni cc thnh phn ca board li v i nhau.

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    Chng 3: Kt TMS320C6713

    c im ca thit b: EPM3128TC100-10 c in p hotng l 3.3V (c th chu c 5V), 100 chn cho php cung c p 128 macrcells vln n 80 chn I/O v i th i gian tr l 10ns t chn chn. Thit b da trnEEPROM v l c th l p trnh trn h thng thng qua giao din JTAG (10 chnu trn DSK). T p tin ngun CPLD c vit theo chun cng nghi p VHDL.

    Thanh ghi CPLDThanh ghi CPLD cho php ngi dng iu khin chc nng

    CPLD trong phn mm. Trn KIT 6713 DSK thanh ghi c s dng chnh chovic truy cp cc LED v DIP switch v iu khin card daughter. Thanh ghi l nhx trong CE1 ca EMIF ti khng gian a ch 0x90080000, l thanh ghi 8 bit btng b.

    Bng 3.3 : nh ngha thanh ghi CPLD

    Thanh ghi USER_REG USER_REG c dng c tr ng thi 4 DIP Switch v tr v4LED On hoc Off.Cc DIP switch c c b i 4 bit cao v vit b i4 bt th p ca thanh ghi.

    Bng 3.4: Thanh ghi USER_REG

    Thanh ghi DC_REG DC_REG c s dng iu khin, gim st daughter card. N d tm

    s c mt ca daughter card. DC_STAT v DC_CNTL cung c p giao tip n gin

    vi daughter card qua ng tr ng thi c v ng iu khin vit. DC_RST cths dng t li (reset) card.

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    hiu tng t trn ng tn hiu ra v headphone, v vy ng i dng c th nghethy m thanh.

    B codec giao ti p s dng 2 knh ni tip, 1 n iu khin thanh ghicu hnh bn trong ca codec v 1 n gi v nhn mu m thanh s. AIC23 h tr tr ng thi cu hnh khc nhau mnh hng n nh dng ca d liu ca knh d liu v knh iu khin, nhng tm tt d i y l bn ci t c a thch hncho 6713 DSK, nhiu m t chi tit hn c cho pha d i.

    Control channel : McBSP0, SPI v i xung ni v frame ng b.Data channel : MCBSP1, AIC23 trong ch chnh v i 12MHz xung

    clock.

    Hnh 3.11: AIC23 Codec

    Knh iu khi n m ha gi i m6713 DSK s dng McBSP0 nh l knh iu khin bm ha v gii

    m. Ch SPI l mt dng truyn d liu n gin v c s dng b i nhiu thit b cho giao tip c bn. Lc th i gian ch SPI nh sau:

    Hnh 3.12 Lc th i gian ch SPI McBSP c k t ni n bm ha v gii m nh sau:

    Bng 3.7: K t n i McBSP v i bm ha, gi i mMcBSP0 AIC23

    FSX Transmit Frame Sync LRCIN Left-Right Clock inputCLKX Data Clock BCLK Data Clock DX Transmit Data DIN Receive Data

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    Knh d liu m ha gi i mKnh d liu c dng truyn v nhn d liu m thanh n

    AIC23. 6713 DSK dng McBSP1 nh l knh dliu. Ch DSP l ch ngin ni m schuyn i tr ng thi t cao xung th p ca LTCIN bt u hotng. D liu 32 bit, gm 16 bit cho knh phi v 16 bit cho knh tri. Th i gianch DSP nh sau:

    Hnh 3.13 Th i gian ch DSP

    McBSP c k t ni n AIC23 nh sau:

    Bng 3.8: McBSP k t ni n AIC23McBSP1 AIC23FSX Transmit Frame Sync LRCIN Left-Right Clock inputFSR Receive Frame Sync LRCOUT Left-Right Clock outputCLKX Data Clock BCLK Data Clock DX Transmit Data DIN Receive DataDR Receive Data DOUT Transmit data

    Thanh ghi CodecAIC23 c10 thanh ghi iu khin chc nng nh m lng, nh dng

    d liu, tc ly mu v ch nng l ng thp. Thanh ghi c vit thng quaknh iu khin McBSP0.

    Bng 3.9 thanh ghi Codec

    Ly mu t t i codec

    Gi tr 32 bit c gi t i codec b i hm DSK6713_AIC23_write ().Hm ny:

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    Xt c MsBSP1 XRDY v tr v gi tr tc th i ca n, nu l False (0)v c tr vgi tr 0 v khng gi mu.

    Nu l True (1) th gi mu xung SXR ca McBSP1 v tr vgi tr 1. Ly mu t codec c t codec b i hm DSK6713_AIC23_read(). Hm ny:

    Xt c RRDY ca McBSP1 v tr v gi tr tc th i, nu l False thkhng c gi tr v tr vgi tr false.

    Nu l true th c gi tr 32 bt t DRR ca McBSP1 v tr vgi tr True (1).

    3.2.4 LED v Switch

    Hnh 3.14 V tr LED v SWITCH

    DSK c tm n LED to thnh t bn ch s tr ng thi v bn ndng xc nh User LED. Cc ch s c biu hin bi cc n bn cnh DIPSwitches.

    User LEDs :S dng 4 LED iu khin cho php cc thng tin phn hi ca ng i

    dng v hin th cc thng tin tr ng thi n gin. H c iu khin bng bngcch vit vo thanh ghi CPLD USER_REG. H cng c ththit l p xa thng qua

    LED Module ca Bo Support Library.Ch s tr ng thi:Cc ch s theo di tr ng thi cc chc nng.n LED PWR l mch in c ngun cung c p 5V, s c sng khi

    c k t ni.n RESET LED sng khi c skin RESET.n LED USB_IN_USE sng khi chy m phng USB v tt khi a

    chy thc ngoi.n USB BUSY LED ssng khi vic truyn ti qua USB ang tin

    hnh.

    Cc Dip Switch s dngBn thit b chuyn mch DIP cho php phn hi t ng i s dng.DIP Switches c th c thng qua thanh ghi CPLD USER_REG. DIP

    Switch c th c bng cch s dng module DIP Switch ca Bo Support Library. Switch c u hnh

    6713 DSK c 4 Switch cu hnhcho php ng i s dng kim sottnh tr ng DSP khi n Reset. Cc khi cu hnh switch c nhn SW3 trn bngDSK, bn cnh cc nt reset.

    Cu hnh Switch1 iu khin DSP, trong khi Switch 2 v 3 cu hnh

    ch khi ng, s c s dng khi bt u thc hin DSP. Switch 4 xc nh tn

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    hiu HPI hoc McASP a ra trn chn share. Ci t cu hnh mc nh ccSwitch u off.

    Bng 3.10: C u hnh Switch

    HPI Expansion InterfaceDSK cung c p ba k t ni m r ng c th c s dng ch p nhn

    mt u cm kiu daughtercard. Daughtercard cho php ng i s dng xy dngtrn nn tng DSK ca h m r ng kh nng v cung c p cc ty chnh vngdng I/O. Cc k t ni m r ng l b nh , thit b ngoi vi v Host Port Interface(HPI). bit thm thng tin c th tm thm v i t kha 6713 DSK Technical

    Reference .Bnh , thit b ngoi vi v Host Port Interfaces.

    Cc k t ni b nh cho php truy cp khng ng b t i EMIF caDSP giao ti p t i bnh v thit b nh x bnh . Cc k t ni ngoi vi s a ratn hiu ngoi vi ca DSP nh McBSPs, timers v clocks. C hai k t ni cung c pngun v mass t i daughtercard.

    3.2.5 JTAG EmulatorCung c p JTAG debug tc cao thng qua giao ti p cng USB.JTAG c p t i mt b quy tc c thit k bao gm kim tra, l p

    trnh v g li ca chip. Giao din JTAG cho php ng i dng kim tra tn hiu vng k vo mt con chip thng qua mt giao din bn ngoi m ch s dng nmchn thm trn chip. Trong mt mi tr ng pht trin DSP TI Code Composer s dng giao din JTAG g r i ch ng trnh khng xm nh p thng qua mt thit b phn cng gi l JTAG gi l p.

    B gi l p nhng USB ( Embedded USB Emulator ): Giao ti p v i PCthng qua giao din tng thch USB 1.1. USB port PinOut:

    Bng 3.11: USB port PinOut

    Tn Chn S dng M t 1 USB VDD p ng ra USB

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    2 D+ Data +3 D- Data -4 USB VSS Ni t5 Vbc (shield) Cp vbc6 Vbc (shiled) Cp vbc

    H thng n led TMS320C6713 DSK c 4 n led hthng.

    Bng 3.12: H thng n led Tham chiu Mu Chc nng Tr ng thi ON

    D4 Xanh l cy Gi lp USB c s dng.Khi gi l p JTAG ngoic dng th n tt

    1

    D3 Xanh l cy +5V 1D6 Cam Ch RESET 1

    DS201 Xanh l cy Ch USB, truyn ti d liu thng qua cng USB

    1

    3.3 H ng d n s dng ph n m m Code Composser Studio ng dng Code Composser Studio (CCS) cung c p nhng tnh nng:

    Mi tr ng bin t p, g li, qun l cc project, H tr bin dch, ng gi cc chng trnh vit v i ngn ngC/C++ M phng H thng hot ng th i gian thc (DSP/BIOS) Trao i d liu th i gian thc gia host v i target. Phn tch th i gian thc

    3.3.1.1 Ci t ph n c ng v ph n m m Ph n m m: Ci t chng trnh CCS vo my, qu trnh ci t

    tng t nh ci t cc phn mm khc. Qu trnh ci t thnhcng sc 2 Shortcut trn Desktop

    6713 DSK CCStudio v.3.1: Vit Code n p cho Kit DSP. 6713 DSK Diagnostics Utility v3.1 Chng trnh chun on kim tra li Kit

    Ph n c ng :+ C p ngun 5V cho Kit DSP, s thy n LED bo hiu in p.

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    + Gn cp USB k t ni tKit DSP ln my tnh qua cng USB. Test KIT

    Click Icon 6713DSK Diagnostc Unity v3.1

    Hnh 3.15 Giao di n ki m tra DSK

    3.3.2 K t n i

    Khi ng CCS Click Nu s dng phin bn 3.1 th khng hin th icon k t ni, ta phi

    thc hin k t ni. Menu Debugg/Connect Nu thnh cng sxut hinIcon k t ni pha cui bn tri mn hnh CCS.

    Hnh 3.16: Giao di n chnh CCS

    3.3.3 M Project tn t i Project/ Open

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    Hnh 3.17 : m Project 3.3.4 Load v Run Project

    Hnh 3.18: load v run project Chn File .out trong th mc Debug, chn Open, chng trnh sload t i DSK

    Hnh 3.19: run chng trnh

    Dng chng trnh ang chy trn DSK C6713, Debug/ Halt (Shift + F5hoc icon )

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    Hnh 3.20: d ng (haft) m t chng trnh

    Thit lp ng dn th mc IncludeProject -> Build Options ->[Compiler tab] ->[Preprocessor category]

    Hnh 3.21 Thi t l p ng d n th mc Include

    Thit l p Mem modemi memory modem:data=far

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    Hnh 3.22: Thi t l p Mem modem

    3.3.5 To Project m iTo Project v vit codeTo Project m i : Project/ new, chn Target ng vi dng KIT ang

    dng TMS32C67xx

    Hnh 3.23 : ch n target

    Vit code C (.c):File->New->Source File, vit code chng trnh y.

    Lu vo vo th mcFile->Save Lu vo cng th mc trn, file .c (file bt.c)

    Thm file .c vo Project:

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    Project->Add Files to Project Thm file .c m i to vo (bt.c)

    Hnh 3.24 C a s vi t Code

    Thm m t s file c n thi tProject->Add Files to Project Nh p phi voInclude , chn Add files to Project

    Hnh 3.25 Thm file vo project

    Thm tt c file dng trong on chng trnh vo:"tonecfg.h", "dsk6713.h","dsk6713_aic23.h"Tng t, nh p phi vo Libraries, chn Add files to Project, Add file

    dsk6713bsl.lib.

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    Hnh 3.26: thm file vo project

    3.3.6 Built v RunQu trnh built mt ng dng tr i qua trnh t nh hnh ..

    Hnh 3.27 Trnh t xy d ng (built) m t ng d ng Built project : Project Rebuild All,

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    Hnh 3.28: C a s built project Nu thnh cng, t p tin.out s c to ra.

    3.3.7 V th trong CCS Chng ta c th v th ca tn hiu trong min tn s v

    min th i gian s dng CCS. Gi s c on code sau, v cn hin th dng sngkhi thc thi chng trnh vi on code .

    #include "DSK6713_AIC23.h"Uint32 fs=DSK6713_AIC23_FREQ_8KHZ; //Tn s ly mushor output_buffer [256];const short BUFLEN = 256;int index = 0;

    void main(){

    short sample_data;comm_poll(); //init DSK, codec, McBSPwhile(1) //infinite loop

    {sample_data = input_sample(); //sample inputoutput_buffer[index] = sample_data; //copy of the dataindex++;index = index%BUFLEN; //if index is greater than BUFLEN

    // reinitialize it to zerooutput_sample(sample_data); //output sample

    }}

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    Nhn xt, th s c v ra theo bin output_buffer. V th. Trong ca sCCS, chn View Graph Time/Frequency.

    Hnh 3.29: Thi t l p th hin th trong mi n th i gian

    Hnh 3.30: Thi t l p th hi n th trong mi n t n s

    3.3.8 Mo s a m t s li thng th ngThit l p thuc tnh BuiltProject Build OptionsChn Target Version: C671x

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    Mo s a li file: during linking

    Hnh 3.33: s a l i during linking

    Vn ny do sai ng dn trong include th vin trong thuc tnhlinker.

    Sa li ny: Ta remove 3 file: rts6700.lib, DSK6713bsl.lib, andcsl6713.lib t linker options v thm th cng bng cch add file theo ng dn(Project -> Add files toProject)

    Hnh 3.34: thi t l p thu c tnh linker

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    3.4 Kh o st m t s ng d ng c a Kt TMS320C6713

    Stater Kit TMS320C6713 c ccng dng trong nhng lnh vc sau: Truyn thng:Modem in thoi, FAX, cc t bo in thoi,

    mng khng dy, loa in thoi, my tr l i,. m thanh/ting ni: Voice mail, sha v nn m thanh ting

    ni, kim tra speaker, tng h p m thanh. T ng: iu khin ng c,dng hot ng, chun on h

    thng H thng iu khin: H thng iu khin servo trong a,

    iu khin my in laser, iu khin robot, iu khin m t v ng c, cng c iu khin my t ng.

    Trong qun i: X l tn hiu raa v tn hiu tu ngm, h thng nh v tn la, modem pht tn s radia HF, m bo khong r ng ca ph v m bo ting ni.

    Y hc: Thit b tr thch,nh MRI (nh ch p s dng cngh ng),nh siu m, gim st bnh nhn..

    Thit b o c: Phn tch ph, to tn hiu. X l nh: HDTV, nng cao cht l ngnh, xoay 3 chiu v

    hot hnh.Di y l mt s ng dng:

    3.4.1 To tn hi u sng Sin3.4.1.1 Lu gii thu t

    Main()

    Khoi tao thu vien ho troDSK6713_init()

    Kich hoat Codec AIC23

    Gui bang tin hieu ra output

    Gui bang tin hieu ra output

    Sample < Sin_table_size

    Xuat mau hien tai ra ngo ra

    End

    Sample ++

    no

    yes

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    3.4.1.2 Code chng trnh pht ra dng sng Sine f=1KHz

    #include "dsk6713.h"#include "dsk6713_aic23.h"#define SINE_TABLE_SIZE 48

    /* Ci t c u hnh Codec */ DSK6713_AIC23_Config config = {0x0017, // 0 DSK6713_AIC23_LEFTINVOL Left line input channel volume0x0017, // 1 DSK6713_AIC23_RIGHTINVOL Right line input channel volume0x00d8, // 2 DSK6713_AIC23_LEFTHPVOL Left channel headphone volume 0x00d8, // 3 DSK6713_AIC23_RIGHTHPVOLRight channel headphone volume0x0011, // 4 DSK6713_AIC23_ANAPATH Analog audio path control0x0000, // 5 DSK6713_AIC23_DIGPATH Digital audio path control0x0000, // 6 DSK6713_AIC23_POWERDOWN Power down control0x0043, // 7 DSK6713_AIC23_DIGIF Digital audio interface format0x0001, // 8 DSK6713_AIC23_SAMPLERATE Sample rate control0x0001 // 9 DSK6713_AIC23_DIGACT Digital interface activation};

    /* Bng gi tr 48 m u sng sin */ Int16 sinetable[SINE_TABLE_SIZE] = {

    0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c

    }; /* Hm main */ void main(){

    DSK6713_AIC23_CodecHandle hCodec;Int16 sample;

    /* Hm h tr cho th vin hm */ DSK6713_init();

    /* Start the codec */ hCodec = DSK6713_AIC23_openCodec(0, &config);

    for (sample = 0; sample < SINE_TABLE_SIZE; sample++){

    /* G i mt m u t i knh tri */ while (!DSK6713_AIC23_write(hCodec, sinetable[sample]));

    /* G i mt m u t i knh ph i */ while (!DSK6713_AIC23_write(hCodec, sinetable[sample]));

    } /* Close the codec */

    DSK6713_AIC23_closeCodec(hCodec);}

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    3.4.1.3 Hnh nh d ng sng

    Hnh 3.35: Hnh nh d ng sng Sine

    3.4.2 To tn hi u sng tam gic 3.4.2.1 C s tnh ton

    T chng trnh sngsin trn ta ch thay i 48 mu gi tr gn cho bin sinetable [SINE_TABLE_SIZE], thnh 48 mu mi ng vi dng sngtamgic v i cch tnh tonnh sau:

    Ta c 48 mu cho ton chu k T vy T l 24 mu nhng do dngsng c tnh cht i xng nn ta c th tnh trong T, th c 12 mu

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    u tin. tnh khong mu cho xung tam gic ta tnh nh sau:( d tnh ton ta i v s thp phn).

    Ta tnh cho na chu k u (dng). 7ffd h = 7x163 + 15x162 + 15x161 + 13x160 = 32765. 0000 h = 0.T gi tr cc i trn tnh n gi tr cc tiu ny l

    12 khong nn chia cho 12. Khong gi tr gia cch mu: 2730

    12

    032765

    V sng dng tam gic l hm tuyn tnh nn ta tnh c12 gitr trong T l nh sau:

    Gi tr mu 12 l 32760 32765 =7ffd h. T tip theo ta ly i xng qua t gi th cc i.

    Ta tnh cho na chu k sau (m). 8002 h = 8x163 + 0x162 + 0x161 + 2x160 = 32770. L gi tr cc

    tiu nh nht. ef4c h = 14x163 + 15x162 + 4x161 +12x160 = 61260. T gi tr

    cc tiu tnh n gi tr ny l 12 khong nn chia cho 12. Khong gi tr gia cch mu: 2730

    12

    032770

    V sng dng tam gic l hm tuyn tnh nn ta tnh c 12 gitr trong T l ly gi tr cc tiu cp s cng vi s gia l 2730c nh sau:

    STT 1 2 3 4 5 6 7 8 9 10 11 12S

    t/phn 32770 35500 38230 40960 43690 46420 49150 51880 54610 57340 60070 62800

    SHex 8002h 8aach 9556h a000h aaaah b554h bffeh caa8h d552h dffch eaa6h f550h

    Gi tr mu 12 l 62800 ta ly gi tr ny l 0 = 0000h. Ttip theo ta ly i xng qua t gi th cc i.

    3.4.2.2 Code chng trnh

    Tng t on chng trnh sng sin ta chthay gi tr bngInt16 sinetable[SINE_TABLE_SIZE] thnhInt16 tamgiactable[SINE_TABLE_SIZE], v i gi tr nh sau:

    Int16 tamgiactable[ SINE_TABLE_SIZE] ={

    0x0000 , 0x0aaa , 0x1554 , 0x1ffe , 0x2aa8 , 0x3552 ,0x3ffc , 0x4aa6 , 0x5550 , 0x5ffa , 0x6aa4 , 0x754e ,0x7ffd , 0x754e , 0x6aa4 , 0x5ffa , 0x5550 , 0x4aa6 ,0x3ffc , 0x3552 , 0x2aa8 , 0x1ffe , 0x1554 , 0x0aaa ,0x0000 , 0xf550 , 0xeaa6 , 0xdffc , 0xd552 , 0xcaa8 ,0xbffe , 0xb554 , 0xaaaa , 0xa000 , 0x9556 , 0x8aac ,0x8002 , 0x8aac , 0x9556 , 0xa000 , 0xaaaa , 0xb554 ,0xbffe , 0xcaa8 , 0xd552 , 0xdffc , 0xeaa6 , 0xf550

    STT 1 2 3 4 5 6 7 8 9 10 11 12S

    t/phn 2730 5460 8190 10920 13650 16380 19110 21840 24570 27300 30030 32760

    SHex 0aaah 1554h 1ffeh 2aa8h 3552h 3ffch 4aa6h 5550h 5ffah 6aa4h 754eh 7ffdh

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    };

    3.4.2.3 Hnh nh d ng sng

    Hnh 3.36: Hnh nh d ng sng tam gic3.4.3 ng d ng dng sw l a ch n d ng sng ng ra (sin, vung, tam gic)

    3.4.3.1 Code chng trnh #include "tonecfg.h"#include "dsk6713.h"#include "dsk6713_aic23.h"#include "dsk6713_led.h"#include "dsk6713_dip.h"

    #define TABLE_SIZE 48 //chieu dai bang song sinDSK6713_AIC23_Config config = { /* cau hinh codec */0x0017, 0x0017, 0x00d8, 0x00d8, 0x0011, 0x0000, 0x0000,0x0043, 0x0001, 0x0001 };

    Int16 sinetable[TABLE_SIZE] = { // Bng gi tr sng sin 0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c

    };Int16 squaretable[TABLE_SIZE] = { // Bng gi tr sng vung 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd,0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd,0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x7ffd , 0x8001,0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001,0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001,0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001 , 0x8001

    };Int16 triangletable[TABLE_SIZE] = { // Bng gi tr sng tam gic

    0x0000, 0x0aaa, 0x1554, 0x1ffe, 0x2aa8, 0x3552, 0x3ffc, 0x4aa6,0x5550, 0x5ffa, 0x6aa4, 0x754e, 0x7ffd, 0x754e, 0x6aa4, 0x5ffa,0x5550, 0x4aa6, 0x3ffc, 0x3552, 0x2aa8, 0x1ffe, 0x1554, 0x0aaa,

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    Chng 3: Kt TMS320C6713

    0x0000, 0xf550, 0xeaa6, 0xdffc, 0xd552, 0xcaa8, 0xbffe, 0xb554,0xaaaa, 0xa000, 0x9556, 0x8aac, 0x8002, 0x8aac, 0x9556, 0xa000,0xaaaa, 0xb554, 0xbffe, 0xcaa8, 0xd552, 0xdffc, 0xeaa6, 0xf550};

    Int16 out_sample[TABLE_SIZE];

    void main(){DSK6713_AIC23_CodecHandle hCodec;Int16 i, sample;

    DSK6713_init();DSK6713_LED_init();DSK6713_DIP_init();hCodec = DSK6713_AIC23_openCodec(0, &config);

    while (1){if (DSK6713_DIP_get(0) == 0)

    {for (i=0;i

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    Chng 3: Kt TMS320C6713

    DSK6713_LED_off(3);for (sample = 0; sample < TABLE_SIZE; sample++){

    while (!DSK6713_AIC23_write(hCodec, out_sample[sample]));while (!DSK6713_AIC23_write(hCodec, out_sample[sample]));

    }

    }else if (DSK6713_DIP_get(3)==0){

    DSK6713_LED_on(0);DSK6713_waitusec(200000);DSK6713_LED_off(0);DSK6713_waitusec(200000);

    DSK6713_LED_on(1);DSK6713_waitusec(200000);DSK6713_LED_off(1);DSK6713_waitusec(200000);

    DSK6713_LED_on(2);DSK6713_waitusec(200000);DSK6713_LED_off(2);DSK6713_waitusec(200000);

    DSK6713_LED_on(3);DSK6713_waitusec(200000);DSK6713_LED_off(3);DSK6713_waitusec(200000);DSK6713_LED_off(3);DSK6713_LED_off(0);DSK6713_LED_off(1);DSK6713_LED_off(2);

    DSK6713_LED_on(0);DSK6713_waitusec(200000);DSK6713_LED_on(1);DSK6713_waitusec(200000);DSK6713_LED_on(2);DSK6713_waitusec(200000);DSK6713_LED_on(3);DSK6713_waitusec(200000);

    }else

    { DSK6713_LED_on(3);DSK6713_LED_off(0);DSK6713_LED_off(1);DSK6713_LED_off(2);

    }}}

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    3.4.3.2 Hnh nh th c nghi m

    Hnh 3.37: D ng sng ra khi l a ch n SW


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