Chapter 3 Digital Logic Structures

Chapter 3Digital LogicStructures

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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

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Transistor: Building Block of ComputersMicroprocessors contain millions of transistors

• Intel Pentium II: 7 million• Compaq Alpha 21264: 15 million• Intel Pentium III: 28 million

Logically, each transistor acts as a switch

Combined to implement logic functions • AND, OR, NOT

Combined to build higher-level structures• Adder, multiplexor, decoder, register, …

Combined to build processor• LC-2

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Simple Switch CircuitSwitch open:

• No current through circuit

• Light is off

• Vout is + 5V

Switch closed:• Short circuit across switch

• Current flows

• Light is on

• Vout is 0V

Switch-based circuits can easily represent two states:on/off, open/closed, voltage/no voltage.

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LOGICAL AND:

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N-type MOS TransistorMOS = Metal Oxide Semiconductor

• two types: N-type and P-type

N-type• when Gate has positive voltage,

short circuit between #1 and #2(switch closed)

• when Gate has zero voltage,open circuit between #1 and #2(switch open)

Gate = 1

Gate = 0

Terminal #2 must beconnected to GND (0V).

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P-type MOS TransistorP-type is complementary to N-type

• when Gate has positive voltage,open circuit between #1 and #2(switch open)

• when Gate has zero voltage,short circuit between #1 and #2(switch closed)

Gate = 1

Gate = 0

Terminal #1 must beconnected to +2.9V.

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Logic GatesUse switch behavior of MOS transistorsto implement logical functions: AND, OR, NOT.

Digital symbols:• recall that we assign a range of analog voltages to each

digital (logic) symbol

• assignment of voltage ranges depends on electrical properties of transistors being used

typical values for "1": +5V, +3.3V, +2.9V from now on we'll use +5V

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CMOS CircuitComplementary MOS

Uses both N-type and P-type MOS transistors• P-type

Attached to + voltagePulls output voltage UP when input is zero

• N-typeAttached to GNDPulls output voltage DOWN when input is one

For all inputs, make sure that output is either connected to GND or to +,but not both!

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Inverter (NOT Gate)

In Out

0 V 2.9 V

2.9 V 0 V

In Out

0 1

1 0

Truth table

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NOR Gate

A B C

0 0 1

0 1 0

1 0 0

1 1 0

Note: Serial structure on top, parallel on bottom.

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OR Gate

Add inverter to NOR.

A B C

0 0 0

0 1 1

1 0 1

1 1 1

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NAND Gate (AND-NOT)

A B C

0 0 1

0 1 1

1 0 1

1 1 0

Note: Parallel structure on top, serial on bottom.

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AND Gate

Add inverter to NAND.

A B C

0 0 0

0 1 0

1 0 0

1 1 1

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Basic Logic Gates

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Fundamental Properties of boolean algebra:Commutative: X + Y = Y + X X . Y = Y . XAssociative: ( X + Y) + Z = X + (Y + Z) ( X . Y) . Z = X . (Y . Z)Distributive: X . (Y + Z) = (X . Y) + (X . Z)X + (Y . Z) = (X + Y) . (X + Z)Identity:X + 0 = XX . 1 = XComplement:X +X’ = 1X . X’ = 0

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X+1

X+0

X.X

X.1

X.0

X+XY

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More than 2 Inputs?AND/OR can take any number of inputs.

• AND = 1 if all inputs are 1.• OR = 1 if any input is 1.• Similar for NAND/NOR.

Can implement with multiple two-input gates,or with single CMOS circuit.

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PracticeImplement a 3-input NOR gate with CMOS.

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Logical CompletenessCan implement ANY truth table with AND, OR, NOT.

A B C D

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0

1. AND combinations that yield a "1" in the truth table.

2. OR the resultsof the AND gates.

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PracticeImplement the following truth table.

A B C

0 0 0

0 1 1

1 0 1

1 1 0

A

B C

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Another example:

X Y Z Output

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

We want to build a circuit that has 3 binary inputs.

This CKT is On if the inputs are X’Y’Z or X’YZ’ .

XYZ

Output

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XOR gate:A XOR B= A.B’+A’.B

A + B A B

0 0 0

0 1 1

1 0 1

1 1 0

A

B

A + B

A + B

A

BA.B’+A’.B

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DeMorgan's LawConverting AND to OR (with some help from NOT)

Consider the following gate:

A B

0 0 1 1 1 0

0 1 1 0 0 1

1 0 0 1 0 1

1 1 0 0 0 1

BA BA BA

Same as A+B

To convert AND to OR (or vice versa),

invert inputs and output.

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DeMorgan Law:

A+B= (A’ . B’)’

A.B=(A’+B’)’

A B A’ B’ A’.B’ (A’.B’)’

0 0 1 1 1 0

0 1 1 0 0 1

1 0 0 1 0 1

1 1 0 0 0 1

OR Truth table

A B A’ B’ A’+B’ (A’+B’)’

0 0 1 1 1 0

0 1 1 0 1 0

1 0 0 1 1 0

1 1 0 0 0 1

AND Truth table

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A’.B = (A+B’)’

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Build the following logical expression using AND, Not Gates only:

F=X.Y+Z’

=((X.Y)’.Z’’)’

=((X.Y)’.Z)’

Another example:

F= XYZ+Y’Z+XZ’

= ( (XYZ)’.(Y’Z)’.(XZ’)’ )’

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From Demorgans lawA+B= (A’.B’)’

(A+B)’= (A’.B’)’’=A’.B’

A.B= (A’+B’)’

(A.B)’= (A’+B’)’’=A’+B’

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Simplify the following boolean expressionF= (A’BC + C + A + D )’ = ( A’BCC’ + (A’BC)’C +A+D)’ = ( A’B. 0 + (A’BC)’C +A+D)’ = ( 0 + (A’BC)’C +A+D)’ = ( (A+B’+C’)C+A+D)’ = ( AC+B’C+C’C+A+D)’ = ( AC+B’C+ 0 + A +D)’ = (AC+A + B’C + D)’ = ( A + B’C + D)’ = A’ (B’C)’ D’ = A’ D’( B+C’) = A’BD’+A’C’D’

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Simplification using boolean algebra:We have the following truth table for logical circuit and we want to implement this in the minimum number of gates:

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

F=A’B’C+A’BC+AB’C’+AB’C+ABC’

= A’B’C+A’BC+AB’(C+C’)+ABC’

= A’C(B+B’) +AB’ +ABC’

= A’C+AB’+AC’(B+B’) ;we can reuse AB’C’

=A’C+AB’+AC’

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Another example:

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

F=A’B’C+A’BC+AB’C+ABC’+ABC

= A’C(B+B’)+AB’C+ABC’+ABC

= A’C + AC(B’+B) +ABC’

= A’C+AC+ AB(C+C’)

=A’C+AC+AB

= C(A+A’)+AB

= C+AB

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Karnaugh MapsKarnaugh map : is a representation for the truth table in a graphical way, which makes the simplification of any boolean function easier.

For 3 input boolean function the Karnaugh map will be as follows :

00 01 11 10

0A’B’C’

000

A’B’C

001

A’BC

011

A’BC’

010

1AB’C’

100

AB’C

101

ABC

111

ABC’

110

A

BC

As we can see, each cell represent one raw of the truth table

Next step is to fill the map using the truth table output.

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Simplification using Karnaugh:Let us resolve the previous examples using karnaugh map:

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

00 01 11 10

0 0 1 1 0

1 1 1 0 1A

BC

F=A’C+B’C+AC’

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Resolve the same example in another way:

00 01 11 10

0 0 1 1 0

1 1 1 0 1

BC

F=A’C+AB’+AC’

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Karnaugh map for 4 input boolean function

AB

CD00 01 11 10

00 0

0000

1

0001

3

0011

2

0010

01 4

0100

5

0101

7

0111

6

0110

11 12

1100

13

1101

15

1111

14

1110

10 8

1000

9

1001

11

1011

10

1010

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Assume we have the boolean function F with 4 inputs:F(A,B,C,D)= ∑ (0,1 ,4, 6, 8,11,13, 15)Make the truth table for this functionWrite the boolean equation for this function (Before simplification)Simplify this function using karnaugh map techniqueDraw the simplified equation.

00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

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SummaryMOS transistors are used as switches to implementlogic functions.

• N-type: connect to GND, turn on (with 1) to pull down to 0• P-type: connect to +2.9V, turn on (with 0) to pull up to 1

Basic gates: NOT, NOR, NAND• Logic functions are usually expressed with AND, OR, and NOT

Properties of logic gates• Completeness

can implement any truth table with AND, OR, NOT• DeMorgan's Law

convert AND to OR by inverting inputs and output

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Building Functions from Logic Gates

We've already seen how to implement truth tablesusing AND, OR, and NOT -- an example of combinational logic.

Combinational Logic Circuit• output depends only on the current inputs• stateless

Sequential Logic Circuit• output depends on the sequence of inputs (past and present)• stores information (state) from past inputs

We'll first look at some useful combinational circuits,then show how to use sequential circuits to store information.

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Decodern inputs, 2n outputs

A

B

Y0 1

Y1

Y2

Y3

0

0

0

1

11

01

1

11

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Decodern inputs, 2n outputs

• exactly one output is 1 for each possible input pattern

2-bitdecoder

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3x8 decoder

012

3

4

56

7

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Build the following truth table using Decoder and OR gate

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

3x8 decoder

012

3

4

56

7

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Multiplexer (MUX)n-bit selector and 2n inputs, one output

S1 S0

I0

I1

I2

I3

0 0

01

0 1

1

1

0

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Multiplexer (MUX)n-bit selector and 2n inputs, one output

• output equals one of the inputs, depending on selector

4-to-1 MUX

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Full AdderAdd two bits and carry-in,produce one-bit sum and carry-out.

S = A + B + Cin

Cout = A.B+A.C+B.C

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

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Full AdderAdd two bits and carry-in,produce one-bit sum and carry-out. A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

3x8 decoder

012

3

4

56

7

A

B

Cin

S

C

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Four-bit Adder

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Combinational vs. SequentialCombinational Circuit

• always gives the same output for a given set of inputsex: adder always generates sum and carry,

regardless of previous inputs

Sequential Circuit• stores information• output depends on stored information (state) plus input

so a given input might produce different outputs,depending on the stored information

• example: ticket counteradvances when you push the buttonoutput depends on previous state

• useful for building “memory” elements and “state machines”

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R-S Latch: Simple Storage ElementR is used to “reset” or “clear” the element – set it to zero.

S is used to “set” the element – set it to one.

If both R and S are one, out could be either zero or one.• “quiescent” state -- holds its previous value• note: if a is 1, b is 0, and vice versa

1

0

1

1

1

1

0

0

1

1

0

0

1

1

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Clearing the R-S latchSuppose we start with output = 1, then change R to zero.

Output changes to zero.

Then set R=1 to “store” value in quiescent state.

1

0

1

1

1

1

0

0

1

0

1

0

0

0

1

1

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Setting the R-S LatchSuppose we start with output = 0, then change S to zero.

Output changes to one.

Then set S=1 to “store” value in quiescent state.

1

1

0

0

1

1

0

1

1

1

0

0

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R-S Latch SummaryR = S = 1

• hold current value in latch

S = 0, R=1• set value to 1

R = 0, S = 1• set value to 0

R = S = 0• both outputs equal one• final state determined by electrical properties of gates• Don’t do it!

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Gated D-LatchTwo inputs: D (data) and WE (write enable)

• when WE = 1, latch is set to value of DS = NOT(D), R = D

• when WE = 0, latch holds previous valueS = R = 1

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RegisterA register stores a multi-bit value.

• We use a collection of D-latches, all controlled by a common WE.

• When WE=1, n-bit value D is written to register.

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Representing Multi-bit ValuesNumber bits from right (0) least significant bit LSb to left (n-1) most significant bit MSb

• just a convention -- could be left to right, but must be consistent

Use brackets to denote range:D[l:r] denotes bit l to bit r, from left to right

May also see A<14:9>, A14:9

especially in hardware block diagrams.

A = 0101001101010101

A[2:0] = 101A[14:9] = 101001

015

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MemoryNow that we know how to store bits,we can build a memory – a logical k × m array of stored bits.

•••

k = 2n

locations

m bits

Address Space:number of locations(usually a power of 2)

Addressability:number of bits per location(e.g., byte-addressable)

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22 x 3 Memory

addressdecoder

word select word WEaddress

writeenable

input bits

output bits

1 0 100

1

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22 x 3 Memory

addressdecoder

word select word WEaddress

writeenable

input bits

output bits

1 0 000

01 0 11 0 1

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IF we want to build a memory of size 1024 word each word 8 bit

a) What is the size of the decoder needed

b) How many d- flip flops do we need

c) How many And Gates do we need

d) How many OR gates do we need

e) How many inputs for the OR gates needed

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More Memory Details

This is not the way actual memory is implemented.• fewer transistors, much more dense,

relies on electrical properties

But the logical structure is very similar.• address decoder• word select line• word write enable

Two basic kinds of RAM (Random Access Memory)

Static RAM (SRAM)• fast, maintains data without power

Dynamic RAM (DRAM)• slower but denser, bit storage must be periodically refreshed

Also, non-volatile memories: ROM, PROM, flash, …

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State MachineAnother type of sequential circuit

• Combines combinational logic with storage• “Remembers” state, and changes output (and state)

based on inputs and current state

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

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Combinational vs. SequentialTwo types of “combination” locks

4 1 8 4

30

15

5

1020

25

CombinationalSuccess depends only onthe values, not the order in which they are set.

SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).

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StateThe state of a system is a snapshot ofall the relevant elements of the systemat the moment the snapshot is taken.

Examples:• The state of a basketball game can be represented by

the scoreboard.Number of points, time remaining, possession, etc.

• The state of a tic-tac-toe game can be represented bythe placement of X’s and O’s on the board.

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State of Sequential LockOur lock example has four different states,labelled A-D:

A: The lock is not open,and no relevant operations have been performed.

B: The lock is not open,and the user has completed the R-13 operation.

C: The lock is not open,and the user has completed R-13, followed by L-22.

D: The lock is open.

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State DiagramShows states and actions that cause a transition between states.

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Finite State MachineA description of a system with the following components:

1. A finite number of states

2. A finite number of external inputs

3. A finite number of external outputs

4. An explicit specification of all state transitions

5. An explicit specification of what causes eachexternal output value.

Often described by a state diagram.• Inputs may cause state transitions.• Outputs are associated with each state (or with each transition).

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The ClockFrequently, a clock circuit triggers transition fromone state to the next.

At the beginning of each clock cycle,state machine makes a transition,based on the current state and the external inputs.

• Not always required. In lock example, the input itself triggers a transition.

“1”

“0”

timeOneCycle

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Implementing a Finite State MachineCombinational logic

• Determine outputs and next state.

Storage elements• Maintain state representation.

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

Clock

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Storage: Master-Slave FlipflopA pair of gated D-latches, to isolate next state from current state.

During 1st phase (clock=1),previously-computed statebecomes current state and issent to the logic circuit.

During 2nd phase (clock=0),next state, computed bylogic circuit, is stored inLatch A.

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StorageEach master-slave flipflop stores one state bit.

The number of storage elements (flipflops) neededis determined by the number of states(and the representation of each state).

Examples:• Sequential lock

Four states – two bits• Basketball scoreboard

7 bits for each score, 5 bits for minutes, 6 bits for seconds,1 bit for possession arrow, 1 bit for half, …

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Complete ExampleA blinking traffic sign

• No lights on• 1 & 2 on• 1, 2, 3, & 4 on• 1, 2, 3, 4, & 5 on• (repeat as long as switch

is turned on)

DANGERMOVERIGHT

1

2

3

4

5

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Traffic Sign State Diagram

State bit S1 State bit S0

Switch onSwitch off

Outputs

Transition on each clock cycle.

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Traffic Sign Truth Tables

Outputs(depend only on state: S1S0)

S1 S0 Z Y X

0 0 0 0 0

0 1 1 0 0

1 0 1 1 0

1 1 1 1 1

Lights 1 and 2

Lights 3 and 4

Light 5

Next State: S1’S0’(depend on state and input)

In S1 S0 S1’ S0’

0 X X 0 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 1

1 1 1 0 0

Switch

Whenever In=0, next state is 00.

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Traffic Sign Logic

Master-slaveflipflop

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From Logic to Data PathThe data path of a computer is all the logic used toprocess information.

• See the data path of the LC-2 on next slide.

Combinational Logic• Decoders -- convert instructions into control signals• Multiplexers -- select inputs and outputs• ALU (Arithmetic and Logic Unit) -- operations on data

Sequential Logic• State machine -- coordinate control signals and data movement• Registers and latches -- storage elements

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LC-2 Data Path

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Chapter 3 Digital Logic Structures

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