Chapter 4Chapter 4
CMOS Process TechnologyCMOS Process Technology
Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory
July 5th, 2004; Revised - June 26th, 2006
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OutlinesOutlines Chip-Making Process
Photolithography
CMOS IC Fabrication Processes Simple Process
Modern Process
Packaging Technology
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Chip-Making Process: An OverviewChip-Making Process: An Overview
Crystal GrowthCrystal Growth PackagingPackaging
PhotolithographyPhotolithography
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Growing the Silicon IngotGrowing the Silicon Ingot
From Smithsonian, 2000
Most common technique is the Czochralski (CZ) Czochralski (CZ) method developed by Mitsubishi Materials Silicon in the 50’s Length: up to 2 m
Diameter: 200 mm (8”) to 300 mm (12”)
Weight: Over 225 kg.
Pulling takes up to hundred hours
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Czochralski (CZ) MethodCzochralski (CZ) Method
Crystal orientation is determined by seed orientationCrystal orientation is determined by seed orientation
Ingot diameter is determined by Ingot diameter is determined by temperaturetemperature, , orientationorientation, , and and extraction speedextraction speed..
Develop by Mitsubishi in the 50’s
1420 C1420 C
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Wafer ShapingWafer Shaping
Ingot is cut around and ground down Ingot is cut around and ground down into a uniform diameter (8”-12”), then into a uniform diameter (8”-12”), then sliced into wafers of about 1 mm thick.sliced into wafers of about 1 mm thick.
QuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.Wire Saw MachineWire Saw Machine
The sliced wafers are mechanically The sliced wafers are mechanically lapped by the use of alumina abrasive lapped by the use of alumina abrasive material to remove surface roughness material to remove surface roughness and damages caused by the saw cut and damages caused by the saw cut and to improve the flatness of the wafer.and to improve the flatness of the wafer.
QuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.
Lapping MachineLapping Machine
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Wafer Shaping (2)Wafer Shaping (2)
Mechanical damages induced during Mechanical damages induced during the previous processes are removed the previous processes are removed by chemical etching.by chemical etching.
The mechano-chemical polishing The mechano-chemical polishing process improves the flatness of the process improves the flatness of the wafer, making highly flat surface by wafer, making highly flat surface by the use of colloidal silica.the use of colloidal silica.
QuickTime™ and aTIFF (Uncompressed) decompressorare needed to see this picture.Wafer PolishersWafer Polishers
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The Target: CMOS InverterThe Target: CMOS Inverter
PolysiliconPolysilicon
InIn OutOut
VVDDDD
GNDGND
PMOSPMOS 2
Metal 1Metal 1
NMOSNMOS
ContactsContacts
N WellN Well
LayoutLayout
OutOutInIn
VVDDDD
PMOSPMOS
NMOSNMOS
SchemeticSchemetic
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Current CMOS StructureCurrent CMOS Structure
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Define active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
CMOS Process at a GlanceCMOS Process at a Glance
One full photolithographyphotolithography sequence per layer (mask)
Built (roughly) from the bottom up
5 5 metal 2metal 2
4 4 metal 1metal 1
2 2 polysiliconpolysilicon
3 3 source and drain diffusionssource and drain diffusions
11 tubs (aka wells, active areas)tubs (aka wells, active areas)
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Planarization: Polishing the WafersPlanarization: Polishing the Wafers
From Smithsonian, 2000
CMP (Chemical-Mechanical Planarization)CMP (Chemical-Mechanical Planarization) - Essential to keep the - Essential to keep the surface of the wafer approximately flat between processing surface of the wafer approximately flat between processing steps.steps.
liquid carrier with a liquid carrier with a suspended abrasive suspended abrasive component such as component such as aluminum oxide or aluminum oxide or silicasilica
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OutlinesOutlines Chip-Making Process
Photolithography Photolithography
CMOS IC Fabrication Processes Simple Process
Modern Process
Packaging Technology
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PhotolithographyPhotolithography An IC consists of
several layers of material that are manufactured in successive steps.
PhotolithographyPhotolithography is used to selectively process the layers, where the 2-D mask geometry is copied on the surface.
PhotoPhoto + + LithoLitho + + GraphyGraphy (Light) (Stone) (Writing)(Light) (Stone) (Writing)
== “Writing Stone with Light”“Writing Stone with Light”
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oxide growthoxide growthoptical optical
maskmask
photoresist coatingphotoresist coatingphotoresist photoresist removal removal (ashing)(ashing)
spin, rinse, dryspin, rinse, dry acid etchacid etch
photoresist photoresist development development
stepper stepper exposureexposure
Photolithographic ProcessPhotolithographic Process
Ion implantationPlasma etching
Metal deposition
Typical operations in a single Typical operations in a single photolithographic processphotolithographic process
process process stepstep
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Oxide Growth/Oxide DepositionOxide Growth/Oxide Deposition Oxidation of the silicon
surface creates a SiO2 layer that acts as an insulator.
Oxide layers are also used to isolate metal interconnections.
An annealing step is required to An annealing step is required to restore the crystal structure after restore the crystal structure after thermal oxidation.thermal oxidation.
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Photoresist Deposition/CoatingPhotoresist Deposition/Coating The surface of the
wafer is coated with a photosensitive material, the photoresistphotoresist.
The mask pattern is developed on the photoresist, with UV light exposure.
Depending on the type of the photoresist (negativenegative or positivepositive), the exposed or unexposed parts of the photoresist change their property and become resistant to certain types of solvents.
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Stepper ExposureStepper Exposure
The mask pattern is developed on the photoresist, with UV light exposureUV light exposure.
Glass Mask (reticle) containing the patterns to be transferred is brought in close proximity to the wafer
A Mask SampleA Mask Sample
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Photoresist DevolopmentPhotoresist Devolopment The wafers are developed in either an acid or
base solution to remove the nonexposed (exposed) areas of the photoresist.
Once the exposed photoresist is removed, the wafer is “soft baked” at a low temperature to harden the photoresist.
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Acid EtchingAcid Etching Etching is a common process to
pattern material on the surface.
Once the desired shape is patterned with photoresist, the unprotected areas are etched away.
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Spin, Rinse, and DrySpin, Rinse, and Dry A special tool called SRD is used to clean the
wafers after each acid etch step
Use de-ionized water to remove any residue chemical substance.
Use nitrogen because it has no reaction with the silicon.
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Various Process StepsVarious Process Steps The exposed area can now be subjected to a wide range
of process steps Ion implantation
Plasma (Dry) etching
Metal (Thin Film) deposition
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Ashing - Photoresist RemovalAshing - Photoresist Removal A high-temperature plasma is used to selectively
remove the remaining photoresist without damaging previous layers.
After ashing the wafer is ready for the next round of photolithography.
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Photolithographic Process ExamplePhotolithographic Process Example
Si-substrate
Silicon base material
1. After oxidation1. After oxidation
SiOSiO22
Si-substrate
2. After deposition of 2. After deposition of negative photoresistnegative photoresist
PhotoresistPhotoresistSiOSiO22
Si-substrate
Si-substrate
3. Stepper exposure3. Stepper exposure
UV-light
Patternedoptical mask
Exposed resist
4. Photoresist Devolop and Bake4. Photoresist Devolop and Bake
Si-substrate
Exposed resist
heatheat
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Photolithographic Process ExamplePhotolithographic Process Example
Si-substrate
SiO2
8. Final result after 8. Final result after removal of resist removal of resist (ashing)(ashing)
6. After etching and spin, rinse and dry.6. After etching and spin, rinse and dry.
Si-substrate
SiO2
Hardened resist
5. After development and 5. After development and etching of resist, chemical or etching of resist, chemical or plasma etch of SiOplasma etch of SiO22
SiO2
Si-substrate
Hardened resist
Chemical or plasmaetch
• Step 7 is optional in this Step 7 is optional in this example. The step is need example. The step is need only in implanting a well or only in implanting a well or doping polysilicon doping polysilicon
• Planarization step is applied Planarization step is applied at least once in a cycle of at least once in a cycle of photolithography photolithography
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1000 C1000 C
DiffusionDiffusion:: Wafer is exposed to Wafer is exposed to gas containing dopant under gas containing dopant under high temperature (900-1100 C)high temperature (900-1100 C)
Ion ImplantationIon Implantation:: A beam of A beam of dopant ions is swept over the dopant ions is swept over the surface - causing damage to surface - causing damage to substrate, need annealingsubstrate, need annealing
Purified Purified Ion beamIon beam
Diffusion and Ion ImplantationDiffusion and Ion Implantation Change the electrical characteristics of silicon locally by adding
doping agents to the exposed area.
The dopant ions penetrate the surface with a penetration depth that is proportional to their kinetic energy.
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OutlinesOutlines Chip-Making Process
Photolithography
CMOS IC Fabrication ProcessesCMOS IC Fabrication Processes Simple ProcessSimple Process
Modern Process
Packaging Technology
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Photolithography MasksPhotolithography Masks Each photolithography step during fabrication
must be defined by a separate photolithography mask.
Each mask layer must be drawn (either manually or using a design automation tool) according to the layout design ruleslayout design rules.
The combination (superposition) of all necessary mask layers completely defines the circuit to be fabricated.
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Layout Design RulesLayout Design Rules To allow reliable fabrication of each structure,
the mask layers must conform to a set of geometric layout design rules.
Usually, the rules (for example: minimum distance and/or separation between layers) are expressed as multiples of a scaling factor - lambda (lambda ()) - minimum resolution of a technology
For each different fabrication technology, lambda factor can be different.
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Examples of Layout Design RulesExamples of Layout Design Rules
A Minimum-Sized TransistorA Minimum-Sized Transistor
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More Example of Layout RulesMore Example of Layout Rules
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Self-Aligned ProcessSelf-Aligned Process
1. Create thin oxide in the 1. Create thin oxide in the ““activeactive” regions, thick ” regions, thick elsewhereelsewhere
4. 4. Implant dopantImplant dopant (see previous slides(see previous slides))
3. Etch thin oxide from active 3. Etch thin oxide from active region (poly acts as a mask region (poly acts as a mask for the diffusion)for the diffusion)
2. Deposit 2. Deposit polysiliconpolysilicon
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Notes on Self-Aligned ProcessNotes on Self-Aligned Process Polysilicon gate is patterned beforebefore source and
drain are created, Thereby defining the precise location of the channel
region and the locations of the source and drain regions relative to the gate.
And consequently reducing parasitic capacitances in the transistor.
However, this technique cannot completely stop lateral diffusion Accounts for difference between drawn transistor difference between drawn transistor
dimensions and actual onesdimensions and actual ones..
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Simplified CMOS Inverter ProcessSimplified CMOS Inverter Process
cut line
p well
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P-Well MaskP-Well Mask
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Active MaskActive Mask
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Poly MaskPoly Mask
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P+ Select (Source/Drain) MaskP+ Select (Source/Drain) Mask
Self-Aligned GateSelf-Aligned Gate
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N+ Select (Source/Drain) MaskN+ Select (Source/Drain) Mask
Self-Aligned GateSelf-Aligned Gate
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Contact MaskContact Mask
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Metal MaskMetal Mask
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OutlinesOutlines Chip-Making Process
Photolithography
CMOS IC Fabrication ProcessesCMOS IC Fabrication Processes Simple Process
Modern ProcessModern Process
Packaging Technology
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A Modern CMOS ProcessA Modern CMOS Process
Both n- and p- wells grown on top of an epitaxial layer Both n- and p- wells grown on top of an epitaxial layer (using trench isolation areas of SiO(using trench isolation areas of SiO22))
Dual-Well Trench-Isolated CMOSDual-Well Trench-Isolated CMOS
p-
p-epi
p well n well
p+n+
gate oxide
Al (Cu)
tungsten
SiO2
SiO2
TiSi2
field oxide
TrenchTrench
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Modern CMOS Process Walk-ThroughModern CMOS Process Walk-Through
p+
After plasma etch of insulating trenches using the inverse of the active area mask
After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)p+
p-epiSiO2
3Si N
4
Base material: p+p+ substrate with p-epip-epi layer
p+
p-epi
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Modern CMOS Process Walk-Through Modern CMOS Process Walk-Through (2)(2)
SiO2After trench filling, CMP planarization, and removal of sacrificial nitride
After n-well and VTp adjust implants
n
After p-well and VTn adjust implants
p
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Modern CMOS Process Walk-Through Modern CMOS Process Walk-Through (3)(3)
After polysilicon deposition and etch
poly(silicon)
After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon.
p+n+
After deposition of SiO2 insulator and contact hole etch
SiO2
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Modern CMOS Process Walk-Through Modern CMOS Process Walk-Through (4)(4)
After deposition and patterning of first Al layer.
Al
After deposition of SiO2 insulator, etching of via’s, deposition and patterning of second layer of Al.
SiO2
Al
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State-of-the-Art ExampleState-of-the-Art Example
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Interconnect Delay CrisisInterconnect Delay Crisis As technology shrinks, interconnect delay has
more and more impact on the overall design performance. Wire delay now accounts for > 40% of total delay in a
circuit
There are 2 key points where interconnect delay can be reduced. Use low-resistivity materialUse low-resistivity material
Copper in stead of Aluminum (what is the best conductor?)
Use insulator material with a lower dielectric Use insulator material with a lower dielectric constant (k) than SiOconstant (k) than SiO2 2 (Reduce coupling)
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Advanced MetallizationAdvanced Metallization
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Silicon-on-Insulator (SOI)Silicon-on-Insulator (SOI) The idea is to construct the transistor structures in a very thin layer
of silicon on an insulatinginsulating material rather than a common substrate as in bulk CMOS process.
This reduces parasitic capacitances and eliminates substrate noise coupling.
Insulator (SiOInsulator (SiO22))
TransistorTransistor
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SOI ExampleSOI Example
22% improvement in performance22% improvement in performance
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Fabrication Cost - Moore’s LawFabrication Cost - Moore’s Law
Initial investment of new facilities is too expensive!Initial investment of new facilities is too expensive!
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OutlinesOutlines Chip-Making Process
Photolithography
CMOS IC Fabrication Processes Simple Process
Modern Process
Packaging TechnologyPackaging Technology
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Packaging TechnologyPackaging Technology Many high-performance chips failed stringent
test specifications after packaging because the designer (usually novice!) have not included various effects of packaging constraints and parasitics into their designs. Ground planes, power planes, and bonding pads
greatly affect the behavior of on-chip power and ground bus.
Length of bonding wire and lead length in a package generate a voltage drop in the output circuit.
Inappropriate type of package body can cause thermal runaway and hence damage the ICs.
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Packaging RequirementsPackaging Requirements ElectricalElectrical: Low parasitics
Low capacitance and Inductance
MechanicalMechanical: Reliable and robust Moisture-proof
High pin density
ThermalThermal: Efficient heat removal High thermal conductivity
Low thermal expansion coefficient
EconomicalEconomical: Cheap
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Lead Frame
Substrate
Die
Pad
Wire Bonding
Bonding TechniquesBonding TechniquesWire BondingWire Bonding
High and unpredictable value of parasiticsHigh and unpredictable value of parasitics
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Tape-Automated Bonding (TAB)Tape-Automated Bonding (TAB)
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprockethole
Polymer film
Leadframe
Testpads
Polymer Tape with imprinted Polymer Tape with imprinted Wiring patternWiring pattern
(a) Polymer Tape with imprinted
(b) Die attachment using solder bumps.
wiring pattern.
Substrate
Die
Solder BumpFilm + Pattern
Sprockethole
Polymer film
Leadframe
Testpads
Die Attachment using Die Attachment using Soldier bumpsSoldier bumps
Highly Automated, Highly Automated, Eliminate long bonding Eliminate long bonding wireswires
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Solder bumps
Substrate
Die
Interconnect
layers
Flip-Chip BondingFlip-Chip Bonding
Alleviate power- and clock-distribution problemAlleviate power- and clock-distribution problem
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Package-to-Board InterconnectPackage-to-Board Interconnect
(a) Through-Hole Mounting (b) Surface Mount
Through-Hole MountingThrough-Hole Mounting
(a) Through-Hole Mounting (b) Surface Mount
Surface MountingSurface Mounting
Sturdy, Sturdy, Mechanically reliably,Mechanically reliably,Lower packaging densityLower packaging density
Difficult to mount Difficult to mount Mechanical weaker structureMechanical weaker structureHigher packaging densityHigher packaging density
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PGA - Pin Grid ArrayPGA - Pin Grid Array
DIP - Dual-In-Line PinDIP - Dual-In-Line Pin
QFP - Quad Flat PackQFP - Quad Flat Pack
Package TypesPackage Types
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Package and Bonding ParametersPackage and Bonding Parameters
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Multi-Chip ModulesMulti-Chip Modules Multiple chips are
assembled on a common substrate contained in a single package A large number of critical
interconnections between the chips can be made withinwithin the package.
AdvantagesAdvantages are savings of overall system size, reduced package lead counts, and faster operation.