Chapter 4: The Embedded Computing Platform Computer as Components Embedded Systems Laboratory Dept....

Chapter 4:The Embedded Computing

Platform

Computer as Components

Embedded Systems Laboratory

Dept. of Computer Science & Engineering

National Sun Yat-Sen University

Presenter: Chung-Fu Kao

4/9/2002 The Embedded Computing System© C.-F. Kao2

Chapter view

CPU bus, I/O devices, and interfacing

The CPU system as a framework for understanding design methodology

Development environments and debugging

An alarm clock design


Typical PC hardware platform

CPU

CPU bus

memory

DMAcontroller

timers

businterface

bu

sin

terf

ace

high-speed bus

low-speed bus

device

device

intrctrl


Introduction

Computer platform Microprocessors I/O devices Memory

How to interconnect microprocessors and devices using the CPU bus

CPU

device

device

device

keyboard

display

memory?


The CPU bus

Wire vs. bus Wire: a 1-bit line between two devices

Bus: a collection of wires with a protocol

wiren

bus


Action

Bus protocol

The simplest bus protocol is the four-cycle handshake

time

enq

ack

data

1

2

3

4


Typical bus signals

Clock provides synchronization to the bus

components R/W’

true when bus is reading Address

a n1-bit bundle Data

a n2-bit bundle Data ready’


A typical microprocessor bus

the CPU can read/write devices or memory, bus devices of memory cannot initiate a transfer

CPU

Device 1 Device 1

memory

clockR/W’

data rdy’addressdata


Timing diagrams

time

A

B

C

zero

one

rising falling

stablechanging

10 ns

Timingconstraint


A simple transfer example


Transfer with ‘wait’ states


State diagrams for the bus read transaction

Getdata

Done

Address(start here)

See ack

Wait

CPU

Senddata

Releaseack

Address(start here)

ack

Wait

Device


Bus read state diagram

Getdata Done

Address(start here)

Wait

See ack

one data send/receiveper transfer cycle

How to speedupthe transfer ?


Burst transfer


Bus architectures: Tri-state design

1-bit tri-state design

System tri-state bus

enable

data_out

data_in

tri_out

… … …


Bus architectures: Multiplexing design

Data (W)MUX

ControlMUX

AddressMUX

select

ASBArbiter

AREQx1

AREQx3

AREQx2

BLOK

BWAIT

BnRES/BCLK

AGNTx1

AGNTx3

AGNTx2

BnRES/BCLK

ASBDecoder

BTRAN[1:0]

BA[31:0

BWRITE

BSIZE[1:0]

BPROT[1:0]

DSEL 1

DSEL n

DSEL 2

BERROR

BWAIT

BLAST

Data (R)MUX

ResponseMUX

Select-1

Master(s)

DecoderAddress bus

Data bus

Control (write, transfer type, size)

Slave(s)

Response (wait, last, error)

Select-2

[31:28]

End of Chapter 4.2.1


I/O techniques

Programmed I/O data are exchanged between CPU and I/O CPU must wait until the I/O operation is

complete

Interrupt-driven I/O CPU can continues to execute other

instructions before I/O operation has completed

Direct Memory Access (DMA) CPU does not involve the I/O transfer


DMA: Direct Memory Access

The DMA controller includes 3 registers a starting address register a length register a status register

Cycle stealing

Data count

Data register

Address register

Control Logic

DMA REQ

INTR

DMA ACK

ReadWrite


Possible DMA configuration

(a) Single-Bus, Detached DMA

CPU MEMI/OI/ODMAmodule

. . .

(b) Single-Bus, Integrated DMA-I/O

I/O

DMAmodule

I/O I/O

CPU MEMDMAmodule

CPU MEM

System bus

DMAmodule

I/O bus

I/O I/OI/O

(c) I/O bus


Slave BIU

Timer

Bus example: ARM bus

ARM supports an on-chip bus: AMBA Advanced Microcontroller Bus Architecture

Master BIU

CPU

Master BIU

Master N

AHB/ASB BUS

Decoder

Slave BIU

On-chipRAM

Slave BIU

OtherAPB slaves

Arbiter

……

InterruptController

BIU: Bus Interface Unit

APB BUSAPBBridge

Slave BIU

LED


AMBA features

Pipelining only AHB or ASB

Burst transfers 1, 4, 8, 16-beat transfer

Split transactions release the current transfer

Multiple bus masters


Bus components devices

Slave BIU

Timer

Master BIU

CPU

Master BIU

Master N

AHB/ASB BUS

Decoder

Slave BIU

On-chipRAM

Slave BIU

OtherAPB slaves

Arbiter

……

InterruptController

BIU: Bus Interface Unit

APB BUSAPBBridge

Slave BIU

LED


Memory device organization

The most basic way to characterize a memory is by its capacity

A 4-Mbit memory aspect ratio : as a 1M x 4-bit array, MAX of 220 different

addresses as a 4M x 1-bit array, MAX of 222 different

addresses


Random-Access Memories (RAMs)

There are two major categories of RAM: static RAM (SRAM) dynamic RAM (DRAM)

The differences between SRAM and DRAM SRAM is faster than DRAM SRAM consumes more power than DRAM more DRAM can be put on a single chip DRAM values must be periodically

refreshed


SRAM

SRAM doesn’t need CLOCK signal Block diagram

Timing diagram

SRAM

32K x 8

address

chip select

output enable

write enable

Data_in

Data_out

15

8

8

CS’

R/W’

Adrs

Data From SRAM From CPU


DRAM

Single transistor and capacitor per bit

CPU address bus is split into a row and a column address

NO clock Refreshed

CAS-before-RAS refresh

DRAM

address

chip selectoutput enable

write enableData_in

Data_out

15

8

8


Other DRAMs

FPM DRAM fast page mode switch (burst)

EDO DRAM extended data out

SDRAM synchronous DRAM


Read-Only Memories (ROMs)

Read only, cannot write any data to ROMs ROMs can store data without any power ROM size

height: n input line, consists 2n addressable entries

width: the number of bits in each addressable entry

A ROM can encode a collection of logic functions directly from the truth table


ROMs

Mask ROM Programmable ROM (PROM)

write once Erasable Programmable ROM (EPROM)

can be erased using UV light and then reprogrammed

Electrically Erasable Programmable ROM using high voltages for erasure and

reprogramming Flash ROM


I/O devices

Timers / counters A/D and D/A converters Keyboards LEDs Displays Touchscreens


Timers and counters

Very similar: a timer is incremented by a periodic signal a counter is incremented by an

asynchronous, occasional signal

Rollover causes interrupt


Watchdog timer

Watchdog timer is periodically reset by system timer

If watchdog is not reset, it generates an interrupt to reset the host (CPU)

CPU

reset

WatchdogTimer

time-out


A/D and D/A converters

Analog/digital (A/D) or digital/analog (D/A) converters (ADC/DAC)

To interface non-digital devices to embedded systems

A typical A/D interface has two major digital inputs a data port a clock input


DAC


ADC


Keyboards

Switch de-bouncing

Encoded keyboard An array of switches is read by an encoder

row


LEDs

Light-emitting diodes (LEDs)

+5 V

+

Anode (+)

Cathode (-)


Displays

Common use: 7-segment LCD display

Other high-resolution displays cathode ray tube (CRT) liquid crystal display (LCD)

• passive matrix• active matrix


Touchscreens

Includes input and output device

Input device is a two-dimensional voltmeter

X


Touchscreen position sensing

ADC

voltage

Push↓

spacer ball

conductive sheets

end of chapter 4.5


Design with microprocessors

System architecture

Hardware design

The PC as a platform

Debugging

Manufacturing testing


System architecture – Hardware

Hardware elements CPU bus memory I/O devices: networking, sensors, etc.


System architecture – Software

Functional description must be broken into pieces: conceptual organization performance testability maintenance

Consider the H/W-S/W trade-off using DMA to move data rather than a

programmed loop


Hardware design

targetsystem

host systemserial line

Hardware: evaluation board Software:

cross compiler:• compiles code on host for target system.

cross debugger:• displays target state, allows target system to be

controlled.


Evaluation board


The PC as a platform

Advantages: cheap and easy to get rich and familiar software environment

Disadvantages: requires a lot of hardware resources not well-adapted to real-time high power consumption


Typical PC hardware platform

CPU

CPU bus

memory

DMAcontroller

timers

businterface

bu

sin

terf

ace

high-speed bus

low-speed bus

device

device

intrctrl


Typical busses

ISA (Industry Standard Architecture) original IBM PC bus, low-speed by today’s sta

ndard. PCI (Peripheral Component Interconnect)

standard for high-speed interfacing 33 or 66 MHz.

USB (Universal Serial Bus), IEEE 1394 (Firewire)

relatively low-cost serial interface with high speed.


Software elements

IBM PC uses BIOS (Basic I/O System) to implement low-level functions: boot-up minimal device drivers

BIOS has become a generic term for the lowest-level system software


Debugging embedded systems

Challenges: target system may be hard to observe target may be hard to control may be hard to generate realistic inputs setup sequence may be complex


Software debuggers

A monitor program residing on the target provides basic debugger functions

Debugger should have a minimal footprint in memory

User program must be careful not to destroy debugger program, but , should be able to recover from some damage caused by user code


Breakpoints

A breakpoint allows the user to stop execution, examine system state, and change state

Replace the breakpointed instruction with a subroutine call to the monitor program


ARM breakpoints

0x400 MUL r4,r6,r60x404 ADD r2,r2,r40x408 ADD r0,r0,#10x40c B loop

uninstrumented code

0x400 MUL r4,r6,r60x404 ADD r2,r2,r40x408 ADD r0,r0,#10x40c BL bkpoint

code with breakpoint


Breakpoint handler actions

Save registers Allow user to examine machine Before returning, restore system state

safest way to execute the instruction is to replace it and execute in place

put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint (pp. 222-223)


In-circuit emulators

A microprocessor in-circuit emulator is a specially-instrumented microprocessor

Allows you to stop execution, examine CPU state, modify registers


Logic analyzers

A logic analyzer is an array of low-grade oscilloscopes:


Manufacturing testing

Goal: ensure that manufacturing produces defect-free copies of the design

Can test by comparing unit being tested to the expected behavior but running tests is expensive

Maximize confidence while minimizing testing cost


Testing concepts

Yield: proportion of manufactured systems that work proper manufacturing maximizes yield proper testing accurately estimates yield

Field return: defective unit that leaves the factory.


Faults

Manufacturing problems can be caused by many thing

Fault model: model that predicts effects of a particular type of fault

Fault coverage: proportion of possible faults found by a set of test having a fault model allows us to determine

fault coverage


Software vs. hardware testing

When testing code, we have no fault model we verify the implementation, not the

manufacturing simple tests work well to verify software

manufacturing

Hardware requires manufacturing tests in addition to implementation verification


Hardware fault models

Stuck-at 0/1 fault model: output of gate is always 0/1

0 01 0


Combinational testing

Every gate can be stuck-at-0, stuck-at-1 Usually test for single stuck-at-faults

one fault at a time multiple faults can mask each other

We can generate a test for a gate by: controlling the gate’s input observing the gate’s output through other

gates


Sequential testing

A state machine is combinational logic + registers

Sequential testing is considerably harder a single stuck-at fault affects the machine

on every cycle fault behavior on one cycle can be masked

by same fault on other cycles


Scan chains

A scannable register operates in two modes: normal scan

• forms an element in a shift register


Scan chain cell

SEL

MUX

SEL

MUX

BSR PDR

Input pin

scan

Scan input

Shiftclock

Updateclock

Scanoutput

EXTESTINTEST

Input signalto logic


Boundary scan

IEEE Std. 1149.1 JTAG boundary scan

Serial data in

Serial data out

System interconnectSerial test interconnect


Embedded ICE

ICE

TAPController

InstructionRegister

DecodeLogic

BDU

Microprocessor Core

BreakpointScan Register

Bypass Register

TCK

TMS

TDI

Select Unit

address dataInterface

breakpoint

mode clock

MUX

externaldebug

TDO

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Chapter 4: The Embedded Computing Platform Computer as Components Embedded Systems Laboratory Dept....

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