Bräunl 2021 1 CHAPTER 4 Memory ROM: ”Read Only Memory” – Read only + Keeps data when powered down RAM: ”Random Access Memory” + Read/Write access – Loses data when powered down Addresses are used to locate words in memory Bräunl 2021 2 1. ROM • Will keep its contents when power is off • Contents cannot be changed • Used for system boot • Types: ROM, PROM, EPROM, EEPROM/Flash Bräunl 2021 ROM ROM A D data address CSOE10 8 3 Address Chip Select Data Output Enable Bräunl 2021 4 ROM • ROM Read Only Memory • Mask (data) supplied by customer • Mass production • Can never be changed • PROM Programmable ROM • programmable ROM • comes “empty” (E.g. all bits are 1) • can be programmed (“burned”) by supplying certain voltages to a specific pin • “Burning” of fuses (wires) within chip, setting individual bits to 0 • Once a bit is flipped, it can never be changed • EPROM Erasable Programmable ROM • Original state can be restored, ~ 20mins UV exposure • EEPROM (Flash) Electronically Erasable Programmable ROM • Can be electrically programmed/erased many times (~ 10,000) • “In circuit programming” (e.g. for system parameters in computer system) • Alternative solution: static RAM + battery backup à runs out after some time
Transcript
Bräunl 2021 1
CHAPTER 4 Memory
ROM: ”Read Only Memory”– Read only+ Keeps data when powered down
RAM: ”Random Access Memory”+ Read/Write access– Loses data when powered down
Addresses are used tolocate words in memory
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1. ROM
• Will keep its contents when power is off• Contents cannot be changed• Used for system boot• Types: ROM, PROM, EPROM, EEPROM/Flash
Bräunl 2021
ROM
ROMA D
dataaddress
CS� OE�
10 8
3
Address Chip SelectData Output Enable
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ROM• ROM Read Only Memory
• Mask (data) supplied by customer• Mass production• Can never be changed
• PROM Programmable ROM• programmable ROM• comes “empty” (E.g. all bits are 1)• can be programmed (“burned”) by supplying certain voltages to a specific pin• “Burning” of fuses (wires) within chip, setting individual bits to 0• Once a bit is flipped, it can never be changed
• EPROM Erasable Programmable ROM• Original state can be restored, ~ 20mins UV exposure
• EEPROM (Flash) Electronically Erasable Programmable ROM• Can be electrically programmed/erased many times (~ 10,000)• “In circuit programming” (e.g. for system parameters in computer system)• Alternative solution: static RAM + battery backup à runs out after some time
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ROM ImplementationExample: ROM with 8 bytes contents
2. RAM• Will lose its contents when power is off• Contents can be changed any time• Can store programs or data• Writing data to a location (“address”) overwrites
old data contents• Types: Static, Dynamic
Static RAM– Static RAM keeps data as long as power is on
Dynamic RAM– Dynamic RAM “leaks” memory contents over short time period,
needs periodic “refresh” à periodical read/write all cells
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RAM
RAMCS� R/W� OE�
A Ddataaddress
10 8
10
Address Chip SelectData Read / Write
Output Enable
Easy to build – will show laterLike FF with D and Q on same pin,but R/W’ to distinguish between
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RAM ImplementationSimilar to ROM, but replace connection element • by active switch
data line Capacitor: no change (empty) = 0 charged = 1
address line
12
RAM Implementation2. SRAM (static RAM, no �refresh� required, 6 FETransistors)
CMOS = complementary metal oxide silicon
address
data' data
data + data� required, since n-channel pass transistors conduct only zeroes well
Bräunl 2021 Diagram: IBM
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3. Memory Size – 1 bit
MemData
Here ROM shown, but same for RAMMem = 1 cell = 1 bit (=1 flip-flop)
Single bit
Smallest m
emory possi
ble
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Memory Size – 1 Byte (= 8 bits)
Mem = 8 bits
MemData
MemData
MemData
MemData
MemData
MemData
MemData
MemData
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Memory Size – 1 Byte (= 8 bits)
Mem .
8 Data Lines = Data Bus
Mem = 8 bits Bräunl 2021 16
Memory Size – 1 Byte (= 8 bits)
Mem8
Data Bus
Mem = 8 bits
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Memory Size – 2 Bytes
Mem
Data Bus
Mem = 2*8 = 16 bits
Mem
enable
enable
• 2 Outputs coming together on the same line!• Only one device is allowed to send data at a timeØ Enable/disable mechanism via tri-state gates required
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Memory Size – 2 Bytes
Mem
8 Data Bus
Mem = 2*8 = 16 bits
Mem
enable
enable 8
8
• 2 Outputs coming together on the same line!• Only one device is allowed to send data at a timeØ Enable/disable mechanism tri-state gates required
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Memory Size – 2 Bytes
Mem
Mem = 2*8 = 16 bits
Enable (Address)
Mem
8 Data Bus8
8
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Memory Size – 2 Bytes
Mem
Mem = 2*8 = 16 bits
Enable (Address)0
Mem
Enable=0
Enable=1
8 Data Businactive
0
1
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Memory Size – 2 Bytes
Mem
Mem = 2*8 = 16 bits
Enable (Address)1
Mem
8 Data Bus8
8Enable=0
Enable=1
inactive
1
0
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Memory Size – 2 Bytes
8
Data Bus
Mem = 2*8 = 16 bits
1 Address Line
Mem
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Memory Size – 4 Bytes
8
Data Bus
Mem = 4*8 = bits
2 Address Lines
Mem
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Memory Size – 8 Bytes
8
Data Bus
Mem = 8*8 = 64 bits
3 Address Lines
Mem
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Memory Size – 2n Bytes
n
Address Bus
Mem8
Data Bus
Mem = 2n * 8 bits
• 1 addr. line ® 2 data cells• 2 addr. lines ® 4 data cells• 3 addr. lines ® 8 data cells
…• n addr. lines ® 2n data cells
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• Control lines– Chip-SELECT’ activate memory chip– Output-Enable’ write data to bus (req. for multiple modules)
– Read/Write’ activate writing (RAM only)
Mem2n * m bits
Address
n
Data
m
CS’ R/W’ OE’
4. Memory Control
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01
Mem2n * m bits
Address
n
Data
m
CS’ R/W’ OE’(don’t care)
Mem2n * m bits
Address
n
Data
m
CS’ R/W’ OE’
Mem2n * m bits
Address
n
Read Data
m
CS’ R/W’ OE’
Mem2n * m bits
Address
n
Write Data
m
CS’ R/W’ OE’(don’t care)
Memory Control
Bräunl 2021 28Source: MIT 6.111 Notes
Chip enable
Output enable
Chip enable
READ CYCLE
WRITE CYCLE
copy data to memory
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Mem2n * m bits
CS’ R/W’ OE’
Address
n
Data
m
Memory and CPU
CPUm data lines
n address lines
Data
m
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5. Addresses• Smallest information unit is one bit,
can be “0” or “1”.• Eight bits are called one Byte.
•
most significant bit … least significant bit
• Memory cell width is called a word,e.g. 8, 16, 32 bits
• Note the difference: k=1’000, K=1’024 (same for M, G, T)!• Size of a memory module is calculated as:
size = number of cells * cell size[remember: area = height * width]
• Example: A Memory module has 2M cells with 16bits per cell.What is its size in MB?2M * 2 Bytes = 4MB
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• The number of cells in a memory moduledetermines the number of address lines required.
• Memory module sizes are always powers of 2– 1 cell à no address line required– 2 cells à 1 address line– 4 cells à 2 address lines– …– 1024 = 1K cells à 10 address lines– 1M cells à 20 address lines– 1G cells à 30 address lines– 2n cells à n address lines
Mem2n cells
Address
n
Address Space
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• The number of bits in a memory celldetermines the number of data lines required.
• One data line is required per bit• Typical memory cell sizes are 4, 8, 16, 32, 64
Mem2n * m bits
Address
n
Data
m
Address Space
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Address SpaceExample:• 8 cells, 2 Bytes per cell
Total 16 Bytes• 3 address lines• 16 data lines
Question:• How many address lines has a
4M * 1Byte memory module?• How many data lines has this
module?
4M = 22*220 = 222 à 22
1Byte = 8 bits
Address$0$1$2$3$4$5$6$7
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Address Space
Example: Standard 8 bit controller
• 16 address bits
Example: Motorola 68.332
• 27 address bits, 16 data bits
® max. 64KB memory size
® max. 128M * 2B words = 256MB memory size
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QUIZ – Address, Memory
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How many address lines does a4MB RAM have (word size: byte) ?
A. 8
B. 14
C. 22
D. depends
http://robotics.ee.uwa.edu.au/quiz/
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How many data lines does a4MB RAM have (word size: byte) ?
